2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol
[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
51 struct ath_atx_tid
*tid
, struct sk_buff
*skb
);
52 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
53 int tx_flags
, struct ath_txq
*txq
);
54 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
55 struct ath_txq
*txq
, struct list_head
*bf_q
,
56 struct ath_tx_status
*ts
, int txok
);
57 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
58 struct list_head
*head
, bool internal
);
59 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
60 struct ath_tx_status
*ts
, int nframes
, int nbad
,
62 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
64 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
66 struct ath_atx_tid
*tid
,
76 /*********************/
77 /* Aggregation logic */
78 /*********************/
80 void ath_txq_lock(struct ath_softc
*sc
, struct ath_txq
*txq
)
81 __acquires(&txq
->axq_lock
)
83 spin_lock_bh(&txq
->axq_lock
);
86 void ath_txq_unlock(struct ath_softc
*sc
, struct ath_txq
*txq
)
87 __releases(&txq
->axq_lock
)
89 spin_unlock_bh(&txq
->axq_lock
);
92 void ath_txq_unlock_complete(struct ath_softc
*sc
, struct ath_txq
*txq
)
93 __releases(&txq
->axq_lock
)
95 struct sk_buff_head q
;
98 __skb_queue_head_init(&q
);
99 skb_queue_splice_init(&txq
->complete_q
, &q
);
100 spin_unlock_bh(&txq
->axq_lock
);
102 while ((skb
= __skb_dequeue(&q
)))
103 ieee80211_tx_status(sc
->hw
, skb
);
106 static void ath_tx_queue_tid(struct ath_softc
*sc
, struct ath_txq
*txq
,
107 struct ath_atx_tid
*tid
)
109 struct list_head
*list
;
110 struct ath_vif
*avp
= (struct ath_vif
*) tid
->an
->vif
->drv_priv
;
111 struct ath_chanctx
*ctx
= avp
->chanctx
;
116 list
= &ctx
->acq
[TID_TO_WME_AC(tid
->tidno
)];
117 if (list_empty(&tid
->list
))
118 list_add_tail(&tid
->list
, list
);
121 static struct ath_frame_info
*get_frame_info(struct sk_buff
*skb
)
123 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
124 BUILD_BUG_ON(sizeof(struct ath_frame_info
) >
125 sizeof(tx_info
->rate_driver_data
));
126 return (struct ath_frame_info
*) &tx_info
->rate_driver_data
[0];
129 static void ath_send_bar(struct ath_atx_tid
*tid
, u16 seqno
)
134 ieee80211_send_bar(tid
->an
->vif
, tid
->an
->sta
->addr
, tid
->tidno
,
135 seqno
<< IEEE80211_SEQ_SEQ_SHIFT
);
138 static void ath_set_rates(struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
141 ieee80211_get_tx_rates(vif
, sta
, bf
->bf_mpdu
, bf
->rates
,
142 ARRAY_SIZE(bf
->rates
));
145 static void ath_txq_skb_done(struct ath_softc
*sc
, struct ath_txq
*txq
,
148 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
149 struct ath_frame_info
*fi
= get_frame_info(skb
);
155 txq
= sc
->tx
.txq_map
[q
];
156 if (WARN_ON(--txq
->pending_frames
< 0))
157 txq
->pending_frames
= 0;
160 txq
->pending_frames
< sc
->tx
.txq_max_pending
[q
]) {
161 if (ath9k_is_chanctx_enabled())
162 ieee80211_wake_queue(sc
->hw
, info
->hw_queue
);
164 ieee80211_wake_queue(sc
->hw
, q
);
165 txq
->stopped
= false;
169 static struct ath_atx_tid
*
170 ath_get_skb_tid(struct ath_softc
*sc
, struct ath_node
*an
, struct sk_buff
*skb
)
172 u8 tidno
= skb
->priority
& IEEE80211_QOS_CTL_TID_MASK
;
173 return ATH_AN_2_TID(an
, tidno
);
176 static bool ath_tid_has_buffered(struct ath_atx_tid
*tid
)
178 return !skb_queue_empty(&tid
->buf_q
) || !skb_queue_empty(&tid
->retry_q
);
181 static struct sk_buff
*ath_tid_dequeue(struct ath_atx_tid
*tid
)
185 skb
= __skb_dequeue(&tid
->retry_q
);
187 skb
= __skb_dequeue(&tid
->buf_q
);
193 * ath_tx_tid_change_state:
194 * - clears a-mpdu flag of previous session
195 * - force sequence number allocation to fix next BlockAck Window
198 ath_tx_tid_change_state(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
200 struct ath_txq
*txq
= tid
->txq
;
201 struct ieee80211_tx_info
*tx_info
;
202 struct sk_buff
*skb
, *tskb
;
204 struct ath_frame_info
*fi
;
206 skb_queue_walk_safe(&tid
->buf_q
, skb
, tskb
) {
207 fi
= get_frame_info(skb
);
210 tx_info
= IEEE80211_SKB_CB(skb
);
211 tx_info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
216 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
218 __skb_unlink(skb
, &tid
->buf_q
);
219 ath_txq_skb_done(sc
, txq
, skb
);
220 ieee80211_free_txskb(sc
->hw
, skb
);
227 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
229 struct ath_txq
*txq
= tid
->txq
;
232 struct list_head bf_head
;
233 struct ath_tx_status ts
;
234 struct ath_frame_info
*fi
;
235 bool sendbar
= false;
237 INIT_LIST_HEAD(&bf_head
);
239 memset(&ts
, 0, sizeof(ts
));
241 while ((skb
= __skb_dequeue(&tid
->retry_q
))) {
242 fi
= get_frame_info(skb
);
245 ath_txq_skb_done(sc
, txq
, skb
);
246 ieee80211_free_txskb(sc
->hw
, skb
);
250 if (fi
->baw_tracked
) {
251 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
255 list_add_tail(&bf
->list
, &bf_head
);
256 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
260 ath_txq_unlock(sc
, txq
);
261 ath_send_bar(tid
, tid
->seq_start
);
262 ath_txq_lock(sc
, txq
);
266 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
271 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
272 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
274 __clear_bit(cindex
, tid
->tx_buf
);
276 while (tid
->baw_head
!= tid
->baw_tail
&& !test_bit(tid
->baw_head
, tid
->tx_buf
)) {
277 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
278 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
279 if (tid
->bar_index
>= 0)
284 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
287 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
288 u16 seqno
= bf
->bf_state
.seqno
;
291 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
292 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
293 __set_bit(cindex
, tid
->tx_buf
);
296 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
297 (ATH_TID_MAX_BUFS
- 1))) {
298 tid
->baw_tail
= cindex
;
299 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
303 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
304 struct ath_atx_tid
*tid
)
309 struct list_head bf_head
;
310 struct ath_tx_status ts
;
311 struct ath_frame_info
*fi
;
313 memset(&ts
, 0, sizeof(ts
));
314 INIT_LIST_HEAD(&bf_head
);
316 while ((skb
= ath_tid_dequeue(tid
))) {
317 fi
= get_frame_info(skb
);
321 ath_tx_complete(sc
, skb
, ATH_TX_ERROR
, txq
);
325 list_add_tail(&bf
->list
, &bf_head
);
326 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
330 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
331 struct sk_buff
*skb
, int count
)
333 struct ath_frame_info
*fi
= get_frame_info(skb
);
334 struct ath_buf
*bf
= fi
->bf
;
335 struct ieee80211_hdr
*hdr
;
336 int prev
= fi
->retries
;
338 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
339 fi
->retries
+= count
;
344 hdr
= (struct ieee80211_hdr
*)skb
->data
;
345 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
346 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
347 sizeof(*hdr
), DMA_TO_DEVICE
);
350 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
352 struct ath_buf
*bf
= NULL
;
354 spin_lock_bh(&sc
->tx
.txbuflock
);
356 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
357 spin_unlock_bh(&sc
->tx
.txbuflock
);
361 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
364 spin_unlock_bh(&sc
->tx
.txbuflock
);
369 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
371 spin_lock_bh(&sc
->tx
.txbuflock
);
372 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
373 spin_unlock_bh(&sc
->tx
.txbuflock
);
376 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
380 tbf
= ath_tx_get_buffer(sc
);
384 ATH_TXBUF_RESET(tbf
);
386 tbf
->bf_mpdu
= bf
->bf_mpdu
;
387 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
388 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
389 tbf
->bf_state
= bf
->bf_state
;
390 tbf
->bf_state
.stale
= false;
395 static void ath_tx_count_frames(struct ath_softc
*sc
, struct ath_buf
*bf
,
396 struct ath_tx_status
*ts
, int txok
,
397 int *nframes
, int *nbad
)
399 struct ath_frame_info
*fi
;
401 u32 ba
[WME_BA_BMP_SIZE
>> 5];
408 isaggr
= bf_isaggr(bf
);
410 seq_st
= ts
->ts_seqnum
;
411 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
415 fi
= get_frame_info(bf
->bf_mpdu
);
416 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_state
.seqno
);
419 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
427 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
428 struct ath_buf
*bf
, struct list_head
*bf_q
,
429 struct ath_tx_status
*ts
, int txok
)
431 struct ath_node
*an
= NULL
;
433 struct ieee80211_sta
*sta
;
434 struct ieee80211_hw
*hw
= sc
->hw
;
435 struct ieee80211_hdr
*hdr
;
436 struct ieee80211_tx_info
*tx_info
;
437 struct ath_atx_tid
*tid
= NULL
;
438 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
439 struct list_head bf_head
;
440 struct sk_buff_head bf_pending
;
441 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0, seq_first
;
442 u32 ba
[WME_BA_BMP_SIZE
>> 5];
443 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
444 bool rc_update
= true, isba
;
445 struct ieee80211_tx_rate rates
[4];
446 struct ath_frame_info
*fi
;
448 bool flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
453 hdr
= (struct ieee80211_hdr
*)skb
->data
;
455 tx_info
= IEEE80211_SKB_CB(skb
);
457 memcpy(rates
, bf
->rates
, sizeof(rates
));
459 retries
= ts
->ts_longretry
+ 1;
460 for (i
= 0; i
< ts
->ts_rateindex
; i
++)
461 retries
+= rates
[i
].count
;
465 sta
= ieee80211_find_sta_by_ifaddr(hw
, hdr
->addr1
, hdr
->addr2
);
469 INIT_LIST_HEAD(&bf_head
);
471 bf_next
= bf
->bf_next
;
473 if (!bf
->bf_state
.stale
|| bf_next
!= NULL
)
474 list_move_tail(&bf
->list
, &bf_head
);
476 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
, 0);
483 an
= (struct ath_node
*)sta
->drv_priv
;
484 tid
= ath_get_skb_tid(sc
, an
, skb
);
485 seq_first
= tid
->seq_start
;
486 isba
= ts
->ts_flags
& ATH9K_TX_BA
;
489 * The hardware occasionally sends a tx status for the wrong TID.
490 * In this case, the BA status cannot be considered valid and all
491 * subframes need to be retransmitted
493 * Only BlockAcks have a TID and therefore normal Acks cannot be
496 if (isba
&& tid
->tidno
!= ts
->tid
)
499 isaggr
= bf_isaggr(bf
);
500 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
502 if (isaggr
&& txok
) {
503 if (ts
->ts_flags
& ATH9K_TX_BA
) {
504 seq_st
= ts
->ts_seqnum
;
505 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
508 * AR5416 can become deaf/mute when BA
509 * issue happens. Chip needs to be reset.
510 * But AP code may have sychronization issues
511 * when perform internal reset in this routine.
512 * Only enable reset in STA mode for now.
514 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
519 __skb_queue_head_init(&bf_pending
);
521 ath_tx_count_frames(sc
, bf
, ts
, txok
, &nframes
, &nbad
);
523 u16 seqno
= bf
->bf_state
.seqno
;
525 txfail
= txpending
= sendbar
= 0;
526 bf_next
= bf
->bf_next
;
529 tx_info
= IEEE80211_SKB_CB(skb
);
530 fi
= get_frame_info(skb
);
532 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
) ||
535 * Outside of the current BlockAck window,
536 * maybe part of a previous session
539 } else if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, seqno
))) {
540 /* transmit completion, subframe is
541 * acked by block ack */
543 } else if (!isaggr
&& txok
) {
544 /* transmit completion */
548 } else if (fi
->retries
< ATH_MAX_SW_RETRIES
) {
549 if (txok
|| !an
->sleeping
)
550 ath_tx_set_retry(sc
, txq
, bf
->bf_mpdu
,
557 bar_index
= max_t(int, bar_index
,
558 ATH_BA_INDEX(seq_first
, seqno
));
562 * Make sure the last desc is reclaimed if it
563 * not a holding desc.
565 INIT_LIST_HEAD(&bf_head
);
566 if (bf_next
!= NULL
|| !bf_last
->bf_state
.stale
)
567 list_move_tail(&bf
->list
, &bf_head
);
571 * complete the acked-ones/xretried ones; update
574 ath_tx_update_baw(sc
, tid
, seqno
);
576 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
577 memcpy(tx_info
->control
.rates
, rates
, sizeof(rates
));
578 ath_tx_rc_status(sc
, bf
, ts
, nframes
, nbad
, txok
);
580 if (bf
== bf
->bf_lastbf
)
581 ath_dynack_sample_tx_ts(sc
->sc_ah
,
586 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
589 if (tx_info
->flags
& IEEE80211_TX_STATUS_EOSP
) {
590 tx_info
->flags
&= ~IEEE80211_TX_STATUS_EOSP
;
591 ieee80211_sta_eosp(sta
);
593 /* retry the un-acked ones */
594 if (bf
->bf_next
== NULL
&& bf_last
->bf_state
.stale
) {
597 tbf
= ath_clone_txbuf(sc
, bf_last
);
599 * Update tx baw and complete the
600 * frame with failed status if we
604 ath_tx_update_baw(sc
, tid
, seqno
);
606 ath_tx_complete_buf(sc
, bf
, txq
,
608 bar_index
= max_t(int, bar_index
,
609 ATH_BA_INDEX(seq_first
, seqno
));
617 * Put this buffer to the temporary pending
618 * queue to retain ordering
620 __skb_queue_tail(&bf_pending
, skb
);
626 /* prepend un-acked frames to the beginning of the pending frame queue */
627 if (!skb_queue_empty(&bf_pending
)) {
629 ieee80211_sta_set_buffered(sta
, tid
->tidno
, true);
631 skb_queue_splice_tail(&bf_pending
, &tid
->retry_q
);
633 ath_tx_queue_tid(sc
, txq
, tid
);
635 if (ts
->ts_status
& (ATH9K_TXERR_FILT
| ATH9K_TXERR_XRETRY
))
636 tid
->clear_ps_filter
= true;
640 if (bar_index
>= 0) {
641 u16 bar_seq
= ATH_BA_INDEX2SEQ(seq_first
, bar_index
);
643 if (BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bar_seq
))
644 tid
->bar_index
= ATH_BA_INDEX(tid
->seq_start
, bar_seq
);
646 ath_txq_unlock(sc
, txq
);
647 ath_send_bar(tid
, ATH_BA_INDEX2SEQ(seq_first
, bar_index
+ 1));
648 ath_txq_lock(sc
, txq
);
654 ath9k_queue_reset(sc
, RESET_TYPE_TX_ERROR
);
657 static bool bf_is_ampdu_not_probing(struct ath_buf
*bf
)
659 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
660 return bf_isampdu(bf
) && !(info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
);
663 static void ath_tx_process_buffer(struct ath_softc
*sc
, struct ath_txq
*txq
,
664 struct ath_tx_status
*ts
, struct ath_buf
*bf
,
665 struct list_head
*bf_head
)
667 struct ieee80211_tx_info
*info
;
670 txok
= !(ts
->ts_status
& ATH9K_TXERR_MASK
);
671 flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
672 txq
->axq_tx_inprogress
= false;
675 if (bf_is_ampdu_not_probing(bf
))
676 txq
->axq_ampdu_depth
--;
678 ts
->duration
= ath9k_hw_get_duration(sc
->sc_ah
, bf
->bf_desc
,
680 if (!bf_isampdu(bf
)) {
682 info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
683 memcpy(info
->control
.rates
, bf
->rates
,
684 sizeof(info
->control
.rates
));
685 ath_tx_rc_status(sc
, bf
, ts
, 1, txok
? 0 : 1, txok
);
686 ath_dynack_sample_tx_ts(sc
->sc_ah
, bf
->bf_mpdu
, ts
);
688 ath_tx_complete_buf(sc
, bf
, txq
, bf_head
, ts
, txok
);
690 ath_tx_complete_aggr(sc
, txq
, bf
, bf_head
, ts
, txok
);
693 ath_txq_schedule(sc
, txq
);
696 static bool ath_lookup_legacy(struct ath_buf
*bf
)
699 struct ieee80211_tx_info
*tx_info
;
700 struct ieee80211_tx_rate
*rates
;
704 tx_info
= IEEE80211_SKB_CB(skb
);
705 rates
= tx_info
->control
.rates
;
707 for (i
= 0; i
< 4; i
++) {
708 if (!rates
[i
].count
|| rates
[i
].idx
< 0)
711 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
))
718 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
719 struct ath_atx_tid
*tid
)
722 struct ieee80211_tx_info
*tx_info
;
723 struct ieee80211_tx_rate
*rates
;
724 u32 max_4ms_framelen
, frmlen
;
725 u16 aggr_limit
, bt_aggr_limit
, legacy
= 0;
726 int q
= tid
->txq
->mac80211_qnum
;
730 tx_info
= IEEE80211_SKB_CB(skb
);
734 * Find the lowest frame length among the rate series that will have a
735 * 4ms (or TXOP limited) transmit duration.
737 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
739 for (i
= 0; i
< 4; i
++) {
745 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
750 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
755 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
758 frmlen
= sc
->tx
.max_aggr_framelen
[q
][modeidx
][rates
[i
].idx
];
759 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
763 * limit aggregate size by the minimum rate if rate selected is
764 * not a probe rate, if rate selected is a probe rate then
765 * avoid aggregation of this packet.
767 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
770 aggr_limit
= min(max_4ms_framelen
, (u32
)ATH_AMPDU_LIMIT_MAX
);
773 * Override the default aggregation limit for BTCOEX.
775 bt_aggr_limit
= ath9k_btcoex_aggr_limit(sc
, max_4ms_framelen
);
777 aggr_limit
= bt_aggr_limit
;
779 if (tid
->an
->maxampdu
)
780 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
786 * Returns the number of delimiters to be added to
787 * meet the minimum required mpdudensity.
789 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
790 struct ath_buf
*bf
, u16 frmlen
,
793 #define FIRST_DESC_NDELIMS 60
794 u32 nsymbits
, nsymbols
;
797 int width
, streams
, half_gi
, ndelim
, mindelim
;
798 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
800 /* Select standard number of delimiters based on frame length alone */
801 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
804 * If encryption enabled, hardware requires some more padding between
806 * TODO - this could be improved to be dependent on the rate.
807 * The hardware can keep up at lower rates, but not higher rates
809 if ((fi
->keyix
!= ATH9K_TXKEYIX_INVALID
) &&
810 !(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
))
811 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
814 * Add delimiter when using RTS/CTS with aggregation
815 * and non enterprise AR9003 card
817 if (first_subfrm
&& !AR_SREV_9580_10_OR_LATER(sc
->sc_ah
) &&
818 (sc
->sc_ah
->ent_mode
& AR_ENT_OTP_MIN_PKT_SIZE_DISABLE
))
819 ndelim
= max(ndelim
, FIRST_DESC_NDELIMS
);
822 * Convert desired mpdu density from microeconds to bytes based
823 * on highest rate in rate series (i.e. first rate) to determine
824 * required minimum length for subframe. Take into account
825 * whether high rate is 20 or 40Mhz and half or full GI.
827 * If there is no mpdu density restriction, no further calculation
831 if (tid
->an
->mpdudensity
== 0)
834 rix
= bf
->rates
[0].idx
;
835 flags
= bf
->rates
[0].flags
;
836 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
837 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
840 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
842 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
847 streams
= HT_RC_2_STREAMS(rix
);
848 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
849 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
851 if (frmlen
< minlen
) {
852 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
853 ndelim
= max(mindelim
, ndelim
);
859 static struct ath_buf
*
860 ath_tx_get_tid_subframe(struct ath_softc
*sc
, struct ath_txq
*txq
,
861 struct ath_atx_tid
*tid
, struct sk_buff_head
**q
)
863 struct ieee80211_tx_info
*tx_info
;
864 struct ath_frame_info
*fi
;
871 if (skb_queue_empty(*q
))
878 fi
= get_frame_info(skb
);
881 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
883 bf
->bf_state
.stale
= false;
886 __skb_unlink(skb
, *q
);
887 ath_txq_skb_done(sc
, txq
, skb
);
888 ieee80211_free_txskb(sc
->hw
, skb
);
895 tx_info
= IEEE80211_SKB_CB(skb
);
896 tx_info
->flags
&= ~IEEE80211_TX_CTL_CLEAR_PS_FILT
;
899 * No aggregation session is running, but there may be frames
900 * from a previous session or a failed attempt in the queue.
901 * Send them out as normal data frames
904 tx_info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
906 if (!(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) {
907 bf
->bf_state
.bf_type
= 0;
911 bf
->bf_state
.bf_type
= BUF_AMPDU
| BUF_AGGR
;
912 seqno
= bf
->bf_state
.seqno
;
914 /* do not step over block-ack window */
915 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
))
918 if (tid
->bar_index
> ATH_BA_INDEX(tid
->seq_start
, seqno
)) {
919 struct ath_tx_status ts
= {};
920 struct list_head bf_head
;
922 INIT_LIST_HEAD(&bf_head
);
923 list_add(&bf
->list
, &bf_head
);
924 __skb_unlink(skb
, *q
);
925 ath_tx_update_baw(sc
, tid
, seqno
);
926 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
937 ath_tx_form_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
938 struct ath_atx_tid
*tid
, struct list_head
*bf_q
,
939 struct ath_buf
*bf_first
, struct sk_buff_head
*tid_q
,
942 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
943 struct ath_buf
*bf
= bf_first
, *bf_prev
= NULL
;
944 int nframes
= 0, ndelim
;
945 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
946 al_delta
, h_baw
= tid
->baw_size
/ 2;
947 struct ieee80211_tx_info
*tx_info
;
948 struct ath_frame_info
*fi
;
953 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
957 fi
= get_frame_info(skb
);
959 /* do not exceed aggregation limit */
960 al_delta
= ATH_AGGR_DELIM_SZ
+ fi
->framelen
;
962 if (aggr_limit
< al
+ bpad
+ al_delta
||
963 ath_lookup_legacy(bf
) || nframes
>= h_baw
)
966 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
967 if ((tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
) ||
968 !(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
))
972 /* add padding for previous frame to aggregation length */
973 al
+= bpad
+ al_delta
;
976 * Get the delimiters needed to meet the MPDU
977 * density for this node.
979 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, fi
->framelen
,
981 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
986 /* link buffers of this frame to the aggregate */
987 if (!fi
->baw_tracked
)
988 ath_tx_addto_baw(sc
, tid
, bf
);
989 bf
->bf_state
.ndelim
= ndelim
;
991 __skb_unlink(skb
, tid_q
);
992 list_add_tail(&bf
->list
, bf_q
);
994 bf_prev
->bf_next
= bf
;
998 bf
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &tid_q
);
1003 } while (ath_tid_has_buffered(tid
));
1006 bf
->bf_lastbf
= bf_prev
;
1008 if (bf
== bf_prev
) {
1009 al
= get_frame_info(bf
->bf_mpdu
)->framelen
;
1010 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1012 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
1023 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1024 * width - 0 for 20 MHz, 1 for 40 MHz
1025 * half_gi - to use 4us v/s 3.6 us for symbol time
1027 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, int pktlen
,
1028 int width
, int half_gi
, bool shortPreamble
)
1030 u32 nbits
, nsymbits
, duration
, nsymbols
;
1033 /* find number of symbols: PLCP + data */
1034 streams
= HT_RC_2_STREAMS(rix
);
1035 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
1036 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
1037 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
1040 duration
= SYMBOL_TIME(nsymbols
);
1042 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
1044 /* addup duration for legacy/ht training and signal fields */
1045 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1050 static int ath_max_framelen(int usec
, int mcs
, bool ht40
, bool sgi
)
1052 int streams
= HT_RC_2_STREAMS(mcs
);
1056 usec
-= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1057 symbols
= sgi
? TIME_SYMBOLS_HALFGI(usec
) : TIME_SYMBOLS(usec
);
1058 bits
= symbols
* bits_per_symbol
[mcs
% 8][ht40
] * streams
;
1059 bits
-= OFDM_PLCP_BITS
;
1067 void ath_update_max_aggr_framelen(struct ath_softc
*sc
, int queue
, int txop
)
1069 u16
*cur_ht20
, *cur_ht20_sgi
, *cur_ht40
, *cur_ht40_sgi
;
1072 /* 4ms is the default (and maximum) duration */
1073 if (!txop
|| txop
> 4096)
1076 cur_ht20
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20
];
1077 cur_ht20_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20_SGI
];
1078 cur_ht40
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40
];
1079 cur_ht40_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40_SGI
];
1080 for (mcs
= 0; mcs
< 32; mcs
++) {
1081 cur_ht20
[mcs
] = ath_max_framelen(txop
, mcs
, false, false);
1082 cur_ht20_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, false, true);
1083 cur_ht40
[mcs
] = ath_max_framelen(txop
, mcs
, true, false);
1084 cur_ht40_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, true, true);
1088 static u8
ath_get_rate_txpower(struct ath_softc
*sc
, struct ath_buf
*bf
,
1089 u8 rateidx
, bool is_40
, bool is_cck
)
1092 struct sk_buff
*skb
;
1093 struct ath_frame_info
*fi
;
1094 struct ieee80211_tx_info
*info
;
1095 struct ath_hw
*ah
= sc
->sc_ah
;
1097 if (sc
->tx99_state
|| !ah
->tpc_enabled
)
1098 return MAX_RATE_POWER
;
1101 fi
= get_frame_info(skb
);
1102 info
= IEEE80211_SKB_CB(skb
);
1104 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
1105 int txpower
= fi
->tx_power
;
1109 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
1111 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_2
) {
1113 struct modal_eep_header
*pmodal
;
1115 is_2ghz
= info
->band
== IEEE80211_BAND_2GHZ
;
1116 pmodal
= &eep
->modalHeader
[is_2ghz
];
1117 power_ht40delta
= pmodal
->ht40PowerIncForPdadc
;
1119 power_ht40delta
= 2;
1121 txpower
+= power_ht40delta
;
1124 if (AR_SREV_9287(ah
) || AR_SREV_9285(ah
) ||
1126 txpower
-= 2 * AR9287_PWR_TABLE_OFFSET_DB
;
1127 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
1130 power_offset
= ah
->eep_ops
->get_eeprom(ah
,
1131 EEP_PWR_TABLE_OFFSET
);
1132 txpower
-= 2 * power_offset
;
1135 if (OLC_FOR_AR9280_20_LATER
&& is_cck
)
1138 txpower
= max(txpower
, 0);
1139 max_power
= min_t(u8
, ah
->tx_power
[rateidx
], txpower
);
1141 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1142 * max_power is set to 0, frames are transmitted at max
1145 if (!max_power
&& !AR_SREV_9280_20_OR_LATER(ah
))
1147 } else if (!bf
->bf_state
.bfs_paprd
) {
1148 if (rateidx
< 8 && (info
->flags
& IEEE80211_TX_CTL_STBC
))
1149 max_power
= min_t(u8
, ah
->tx_power_stbc
[rateidx
],
1152 max_power
= min_t(u8
, ah
->tx_power
[rateidx
],
1155 max_power
= ah
->paprd_training_power
;
1161 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
1162 struct ath_tx_info
*info
, int len
, bool rts
)
1164 struct ath_hw
*ah
= sc
->sc_ah
;
1165 struct ath_common
*common
= ath9k_hw_common(ah
);
1166 struct sk_buff
*skb
;
1167 struct ieee80211_tx_info
*tx_info
;
1168 struct ieee80211_tx_rate
*rates
;
1169 const struct ieee80211_rate
*rate
;
1170 struct ieee80211_hdr
*hdr
;
1171 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
1172 u32 rts_thresh
= sc
->hw
->wiphy
->rts_threshold
;
1177 tx_info
= IEEE80211_SKB_CB(skb
);
1179 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1181 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1182 info
->dur_update
= !ieee80211_is_pspoll(hdr
->frame_control
);
1183 info
->rtscts_rate
= fi
->rtscts_rate
;
1185 for (i
= 0; i
< ARRAY_SIZE(bf
->rates
); i
++) {
1186 bool is_40
, is_sgi
, is_sp
, is_cck
;
1189 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1193 info
->rates
[i
].Tries
= rates
[i
].count
;
1196 * Handle RTS threshold for unaggregated HT frames.
1198 if (bf_isampdu(bf
) && !bf_isaggr(bf
) &&
1199 (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) &&
1200 unlikely(rts_thresh
!= (u32
) -1)) {
1201 if (!rts_thresh
|| (len
> rts_thresh
))
1205 if (rts
|| rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1206 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1207 info
->flags
|= ATH9K_TXDESC_RTSENA
;
1208 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1209 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1210 info
->flags
|= ATH9K_TXDESC_CTSENA
;
1213 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1214 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1215 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1216 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1218 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
1219 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
1220 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
1222 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
1224 info
->rates
[i
].Rate
= rix
| 0x80;
1225 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1226 ah
->txchainmask
, info
->rates
[i
].Rate
);
1227 info
->rates
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, len
,
1228 is_40
, is_sgi
, is_sp
);
1229 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
1230 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
1232 info
->txpower
[i
] = ath_get_rate_txpower(sc
, bf
, rix
,
1238 rate
= &common
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1239 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
1240 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1241 phy
= WLAN_RC_PHY_CCK
;
1243 phy
= WLAN_RC_PHY_OFDM
;
1245 info
->rates
[i
].Rate
= rate
->hw_value
;
1246 if (rate
->hw_value_short
) {
1247 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1248 info
->rates
[i
].Rate
|= rate
->hw_value_short
;
1253 if (bf
->bf_state
.bfs_paprd
)
1254 info
->rates
[i
].ChSel
= ah
->txchainmask
;
1256 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1257 ah
->txchainmask
, info
->rates
[i
].Rate
);
1259 info
->rates
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1260 phy
, rate
->bitrate
* 100, len
, rix
, is_sp
);
1262 is_cck
= IS_CCK_RATE(info
->rates
[i
].Rate
);
1263 info
->txpower
[i
] = ath_get_rate_txpower(sc
, bf
, rix
, false,
1267 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1268 if (bf_isaggr(bf
) && (len
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1269 info
->flags
&= ~ATH9K_TXDESC_RTSENA
;
1271 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1272 if (info
->flags
& ATH9K_TXDESC_RTSENA
)
1273 info
->flags
&= ~ATH9K_TXDESC_CTSENA
;
1276 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1278 struct ieee80211_hdr
*hdr
;
1279 enum ath9k_pkt_type htype
;
1282 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1283 fc
= hdr
->frame_control
;
1285 if (ieee80211_is_beacon(fc
))
1286 htype
= ATH9K_PKT_TYPE_BEACON
;
1287 else if (ieee80211_is_probe_resp(fc
))
1288 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1289 else if (ieee80211_is_atim(fc
))
1290 htype
= ATH9K_PKT_TYPE_ATIM
;
1291 else if (ieee80211_is_pspoll(fc
))
1292 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1294 htype
= ATH9K_PKT_TYPE_NORMAL
;
1299 static void ath_tx_fill_desc(struct ath_softc
*sc
, struct ath_buf
*bf
,
1300 struct ath_txq
*txq
, int len
)
1302 struct ath_hw
*ah
= sc
->sc_ah
;
1303 struct ath_buf
*bf_first
= NULL
;
1304 struct ath_tx_info info
;
1305 u32 rts_thresh
= sc
->hw
->wiphy
->rts_threshold
;
1308 memset(&info
, 0, sizeof(info
));
1309 info
.is_first
= true;
1310 info
.is_last
= true;
1311 info
.qcu
= txq
->axq_qnum
;
1314 struct sk_buff
*skb
= bf
->bf_mpdu
;
1315 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1316 struct ath_frame_info
*fi
= get_frame_info(skb
);
1317 bool aggr
= !!(bf
->bf_state
.bf_type
& BUF_AGGR
);
1319 info
.type
= get_hw_packet_type(skb
);
1321 info
.link
= bf
->bf_next
->bf_daddr
;
1323 info
.link
= (sc
->tx99_state
) ? bf
->bf_daddr
: 0;
1328 if (!sc
->tx99_state
)
1329 info
.flags
= ATH9K_TXDESC_INTREQ
;
1330 if ((tx_info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
) ||
1331 txq
== sc
->tx
.uapsdq
)
1332 info
.flags
|= ATH9K_TXDESC_CLRDMASK
;
1334 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1335 info
.flags
|= ATH9K_TXDESC_NOACK
;
1336 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1337 info
.flags
|= ATH9K_TXDESC_LDPC
;
1339 if (bf
->bf_state
.bfs_paprd
)
1340 info
.flags
|= (u32
) bf
->bf_state
.bfs_paprd
<<
1341 ATH9K_TXDESC_PAPRD_S
;
1344 * mac80211 doesn't handle RTS threshold for HT because
1345 * the decision has to be taken based on AMPDU length
1346 * and aggregation is done entirely inside ath9k.
1347 * Set the RTS/CTS flag for the first subframe based
1350 if (aggr
&& (bf
== bf_first
) &&
1351 unlikely(rts_thresh
!= (u32
) -1)) {
1353 * "len" is the size of the entire AMPDU.
1355 if (!rts_thresh
|| (len
> rts_thresh
))
1362 ath_buf_set_rate(sc
, bf
, &info
, len
, rts
);
1365 info
.buf_addr
[0] = bf
->bf_buf_addr
;
1366 info
.buf_len
[0] = skb
->len
;
1367 info
.pkt_len
= fi
->framelen
;
1368 info
.keyix
= fi
->keyix
;
1369 info
.keytype
= fi
->keytype
;
1373 info
.aggr
= AGGR_BUF_FIRST
;
1374 else if (bf
== bf_first
->bf_lastbf
)
1375 info
.aggr
= AGGR_BUF_LAST
;
1377 info
.aggr
= AGGR_BUF_MIDDLE
;
1379 info
.ndelim
= bf
->bf_state
.ndelim
;
1380 info
.aggr_len
= len
;
1383 if (bf
== bf_first
->bf_lastbf
)
1386 ath9k_hw_set_txdesc(ah
, bf
->bf_desc
, &info
);
1392 ath_tx_form_burst(struct ath_softc
*sc
, struct ath_txq
*txq
,
1393 struct ath_atx_tid
*tid
, struct list_head
*bf_q
,
1394 struct ath_buf
*bf_first
, struct sk_buff_head
*tid_q
)
1396 struct ath_buf
*bf
= bf_first
, *bf_prev
= NULL
;
1397 struct sk_buff
*skb
;
1401 struct ieee80211_tx_info
*tx_info
;
1405 __skb_unlink(skb
, tid_q
);
1406 list_add_tail(&bf
->list
, bf_q
);
1408 bf_prev
->bf_next
= bf
;
1414 bf
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &tid_q
);
1418 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1419 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)
1422 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1426 static bool ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
1427 struct ath_atx_tid
*tid
, bool *stop
)
1430 struct ieee80211_tx_info
*tx_info
;
1431 struct sk_buff_head
*tid_q
;
1432 struct list_head bf_q
;
1434 bool aggr
, last
= true;
1436 if (!ath_tid_has_buffered(tid
))
1439 INIT_LIST_HEAD(&bf_q
);
1441 bf
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &tid_q
);
1445 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1446 aggr
= !!(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
);
1447 if ((aggr
&& txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
) ||
1448 (!aggr
&& txq
->axq_depth
>= ATH_NON_AGGR_MIN_QDEPTH
)) {
1453 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1455 last
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
, bf
,
1458 ath_tx_form_burst(sc
, txq
, tid
, &bf_q
, bf
, tid_q
);
1460 if (list_empty(&bf_q
))
1463 if (tid
->clear_ps_filter
|| tid
->an
->no_ps_filter
) {
1464 tid
->clear_ps_filter
= false;
1465 tx_info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1468 ath_tx_fill_desc(sc
, bf
, txq
, aggr_len
);
1469 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1473 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1476 struct ath_atx_tid
*txtid
;
1477 struct ath_txq
*txq
;
1478 struct ath_node
*an
;
1481 an
= (struct ath_node
*)sta
->drv_priv
;
1482 txtid
= ATH_AN_2_TID(an
, tid
);
1485 ath_txq_lock(sc
, txq
);
1487 /* update ampdu factor/density, they may have changed. This may happen
1488 * in HT IBSS when a beacon with HT-info is received after the station
1489 * has already been added.
1491 if (sta
->ht_cap
.ht_supported
) {
1492 an
->maxampdu
= (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR
+
1493 sta
->ht_cap
.ampdu_factor
)) - 1;
1494 density
= ath9k_parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
1495 an
->mpdudensity
= density
;
1498 /* force sequence number allocation for pending frames */
1499 ath_tx_tid_change_state(sc
, txtid
);
1501 txtid
->active
= true;
1502 *ssn
= txtid
->seq_start
= txtid
->seq_next
;
1503 txtid
->bar_index
= -1;
1505 memset(txtid
->tx_buf
, 0, sizeof(txtid
->tx_buf
));
1506 txtid
->baw_head
= txtid
->baw_tail
= 0;
1508 ath_txq_unlock_complete(sc
, txq
);
1513 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1515 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1516 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
1517 struct ath_txq
*txq
= txtid
->txq
;
1519 ath_txq_lock(sc
, txq
);
1520 txtid
->active
= false;
1521 ath_tx_flush_tid(sc
, txtid
);
1522 ath_tx_tid_change_state(sc
, txtid
);
1523 ath_txq_unlock_complete(sc
, txq
);
1526 void ath_tx_aggr_sleep(struct ieee80211_sta
*sta
, struct ath_softc
*sc
,
1527 struct ath_node
*an
)
1529 struct ath_atx_tid
*tid
;
1530 struct ath_txq
*txq
;
1534 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1535 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
1539 ath_txq_lock(sc
, txq
);
1541 if (list_empty(&tid
->list
)) {
1542 ath_txq_unlock(sc
, txq
);
1546 buffered
= ath_tid_has_buffered(tid
);
1548 list_del_init(&tid
->list
);
1550 ath_txq_unlock(sc
, txq
);
1552 ieee80211_sta_set_buffered(sta
, tidno
, buffered
);
1556 void ath_tx_aggr_wakeup(struct ath_softc
*sc
, struct ath_node
*an
)
1558 struct ath_atx_tid
*tid
;
1559 struct ath_txq
*txq
;
1562 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1563 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
1567 ath_txq_lock(sc
, txq
);
1568 tid
->clear_ps_filter
= true;
1570 if (ath_tid_has_buffered(tid
)) {
1571 ath_tx_queue_tid(sc
, txq
, tid
);
1572 ath_txq_schedule(sc
, txq
);
1575 ath_txq_unlock_complete(sc
, txq
);
1579 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1582 struct ath_atx_tid
*tid
;
1583 struct ath_node
*an
;
1584 struct ath_txq
*txq
;
1586 an
= (struct ath_node
*)sta
->drv_priv
;
1587 tid
= ATH_AN_2_TID(an
, tidno
);
1590 ath_txq_lock(sc
, txq
);
1592 tid
->baw_size
= IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
1594 if (ath_tid_has_buffered(tid
)) {
1595 ath_tx_queue_tid(sc
, txq
, tid
);
1596 ath_txq_schedule(sc
, txq
);
1599 ath_txq_unlock_complete(sc
, txq
);
1602 void ath9k_release_buffered_frames(struct ieee80211_hw
*hw
,
1603 struct ieee80211_sta
*sta
,
1604 u16 tids
, int nframes
,
1605 enum ieee80211_frame_release_type reason
,
1608 struct ath_softc
*sc
= hw
->priv
;
1609 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1610 struct ath_txq
*txq
= sc
->tx
.uapsdq
;
1611 struct ieee80211_tx_info
*info
;
1612 struct list_head bf_q
;
1613 struct ath_buf
*bf_tail
= NULL
, *bf
;
1614 struct sk_buff_head
*tid_q
;
1618 INIT_LIST_HEAD(&bf_q
);
1619 for (i
= 0; tids
&& nframes
; i
++, tids
>>= 1) {
1620 struct ath_atx_tid
*tid
;
1625 tid
= ATH_AN_2_TID(an
, i
);
1627 ath_txq_lock(sc
, tid
->txq
);
1628 while (nframes
> 0) {
1629 bf
= ath_tx_get_tid_subframe(sc
, sc
->tx
.uapsdq
, tid
, &tid_q
);
1633 __skb_unlink(bf
->bf_mpdu
, tid_q
);
1634 list_add_tail(&bf
->list
, &bf_q
);
1635 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1636 if (bf_isampdu(bf
)) {
1637 ath_tx_addto_baw(sc
, tid
, bf
);
1638 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1641 bf_tail
->bf_next
= bf
;
1646 TX_STAT_INC(txq
->axq_qnum
, a_queued_hw
);
1648 if (an
->sta
&& !ath_tid_has_buffered(tid
))
1649 ieee80211_sta_set_buffered(an
->sta
, i
, false);
1651 ath_txq_unlock_complete(sc
, tid
->txq
);
1654 if (list_empty(&bf_q
))
1657 info
= IEEE80211_SKB_CB(bf_tail
->bf_mpdu
);
1658 info
->flags
|= IEEE80211_TX_STATUS_EOSP
;
1660 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1661 ath_txq_lock(sc
, txq
);
1662 ath_tx_fill_desc(sc
, bf
, txq
, 0);
1663 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1664 ath_txq_unlock(sc
, txq
);
1667 /********************/
1668 /* Queue Management */
1669 /********************/
1671 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1673 struct ath_hw
*ah
= sc
->sc_ah
;
1674 struct ath9k_tx_queue_info qi
;
1675 static const int subtype_txq_to_hwq
[] = {
1676 [IEEE80211_AC_BE
] = ATH_TXQ_AC_BE
,
1677 [IEEE80211_AC_BK
] = ATH_TXQ_AC_BK
,
1678 [IEEE80211_AC_VI
] = ATH_TXQ_AC_VI
,
1679 [IEEE80211_AC_VO
] = ATH_TXQ_AC_VO
,
1683 memset(&qi
, 0, sizeof(qi
));
1684 qi
.tqi_subtype
= subtype_txq_to_hwq
[subtype
];
1685 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1686 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1687 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1688 qi
.tqi_physCompBuf
= 0;
1691 * Enable interrupts only for EOL and DESC conditions.
1692 * We mark tx descriptors to receive a DESC interrupt
1693 * when a tx queue gets deep; otherwise waiting for the
1694 * EOL to reap descriptors. Note that this is done to
1695 * reduce interrupt load and this only defers reaping
1696 * descriptors, never transmitting frames. Aside from
1697 * reducing interrupts this also permits more concurrency.
1698 * The only potential downside is if the tx queue backs
1699 * up in which case the top half of the kernel may backup
1700 * due to a lack of tx descriptors.
1702 * The UAPSD queue is an exception, since we take a desc-
1703 * based intr on the EOSP frames.
1705 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1706 qi
.tqi_qflags
= TXQ_FLAG_TXINT_ENABLE
;
1708 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1709 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1711 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1712 TXQ_FLAG_TXDESCINT_ENABLE
;
1714 axq_qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1715 if (axq_qnum
== -1) {
1717 * NB: don't print a message, this happens
1718 * normally on parts with too few tx queues
1722 if (!ATH_TXQ_SETUP(sc
, axq_qnum
)) {
1723 struct ath_txq
*txq
= &sc
->tx
.txq
[axq_qnum
];
1725 txq
->axq_qnum
= axq_qnum
;
1726 txq
->mac80211_qnum
= -1;
1727 txq
->axq_link
= NULL
;
1728 __skb_queue_head_init(&txq
->complete_q
);
1729 INIT_LIST_HEAD(&txq
->axq_q
);
1730 spin_lock_init(&txq
->axq_lock
);
1732 txq
->axq_ampdu_depth
= 0;
1733 txq
->axq_tx_inprogress
= false;
1734 sc
->tx
.txqsetup
|= 1<<axq_qnum
;
1736 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1737 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
1738 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
1740 return &sc
->tx
.txq
[axq_qnum
];
1743 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
1744 struct ath9k_tx_queue_info
*qinfo
)
1746 struct ath_hw
*ah
= sc
->sc_ah
;
1748 struct ath9k_tx_queue_info qi
;
1750 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
1752 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
1753 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
1754 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
1755 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
1756 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
1757 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
1759 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
1760 ath_err(ath9k_hw_common(sc
->sc_ah
),
1761 "Unable to update hardware queue %u!\n", qnum
);
1764 ath9k_hw_resettxqueue(ah
, qnum
);
1770 int ath_cabq_update(struct ath_softc
*sc
)
1772 struct ath9k_tx_queue_info qi
;
1773 struct ath_beacon_config
*cur_conf
= &sc
->cur_chan
->beacon
;
1774 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1776 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1778 qi
.tqi_readyTime
= (TU_TO_USEC(cur_conf
->beacon_interval
) *
1779 ATH_CABQ_READY_TIME
) / 100;
1780 ath_txq_update(sc
, qnum
, &qi
);
1785 static void ath_drain_txq_list(struct ath_softc
*sc
, struct ath_txq
*txq
,
1786 struct list_head
*list
)
1788 struct ath_buf
*bf
, *lastbf
;
1789 struct list_head bf_head
;
1790 struct ath_tx_status ts
;
1792 memset(&ts
, 0, sizeof(ts
));
1793 ts
.ts_status
= ATH9K_TX_FLUSH
;
1794 INIT_LIST_HEAD(&bf_head
);
1796 while (!list_empty(list
)) {
1797 bf
= list_first_entry(list
, struct ath_buf
, list
);
1799 if (bf
->bf_state
.stale
) {
1800 list_del(&bf
->list
);
1802 ath_tx_return_buffer(sc
, bf
);
1806 lastbf
= bf
->bf_lastbf
;
1807 list_cut_position(&bf_head
, list
, &lastbf
->list
);
1808 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
1813 * Drain a given TX queue (could be Beacon or Data)
1815 * This assumes output has been stopped and
1816 * we do not need to block ath_tx_tasklet.
1818 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1820 ath_txq_lock(sc
, txq
);
1822 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1823 int idx
= txq
->txq_tailidx
;
1825 while (!list_empty(&txq
->txq_fifo
[idx
])) {
1826 ath_drain_txq_list(sc
, txq
, &txq
->txq_fifo
[idx
]);
1828 INCR(idx
, ATH_TXFIFO_DEPTH
);
1830 txq
->txq_tailidx
= idx
;
1833 txq
->axq_link
= NULL
;
1834 txq
->axq_tx_inprogress
= false;
1835 ath_drain_txq_list(sc
, txq
, &txq
->axq_q
);
1837 ath_txq_unlock_complete(sc
, txq
);
1840 bool ath_drain_all_txq(struct ath_softc
*sc
)
1842 struct ath_hw
*ah
= sc
->sc_ah
;
1843 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1844 struct ath_txq
*txq
;
1848 if (test_bit(ATH_OP_INVALID
, &common
->op_flags
))
1851 ath9k_hw_abort_tx_dma(ah
);
1853 /* Check if any queue remains active */
1854 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1855 if (!ATH_TXQ_SETUP(sc
, i
))
1858 if (!sc
->tx
.txq
[i
].axq_depth
)
1861 if (ath9k_hw_numtxpending(ah
, sc
->tx
.txq
[i
].axq_qnum
))
1866 RESET_STAT_INC(sc
, RESET_TX_DMA_ERROR
);
1867 ath_dbg(common
, RESET
,
1868 "Failed to stop TX DMA, queues=0x%03x!\n", npend
);
1871 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1872 if (!ATH_TXQ_SETUP(sc
, i
))
1876 * The caller will resume queues with ieee80211_wake_queues.
1877 * Mark the queue as not stopped to prevent ath_tx_complete
1878 * from waking the queue too early.
1880 txq
= &sc
->tx
.txq
[i
];
1881 txq
->stopped
= false;
1882 ath_draintxq(sc
, txq
);
1888 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1890 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1891 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1894 /* For each acq entry, for each tid, try to schedule packets
1895 * for transmit until ampdu_depth has reached min Q depth.
1897 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1899 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1900 struct ath_atx_tid
*tid
, *last_tid
;
1901 struct list_head
*tid_list
;
1904 if (txq
->mac80211_qnum
< 0)
1907 if (test_bit(ATH_OP_HW_RESET
, &common
->op_flags
))
1910 spin_lock_bh(&sc
->chan_lock
);
1911 tid_list
= &sc
->cur_chan
->acq
[txq
->mac80211_qnum
];
1913 if (list_empty(tid_list
)) {
1914 spin_unlock_bh(&sc
->chan_lock
);
1920 last_tid
= list_entry(tid_list
->prev
, struct ath_atx_tid
, list
);
1921 while (!list_empty(tid_list
)) {
1924 if (sc
->cur_chan
->stopped
)
1927 tid
= list_first_entry(tid_list
, struct ath_atx_tid
, list
);
1928 list_del_init(&tid
->list
);
1930 if (ath_tx_sched_aggr(sc
, txq
, tid
, &stop
))
1934 * add tid to round-robin queue if more frames
1935 * are pending for the tid
1937 if (ath_tid_has_buffered(tid
))
1938 ath_tx_queue_tid(sc
, txq
, tid
);
1943 if (tid
== last_tid
) {
1948 last_tid
= list_entry(tid_list
->prev
,
1949 struct ath_atx_tid
, list
);
1954 spin_unlock_bh(&sc
->chan_lock
);
1957 void ath_txq_schedule_all(struct ath_softc
*sc
)
1959 struct ath_txq
*txq
;
1962 for (i
= 0; i
< IEEE80211_NUM_ACS
; i
++) {
1963 txq
= sc
->tx
.txq_map
[i
];
1965 spin_lock_bh(&txq
->axq_lock
);
1966 ath_txq_schedule(sc
, txq
);
1967 spin_unlock_bh(&txq
->axq_lock
);
1976 * Insert a chain of ath_buf (descriptors) on a txq and
1977 * assume the descriptors are already chained together by caller.
1979 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1980 struct list_head
*head
, bool internal
)
1982 struct ath_hw
*ah
= sc
->sc_ah
;
1983 struct ath_common
*common
= ath9k_hw_common(ah
);
1984 struct ath_buf
*bf
, *bf_last
;
1985 bool puttxbuf
= false;
1989 * Insert the frame on the outbound list and
1990 * pass it on to the hardware.
1993 if (list_empty(head
))
1996 edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1997 bf
= list_first_entry(head
, struct ath_buf
, list
);
1998 bf_last
= list_entry(head
->prev
, struct ath_buf
, list
);
2000 ath_dbg(common
, QUEUE
, "qnum: %d, txq depth: %d\n",
2001 txq
->axq_qnum
, txq
->axq_depth
);
2003 if (edma
&& list_empty(&txq
->txq_fifo
[txq
->txq_headidx
])) {
2004 list_splice_tail_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
2005 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
2008 list_splice_tail_init(head
, &txq
->axq_q
);
2010 if (txq
->axq_link
) {
2011 ath9k_hw_set_desc_link(ah
, txq
->axq_link
, bf
->bf_daddr
);
2012 ath_dbg(common
, XMIT
, "link[%u] (%p)=%llx (%p)\n",
2013 txq
->axq_qnum
, txq
->axq_link
,
2014 ito64(bf
->bf_daddr
), bf
->bf_desc
);
2018 txq
->axq_link
= bf_last
->bf_desc
;
2022 TX_STAT_INC(txq
->axq_qnum
, puttxbuf
);
2023 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
2024 ath_dbg(common
, XMIT
, "TXDP[%u] = %llx (%p)\n",
2025 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
2028 if (!edma
|| sc
->tx99_state
) {
2029 TX_STAT_INC(txq
->axq_qnum
, txstart
);
2030 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
2036 if (bf_is_ampdu_not_probing(bf
))
2037 txq
->axq_ampdu_depth
++;
2039 bf_last
= bf
->bf_lastbf
;
2040 bf
= bf_last
->bf_next
;
2041 bf_last
->bf_next
= NULL
;
2046 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
2047 struct ath_atx_tid
*tid
, struct sk_buff
*skb
)
2049 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2050 struct ath_frame_info
*fi
= get_frame_info(skb
);
2051 struct list_head bf_head
;
2052 struct ath_buf
*bf
= fi
->bf
;
2054 INIT_LIST_HEAD(&bf_head
);
2055 list_add_tail(&bf
->list
, &bf_head
);
2056 bf
->bf_state
.bf_type
= 0;
2057 if (tid
&& (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) {
2058 bf
->bf_state
.bf_type
= BUF_AMPDU
;
2059 ath_tx_addto_baw(sc
, tid
, bf
);
2064 ath_tx_fill_desc(sc
, bf
, txq
, fi
->framelen
);
2065 ath_tx_txqaddbuf(sc
, txq
, &bf_head
, false);
2066 TX_STAT_INC(txq
->axq_qnum
, queued
);
2069 static void setup_frame_info(struct ieee80211_hw
*hw
,
2070 struct ieee80211_sta
*sta
,
2071 struct sk_buff
*skb
,
2074 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2075 struct ieee80211_key_conf
*hw_key
= tx_info
->control
.hw_key
;
2076 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2077 const struct ieee80211_rate
*rate
;
2078 struct ath_frame_info
*fi
= get_frame_info(skb
);
2079 struct ath_node
*an
= NULL
;
2080 enum ath9k_key_type keytype
;
2081 bool short_preamble
= false;
2085 * We check if Short Preamble is needed for the CTS rate by
2086 * checking the BSS's global flag.
2087 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2089 if (tx_info
->control
.vif
&&
2090 tx_info
->control
.vif
->bss_conf
.use_short_preamble
)
2091 short_preamble
= true;
2093 rate
= ieee80211_get_rts_cts_rate(hw
, tx_info
);
2094 keytype
= ath9k_cmn_get_hw_crypto_keytype(skb
);
2097 an
= (struct ath_node
*) sta
->drv_priv
;
2099 if (tx_info
->control
.vif
) {
2100 struct ieee80211_vif
*vif
= tx_info
->control
.vif
;
2102 txpower
= 2 * vif
->bss_conf
.txpower
;
2104 struct ath_softc
*sc
= hw
->priv
;
2106 txpower
= sc
->cur_chan
->cur_txpower
;
2109 memset(fi
, 0, sizeof(*fi
));
2112 fi
->keyix
= hw_key
->hw_key_idx
;
2113 else if (an
&& ieee80211_is_data(hdr
->frame_control
) && an
->ps_key
> 0)
2114 fi
->keyix
= an
->ps_key
;
2116 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
2117 fi
->keytype
= keytype
;
2118 fi
->framelen
= framelen
;
2119 fi
->tx_power
= txpower
;
2123 fi
->rtscts_rate
= rate
->hw_value
;
2125 fi
->rtscts_rate
|= rate
->hw_value_short
;
2128 u8
ath_txchainmask_reduction(struct ath_softc
*sc
, u8 chainmask
, u32 rate
)
2130 struct ath_hw
*ah
= sc
->sc_ah
;
2131 struct ath9k_channel
*curchan
= ah
->curchan
;
2133 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_APM
) && IS_CHAN_5GHZ(curchan
) &&
2134 (chainmask
== 0x7) && (rate
< 0x90))
2136 else if (AR_SREV_9462(ah
) && ath9k_hw_btcoex_is_enabled(ah
) &&
2144 * Assign a descriptor (and sequence number if necessary,
2145 * and map buffer for DMA. Frees skb on error
2147 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
2148 struct ath_txq
*txq
,
2149 struct ath_atx_tid
*tid
,
2150 struct sk_buff
*skb
)
2152 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2153 struct ath_frame_info
*fi
= get_frame_info(skb
);
2154 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2159 bf
= ath_tx_get_buffer(sc
);
2161 ath_dbg(common
, XMIT
, "TX buffers are full\n");
2165 ATH_TXBUF_RESET(bf
);
2167 if (tid
&& ieee80211_is_data_present(hdr
->frame_control
)) {
2168 fragno
= le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
;
2169 seqno
= tid
->seq_next
;
2170 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
2173 hdr
->seq_ctrl
|= cpu_to_le16(fragno
);
2175 if (!ieee80211_has_morefrags(hdr
->frame_control
))
2176 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
2178 bf
->bf_state
.seqno
= seqno
;
2183 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
2184 skb
->len
, DMA_TO_DEVICE
);
2185 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_buf_addr
))) {
2187 bf
->bf_buf_addr
= 0;
2188 ath_err(ath9k_hw_common(sc
->sc_ah
),
2189 "dma_mapping_error() on TX\n");
2190 ath_tx_return_buffer(sc
, bf
);
2199 void ath_assign_seq(struct ath_common
*common
, struct sk_buff
*skb
)
2201 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2202 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2203 struct ieee80211_vif
*vif
= info
->control
.vif
;
2204 struct ath_vif
*avp
;
2206 if (!(info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
))
2212 avp
= (struct ath_vif
*)vif
->drv_priv
;
2214 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2215 avp
->seq_no
+= 0x10;
2217 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2218 hdr
->seq_ctrl
|= cpu_to_le16(avp
->seq_no
);
2221 static int ath_tx_prepare(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2222 struct ath_tx_control
*txctl
)
2224 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2225 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2226 struct ieee80211_sta
*sta
= txctl
->sta
;
2227 struct ieee80211_vif
*vif
= info
->control
.vif
;
2228 struct ath_vif
*avp
;
2229 struct ath_softc
*sc
= hw
->priv
;
2230 int frmlen
= skb
->len
+ FCS_LEN
;
2231 int padpos
, padsize
;
2233 /* NOTE: sta can be NULL according to net/mac80211.h */
2235 txctl
->an
= (struct ath_node
*)sta
->drv_priv
;
2236 else if (vif
&& ieee80211_is_data(hdr
->frame_control
)) {
2237 avp
= (void *)vif
->drv_priv
;
2238 txctl
->an
= &avp
->mcast_node
;
2241 if (info
->control
.hw_key
)
2242 frmlen
+= info
->control
.hw_key
->icv_len
;
2244 ath_assign_seq(ath9k_hw_common(sc
->sc_ah
), skb
);
2246 if ((vif
&& vif
->type
!= NL80211_IFTYPE_AP
&&
2247 vif
->type
!= NL80211_IFTYPE_AP_VLAN
) ||
2248 !ieee80211_is_data(hdr
->frame_control
))
2249 info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
2251 /* Add the padding after the header if this is not already done */
2252 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2253 padsize
= padpos
& 3;
2254 if (padsize
&& skb
->len
> padpos
) {
2255 if (skb_headroom(skb
) < padsize
)
2258 skb_push(skb
, padsize
);
2259 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
2262 setup_frame_info(hw
, sta
, skb
, frmlen
);
2267 /* Upon failure caller should free skb */
2268 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2269 struct ath_tx_control
*txctl
)
2271 struct ieee80211_hdr
*hdr
;
2272 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2273 struct ieee80211_sta
*sta
= txctl
->sta
;
2274 struct ieee80211_vif
*vif
= info
->control
.vif
;
2275 struct ath_frame_info
*fi
= get_frame_info(skb
);
2276 struct ath_vif
*avp
= NULL
;
2277 struct ath_softc
*sc
= hw
->priv
;
2278 struct ath_txq
*txq
= txctl
->txq
;
2279 struct ath_atx_tid
*tid
= NULL
;
2281 bool queue
, skip_uapsd
= false, ps_resp
;
2285 avp
= (void *)vif
->drv_priv
;
2287 if (info
->flags
& IEEE80211_TX_CTL_TX_OFFCHAN
)
2288 txctl
->force_channel
= true;
2290 ps_resp
= !!(info
->control
.flags
& IEEE80211_TX_CTRL_PS_RESPONSE
);
2292 ret
= ath_tx_prepare(hw
, skb
, txctl
);
2296 hdr
= (struct ieee80211_hdr
*) skb
->data
;
2298 * At this point, the vif, hw_key and sta pointers in the tx control
2299 * info are no longer valid (overwritten by the ath_frame_info data.
2302 q
= skb_get_queue_mapping(skb
);
2304 ath_txq_lock(sc
, txq
);
2305 if (txq
== sc
->tx
.txq_map
[q
]) {
2307 if (++txq
->pending_frames
> sc
->tx
.txq_max_pending
[q
] &&
2309 if (ath9k_is_chanctx_enabled())
2310 ieee80211_stop_queue(sc
->hw
, info
->hw_queue
);
2312 ieee80211_stop_queue(sc
->hw
, q
);
2313 txq
->stopped
= true;
2317 queue
= ieee80211_is_data_present(hdr
->frame_control
);
2319 /* Force queueing of all frames that belong to a virtual interface on
2320 * a different channel context, to ensure that they are sent on the
2323 if (((avp
&& avp
->chanctx
!= sc
->cur_chan
) ||
2324 sc
->cur_chan
->stopped
) && !txctl
->force_channel
) {
2326 txctl
->an
= &avp
->mcast_node
;
2331 if (txctl
->an
&& queue
)
2332 tid
= ath_get_skb_tid(sc
, txctl
->an
, skb
);
2334 if (!skip_uapsd
&& ps_resp
) {
2335 ath_txq_unlock(sc
, txq
);
2336 txq
= sc
->tx
.uapsdq
;
2337 ath_txq_lock(sc
, txq
);
2338 } else if (txctl
->an
&& queue
) {
2339 WARN_ON(tid
->txq
!= txctl
->txq
);
2341 if (info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
)
2342 tid
->clear_ps_filter
= true;
2345 * Add this frame to software queue for scheduling later
2348 TX_STAT_INC(txq
->axq_qnum
, a_queued_sw
);
2349 __skb_queue_tail(&tid
->buf_q
, skb
);
2350 if (!txctl
->an
->sleeping
)
2351 ath_tx_queue_tid(sc
, txq
, tid
);
2353 ath_txq_schedule(sc
, txq
);
2357 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
2359 ath_txq_skb_done(sc
, txq
, skb
);
2361 dev_kfree_skb_any(skb
);
2363 ieee80211_free_txskb(sc
->hw
, skb
);
2367 bf
->bf_state
.bfs_paprd
= txctl
->paprd
;
2370 bf
->bf_state
.bfs_paprd_timestamp
= jiffies
;
2372 ath_set_rates(vif
, sta
, bf
);
2373 ath_tx_send_normal(sc
, txq
, tid
, skb
);
2376 ath_txq_unlock(sc
, txq
);
2381 void ath_tx_cabq(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2382 struct sk_buff
*skb
)
2384 struct ath_softc
*sc
= hw
->priv
;
2385 struct ath_tx_control txctl
= {
2386 .txq
= sc
->beacon
.cabq
2388 struct ath_tx_info info
= {};
2389 struct ieee80211_hdr
*hdr
;
2390 struct ath_buf
*bf_tail
= NULL
;
2397 sc
->cur_chan
->beacon
.beacon_interval
* 1000 *
2398 sc
->cur_chan
->beacon
.dtim_period
/ ATH_BCBUF
;
2401 struct ath_frame_info
*fi
= get_frame_info(skb
);
2403 if (ath_tx_prepare(hw
, skb
, &txctl
))
2406 bf
= ath_tx_setup_buffer(sc
, txctl
.txq
, NULL
, skb
);
2411 ath_set_rates(vif
, NULL
, bf
);
2412 ath_buf_set_rate(sc
, bf
, &info
, fi
->framelen
, false);
2413 duration
+= info
.rates
[0].PktDuration
;
2415 bf_tail
->bf_next
= bf
;
2417 list_add_tail(&bf
->list
, &bf_q
);
2421 if (duration
> max_duration
)
2424 skb
= ieee80211_get_buffered_bc(hw
, vif
);
2428 ieee80211_free_txskb(hw
, skb
);
2430 if (list_empty(&bf_q
))
2433 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
2434 hdr
= (struct ieee80211_hdr
*) bf
->bf_mpdu
->data
;
2436 if (hdr
->frame_control
& cpu_to_le16(IEEE80211_FCTL_MOREDATA
)) {
2437 hdr
->frame_control
&= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
2438 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
2439 sizeof(*hdr
), DMA_TO_DEVICE
);
2442 ath_txq_lock(sc
, txctl
.txq
);
2443 ath_tx_fill_desc(sc
, bf
, txctl
.txq
, 0);
2444 ath_tx_txqaddbuf(sc
, txctl
.txq
, &bf_q
, false);
2445 TX_STAT_INC(txctl
.txq
->axq_qnum
, queued
);
2446 ath_txq_unlock(sc
, txctl
.txq
);
2453 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
2454 int tx_flags
, struct ath_txq
*txq
)
2456 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2457 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2458 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
2459 int padpos
, padsize
;
2460 unsigned long flags
;
2462 ath_dbg(common
, XMIT
, "TX complete: skb: %p\n", skb
);
2464 if (sc
->sc_ah
->caldata
)
2465 set_bit(PAPRD_PACKET_SENT
, &sc
->sc_ah
->caldata
->cal_flags
);
2467 if (!(tx_flags
& ATH_TX_ERROR
)) {
2468 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
2469 tx_info
->flags
|= IEEE80211_TX_STAT_NOACK_TRANSMITTED
;
2471 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
2474 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2475 padsize
= padpos
& 3;
2476 if (padsize
&& skb
->len
>padpos
+padsize
) {
2478 * Remove MAC header padding before giving the frame back to
2481 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
2482 skb_pull(skb
, padsize
);
2485 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
2486 if ((sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) && !txq
->axq_depth
) {
2487 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
2489 "Going back to sleep after having received TX status (0x%lx)\n",
2490 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
2492 PS_WAIT_FOR_PSPOLL_DATA
|
2493 PS_WAIT_FOR_TX_ACK
));
2495 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
2497 __skb_queue_tail(&txq
->complete_q
, skb
);
2498 ath_txq_skb_done(sc
, txq
, skb
);
2501 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
2502 struct ath_txq
*txq
, struct list_head
*bf_q
,
2503 struct ath_tx_status
*ts
, int txok
)
2505 struct sk_buff
*skb
= bf
->bf_mpdu
;
2506 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2507 unsigned long flags
;
2511 tx_flags
|= ATH_TX_ERROR
;
2513 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
2514 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2516 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
, skb
->len
, DMA_TO_DEVICE
);
2517 bf
->bf_buf_addr
= 0;
2519 goto skip_tx_complete
;
2521 if (bf
->bf_state
.bfs_paprd
) {
2522 if (time_after(jiffies
,
2523 bf
->bf_state
.bfs_paprd_timestamp
+
2524 msecs_to_jiffies(ATH_PAPRD_TIMEOUT
)))
2525 dev_kfree_skb_any(skb
);
2527 complete(&sc
->paprd_complete
);
2529 ath_debug_stat_tx(sc
, bf
, ts
, txq
, tx_flags
);
2530 ath_tx_complete(sc
, skb
, tx_flags
, txq
);
2533 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2534 * accidentally reference it later.
2539 * Return the list of ath_buf of this mpdu to free queue
2541 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
2542 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
2543 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
2546 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
2547 struct ath_tx_status
*ts
, int nframes
, int nbad
,
2550 struct sk_buff
*skb
= bf
->bf_mpdu
;
2551 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2552 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2553 struct ieee80211_hw
*hw
= sc
->hw
;
2554 struct ath_hw
*ah
= sc
->sc_ah
;
2558 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2560 tx_rateindex
= ts
->ts_rateindex
;
2561 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2563 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
2564 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2566 BUG_ON(nbad
> nframes
);
2568 tx_info
->status
.ampdu_len
= nframes
;
2569 tx_info
->status
.ampdu_ack_len
= nframes
- nbad
;
2571 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2572 (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
) == 0) {
2574 * If an underrun error is seen assume it as an excessive
2575 * retry only if max frame trigger level has been reached
2576 * (2 KB for single stream, and 4 KB for dual stream).
2577 * Adjust the long retry as if the frame was tried
2578 * hw->max_rate_tries times to affect how rate control updates
2579 * PER for the failed rate.
2580 * In case of congestion on the bus penalizing this type of
2581 * underruns should help hardware actually transmit new frames
2582 * successfully by eventually preferring slower rates.
2583 * This itself should also alleviate congestion on the bus.
2585 if (unlikely(ts
->ts_flags
& (ATH9K_TX_DATA_UNDERRUN
|
2586 ATH9K_TX_DELIM_UNDERRUN
)) &&
2587 ieee80211_is_data(hdr
->frame_control
) &&
2588 ah
->tx_trig_level
>= sc
->sc_ah
->config
.max_txtrig_level
)
2589 tx_info
->status
.rates
[tx_rateindex
].count
=
2593 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2594 tx_info
->status
.rates
[i
].count
= 0;
2595 tx_info
->status
.rates
[i
].idx
= -1;
2598 tx_info
->status
.rates
[tx_rateindex
].count
= ts
->ts_longretry
+ 1;
2601 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2603 struct ath_hw
*ah
= sc
->sc_ah
;
2604 struct ath_common
*common
= ath9k_hw_common(ah
);
2605 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2606 struct list_head bf_head
;
2607 struct ath_desc
*ds
;
2608 struct ath_tx_status ts
;
2611 ath_dbg(common
, QUEUE
, "tx queue %d (%x), link %p\n",
2612 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2615 ath_txq_lock(sc
, txq
);
2617 if (test_bit(ATH_OP_HW_RESET
, &common
->op_flags
))
2620 if (list_empty(&txq
->axq_q
)) {
2621 txq
->axq_link
= NULL
;
2622 ath_txq_schedule(sc
, txq
);
2625 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2628 * There is a race condition that a BH gets scheduled
2629 * after sw writes TxE and before hw re-load the last
2630 * descriptor to get the newly chained one.
2631 * Software must keep the last DONE descriptor as a
2632 * holding descriptor - software does so by marking
2633 * it with the STALE flag.
2636 if (bf
->bf_state
.stale
) {
2638 if (list_is_last(&bf_held
->list
, &txq
->axq_q
))
2641 bf
= list_entry(bf_held
->list
.next
, struct ath_buf
,
2645 lastbf
= bf
->bf_lastbf
;
2646 ds
= lastbf
->bf_desc
;
2648 memset(&ts
, 0, sizeof(ts
));
2649 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2650 if (status
== -EINPROGRESS
)
2653 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2656 * Remove ath_buf's of the same transmit unit from txq,
2657 * however leave the last descriptor back as the holding
2658 * descriptor for hw.
2660 lastbf
->bf_state
.stale
= true;
2661 INIT_LIST_HEAD(&bf_head
);
2662 if (!list_is_singular(&lastbf
->list
))
2663 list_cut_position(&bf_head
,
2664 &txq
->axq_q
, lastbf
->list
.prev
);
2667 list_del(&bf_held
->list
);
2668 ath_tx_return_buffer(sc
, bf_held
);
2671 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2673 ath_txq_unlock_complete(sc
, txq
);
2676 void ath_tx_tasklet(struct ath_softc
*sc
)
2678 struct ath_hw
*ah
= sc
->sc_ah
;
2679 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1) & ah
->intr_txqs
;
2682 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2683 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2684 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2688 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2690 struct ath_tx_status ts
;
2691 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2692 struct ath_hw
*ah
= sc
->sc_ah
;
2693 struct ath_txq
*txq
;
2694 struct ath_buf
*bf
, *lastbf
;
2695 struct list_head bf_head
;
2696 struct list_head
*fifo_list
;
2700 if (test_bit(ATH_OP_HW_RESET
, &common
->op_flags
))
2703 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&ts
);
2704 if (status
== -EINPROGRESS
)
2706 if (status
== -EIO
) {
2707 ath_dbg(common
, XMIT
, "Error processing tx status\n");
2711 /* Process beacon completions separately */
2712 if (ts
.qid
== sc
->beacon
.beaconq
) {
2713 sc
->beacon
.tx_processed
= true;
2714 sc
->beacon
.tx_last
= !(ts
.ts_status
& ATH9K_TXERR_MASK
);
2716 if (ath9k_is_chanctx_enabled()) {
2717 ath_chanctx_event(sc
, NULL
,
2718 ATH_CHANCTX_EVENT_BEACON_SENT
);
2721 ath9k_csa_update(sc
);
2725 txq
= &sc
->tx
.txq
[ts
.qid
];
2727 ath_txq_lock(sc
, txq
);
2729 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2731 fifo_list
= &txq
->txq_fifo
[txq
->txq_tailidx
];
2732 if (list_empty(fifo_list
)) {
2733 ath_txq_unlock(sc
, txq
);
2737 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2738 if (bf
->bf_state
.stale
) {
2739 list_del(&bf
->list
);
2740 ath_tx_return_buffer(sc
, bf
);
2741 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2744 lastbf
= bf
->bf_lastbf
;
2746 INIT_LIST_HEAD(&bf_head
);
2747 if (list_is_last(&lastbf
->list
, fifo_list
)) {
2748 list_splice_tail_init(fifo_list
, &bf_head
);
2749 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2751 if (!list_empty(&txq
->axq_q
)) {
2752 struct list_head bf_q
;
2754 INIT_LIST_HEAD(&bf_q
);
2755 txq
->axq_link
= NULL
;
2756 list_splice_tail_init(&txq
->axq_q
, &bf_q
);
2757 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, true);
2760 lastbf
->bf_state
.stale
= true;
2762 list_cut_position(&bf_head
, fifo_list
,
2766 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2767 ath_txq_unlock_complete(sc
, txq
);
2775 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2777 struct ath_descdma
*dd
= &sc
->txsdma
;
2778 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2780 dd
->dd_desc_len
= size
* txs_len
;
2781 dd
->dd_desc
= dmam_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2782 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2789 static int ath_tx_edma_init(struct ath_softc
*sc
)
2793 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2795 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2796 sc
->txsdma
.dd_desc_paddr
,
2797 ATH_TXSTATUS_RING_SIZE
);
2802 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2804 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2807 spin_lock_init(&sc
->tx
.txbuflock
);
2809 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2813 "Failed to allocate tx descriptors: %d\n", error
);
2817 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2818 "beacon", ATH_BCBUF
, 1, 1);
2821 "Failed to allocate beacon descriptors: %d\n", error
);
2825 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2827 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2828 error
= ath_tx_edma_init(sc
);
2833 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2835 struct ath_atx_tid
*tid
;
2838 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2839 tidno
< IEEE80211_NUM_TIDS
;
2843 tid
->seq_start
= tid
->seq_next
= 0;
2844 tid
->baw_size
= WME_MAX_BA
;
2845 tid
->baw_head
= tid
->baw_tail
= 0;
2846 tid
->active
= false;
2847 tid
->clear_ps_filter
= true;
2848 __skb_queue_head_init(&tid
->buf_q
);
2849 __skb_queue_head_init(&tid
->retry_q
);
2850 INIT_LIST_HEAD(&tid
->list
);
2851 acno
= TID_TO_WME_AC(tidno
);
2852 tid
->txq
= sc
->tx
.txq_map
[acno
];
2856 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2858 struct ath_atx_tid
*tid
;
2859 struct ath_txq
*txq
;
2862 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2863 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
2867 ath_txq_lock(sc
, txq
);
2869 if (!list_empty(&tid
->list
))
2870 list_del_init(&tid
->list
);
2872 ath_tid_drain(sc
, txq
, tid
);
2873 tid
->active
= false;
2875 ath_txq_unlock(sc
, txq
);
2879 #ifdef CONFIG_ATH9K_TX99
2881 int ath9k_tx99_send(struct ath_softc
*sc
, struct sk_buff
*skb
,
2882 struct ath_tx_control
*txctl
)
2884 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2885 struct ath_frame_info
*fi
= get_frame_info(skb
);
2886 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2888 int padpos
, padsize
;
2890 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2891 padsize
= padpos
& 3;
2893 if (padsize
&& skb
->len
> padpos
) {
2894 if (skb_headroom(skb
) < padsize
) {
2895 ath_dbg(common
, XMIT
,
2896 "tx99 padding failed\n");
2900 skb_push(skb
, padsize
);
2901 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
2904 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
2905 fi
->framelen
= skb
->len
+ FCS_LEN
;
2906 fi
->keytype
= ATH9K_KEY_TYPE_CLEAR
;
2908 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, NULL
, skb
);
2910 ath_dbg(common
, XMIT
, "tx99 buffer setup failed\n");
2914 ath_set_rates(sc
->tx99_vif
, NULL
, bf
);
2916 ath9k_hw_set_desc_link(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_daddr
);
2917 ath9k_hw_tx99_start(sc
->sc_ah
, txctl
->txq
->axq_qnum
);
2919 ath_tx_send_normal(sc
, txctl
->txq
, NULL
, skb
);
2924 #endif /* CONFIG_ATH9K_TX99 */