| blob | e432715e02d89dedcce89615d855233662c26d82 |
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
30 #ifndef __il_4965_h__
31 #define __il_4965_h__
39 /* configuration for the _4965 devices */
45 /* tx queue */
49 /* RXON */
52 /* uCode */
55 /* lib */
65 /* rx */
74 /* tx */
96 /*
97 * Acquire il->lock before calling this function !
98 */
100 /**
101 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
102 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
103 * @scd_retry: (1) Indicates queue will be used in aggregation mode
104 *
105 * NOTE: Acquire il->lock before calling this function !
106 */
110 /* scan */
113 /* station mgmt */
117 /* hcmd */
120 #ifdef CONFIG_IWLEGACY_DEBUG
122 #else
125 {
127 }
128 #endif
130 /* station management */
154 /* rate */
157 {
159 }
161 /* eeprom */
167 /* mac80211 handlers (for 4965) */
188 void
194 /* EEPROM */
195 #define IL4965_EEPROM_IMG_SIZE 1024
197 /*
198 * uCode queue management definitions ...
199 * The first queue used for block-ack aggregation is #7 (4965 only).
200 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
201 */
202 #define IL49_FIRST_AMPDU_QUEUE 7
204 /* Sizes and addresses for instruction and data memory (SRAM) in
205 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
206 #define IL49_RTC_INST_LOWER_BOUND (0x000000)
207 #define IL49_RTC_INST_UPPER_BOUND (0x018000)
209 #define IL49_RTC_DATA_LOWER_BOUND (0x800000)
210 #define IL49_RTC_DATA_UPPER_BOUND (0x80A000)
212 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
213 IL49_RTC_INST_LOWER_BOUND)
214 #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
215 IL49_RTC_DATA_LOWER_BOUND)
217 #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
218 #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
220 /* Size of uCode instruction memory in bootstrap state machine */
221 #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
225 {
228 }
230 /********************* START TEMPERATURE *************************************/
232 /**
233 * 4965 temperature calculation.
234 *
235 * The driver must calculate the device temperature before calculating
236 * a txpower setting (amplifier gain is temperature dependent). The
237 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
238 * values used for the life of the driver, and one of which (R4) is the
239 * real-time temperature indicator.
240 *
241 * uCode provides all 4 values to the driver via the "initialize alive"
242 * notification (see struct il4965_init_alive_resp). After the runtime uCode
243 * image loads, uCode updates the R4 value via stats notifications
244 * (see N_STATS), which occur after each received beacon
245 * when associated, or can be requested via C_STATS.
246 *
247 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
248 * must sign-extend to 32 bits before applying formula below.
249 *
250 * Formula:
251 *
252 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
253 *
254 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
255 * an additional correction, which should be centered around 0 degrees
256 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
257 * centering the 97/100 correction around 0 degrees K.
258 *
259 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
260 * temperature with factory-measured temperatures when calculating txpower
261 * settings.
262 */
263 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
264 #define TEMPERATURE_CALIB_A_VAL 259
266 /* Limit range of calculated temperature to be between these Kelvin values */
267 #define IL_TX_POWER_TEMPERATURE_MIN (263)
268 #define IL_TX_POWER_TEMPERATURE_MAX (410)
270 #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
271 ((t) < IL_TX_POWER_TEMPERATURE_MIN || \
272 (t) > IL_TX_POWER_TEMPERATURE_MAX)
275 /********************* END TEMPERATURE ***************************************/
277 /********************* START TXPOWER *****************************************/
279 /**
280 * 4965 txpower calculations rely on information from three sources:
281 *
282 * 1) EEPROM
283 * 2) "initialize" alive notification
284 * 3) stats notifications
285 *
286 * EEPROM data consists of:
287 *
288 * 1) Regulatory information (max txpower and channel usage flags) is provided
289 * separately for each channel that can possibly supported by 4965.
290 * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz
291 * (legacy) channels.
292 *
293 * See struct il4965_eeprom_channel for format, and struct il4965_eeprom
294 * for locations in EEPROM.
295 *
296 * 2) Factory txpower calibration information is provided separately for
297 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
298 * but 5 GHz has several sub-bands.
299 *
300 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
301 *
302 * See struct il4965_eeprom_calib_info (and the tree of structures
303 * contained within it) for format, and struct il4965_eeprom for
304 * locations in EEPROM.
305 *
306 * "Initialization alive" notification (see struct il4965_init_alive_resp)
307 * consists of:
308 *
309 * 1) Temperature calculation parameters.
310 *
311 * 2) Power supply voltage measurement.
312 *
313 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
314 *
315 * Statistics notifications deliver:
316 *
317 * 1) Current values for temperature param R4.
318 */
320 /**
321 * To calculate a txpower setting for a given desired target txpower, channel,
322 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
323 * support MIMO and transmit diversity), driver must do the following:
324 *
325 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
326 * Do not exceed regulatory limit; reduce target txpower if necessary.
327 *
328 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
329 * 2 transmitters will be used simultaneously; driver must reduce the
330 * regulatory limit by 3 dB (half-power) for each transmitter, so the
331 * combined total output of the 2 transmitters is within regulatory limits.
332 *
333 *
334 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
335 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
336 * reduce target txpower if necessary.
337 *
338 * Backoff values below are in 1/2 dB units (equivalent to steps in
339 * txpower gain tables):
340 *
341 * OFDM 6 - 36 MBit: 10 steps (5 dB)
342 * OFDM 48 MBit: 15 steps (7.5 dB)
343 * OFDM 54 MBit: 17 steps (8.5 dB)
344 * OFDM 60 MBit: 20 steps (10 dB)
345 * CCK all rates: 10 steps (5 dB)
346 *
347 * Backoff values apply to saturation txpower on a per-transmitter basis;
348 * when using MIMO (2 transmitters), each transmitter uses the same
349 * saturation level provided in EEPROM, and the same backoff values;
350 * no reduction (such as with regulatory txpower limits) is required.
351 *
352 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
353 * widths and 40 Mhz (.11n HT40) channel widths; there is no separate
354 * factory measurement for ht40 channels.
355 *
356 * The result of this step is the final target txpower. The rest of
357 * the steps figure out the proper settings for the device to achieve
358 * that target txpower.
359 *
360 *
361 * 3) Determine (EEPROM) calibration sub band for the target channel, by
362 * comparing against first and last channels in each sub band
363 * (see struct il4965_eeprom_calib_subband_info).
364 *
365 *
366 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
367 * referencing the 2 factory-measured (sample) channels within the sub band.
368 *
369 * Interpolation is based on difference between target channel's frequency
370 * and the sample channels' frequencies. Since channel numbers are based
371 * on frequency (5 MHz between each channel number), this is equivalent
372 * to interpolating based on channel number differences.
373 *
374 * Note that the sample channels may or may not be the channels at the
375 * edges of the sub band. The target channel may be "outside" of the
376 * span of the sampled channels.
377 *
378 * Driver may choose the pair (for 2 Tx chains) of measurements (see
379 * struct il4965_eeprom_calib_ch_info) for which the actual measured
380 * txpower comes closest to the desired txpower. Usually, though,
381 * the middle set of measurements is closest to the regulatory limits,
382 * and is therefore a good choice for all txpower calculations (this
383 * assumes that high accuracy is needed for maximizing legal txpower,
384 * while lower txpower configurations do not need as much accuracy).
385 *
386 * Driver should interpolate both members of the chosen measurement pair,
387 * i.e. for both Tx chains (radio transmitters), unless the driver knows
388 * that only one of the chains will be used (e.g. only one tx antenna
389 * connected, but this should be unusual). The rate scaling algorithm
390 * switches antennas to find best performance, so both Tx chains will
391 * be used (although only one at a time) even for non-MIMO transmissions.
392 *
393 * Driver should interpolate factory values for temperature, gain table
394 * idx, and actual power. The power amplifier detector values are
395 * not used by the driver.
396 *
397 * Sanity check: If the target channel happens to be one of the sample
398 * channels, the results should agree with the sample channel's
399 * measurements!
400 *
401 *
402 * 5) Find difference between desired txpower and (interpolated)
403 * factory-measured txpower. Using (interpolated) factory gain table idx
404 * (shown elsewhere) as a starting point, adjust this idx lower to
405 * increase txpower, or higher to decrease txpower, until the target
406 * txpower is reached. Each step in the gain table is 1/2 dB.
407 *
408 * For example, if factory measured txpower is 16 dBm, and target txpower
409 * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower
410 * by 3 dB.
411 *
412 *
413 * 6) Find difference between current device temperature and (interpolated)
414 * factory-measured temperature for sub-band. Factory values are in
415 * degrees Celsius. To calculate current temperature, see comments for
416 * "4965 temperature calculation".
417 *
418 * If current temperature is higher than factory temperature, driver must
419 * increase gain (lower gain table idx), and vice verse.
420 *
421 * Temperature affects gain differently for different channels:
422 *
423 * 2.4 GHz all channels: 3.5 degrees per half-dB step
424 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
425 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
426 *
427 * NOTE: Temperature can increase rapidly when transmitting, especially
428 * with heavy traffic at high txpowers. Driver should update
429 * temperature calculations often under these conditions to
430 * maintain strong txpower in the face of rising temperature.
431 *
432 *
433 * 7) Find difference between current power supply voltage indicator
434 * (from "initialize alive") and factory-measured power supply voltage
435 * indicator (EEPROM).
436 *
437 * If the current voltage is higher (indicator is lower) than factory
438 * voltage, gain should be reduced (gain table idx increased) by:
439 *
440 * (eeprom - current) / 7
441 *
442 * If the current voltage is lower (indicator is higher) than factory
443 * voltage, gain should be increased (gain table idx decreased) by:
444 *
445 * 2 * (current - eeprom) / 7
446 *
447 * If number of idx steps in either direction turns out to be > 2,
448 * something is wrong ... just use 0.
449 *
450 * NOTE: Voltage compensation is independent of band/channel.
451 *
452 * NOTE: "Initialize" uCode measures current voltage, which is assumed
453 * to be constant after this initial measurement. Voltage
454 * compensation for txpower (number of steps in gain table)
455 * may be calculated once and used until the next uCode bootload.
456 *
457 *
458 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
459 * adjust txpower for each transmitter chain, so txpower is balanced
460 * between the two chains. There are 5 pairs of tx_atten[group][chain]
461 * values in "initialize alive", one pair for each of 5 channel ranges:
462 *
463 * Group 0: 5 GHz channel 34-43
464 * Group 1: 5 GHz channel 44-70
465 * Group 2: 5 GHz channel 71-124
466 * Group 3: 5 GHz channel 125-200
467 * Group 4: 2.4 GHz all channels
468 *
469 * Add the tx_atten[group][chain] value to the idx for the target chain.
470 * The values are signed, but are in pairs of 0 and a non-negative number,
471 * so as to reduce gain (if necessary) of the "hotter" channel. This
472 * avoids any need to double-check for regulatory compliance after
473 * this step.
474 *
475 *
476 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
477 * value to the idx:
478 *
479 * Hardware rev B: 9 steps (4.5 dB)
480 * Hardware rev C: 5 steps (2.5 dB)
481 *
482 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
483 * bits [3:2], 1 = B, 2 = C.
484 *
485 * NOTE: This compensation is in addition to any saturation backoff that
486 * might have been applied in an earlier step.
487 *
488 *
489 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
490 *
491 * Limit the adjusted idx to stay within the table!
492 *
493 *
494 * 11) Read gain table entries for DSP and radio gain, place into appropriate
495 * location(s) in command (struct il4965_txpowertable_cmd).
496 */
498 /**
499 * When MIMO is used (2 transmitters operating simultaneously), driver should
500 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
501 * for the device. That is, use half power for each transmitter, so total
502 * txpower is within regulatory limits.
503 *
504 * The value "6" represents number of steps in gain table to reduce power 3 dB.
505 * Each step is 1/2 dB.
506 */
507 #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
509 /**
510 * CCK gain compensation.
511 *
512 * When calculating txpowers for CCK, after making sure that the target power
513 * is within regulatory and saturation limits, driver must additionally
514 * back off gain by adding these values to the gain table idx.
515 *
516 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
517 * bits [3:2], 1 = B, 2 = C.
518 */
519 #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
520 #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
522 /*
523 * 4965 power supply voltage compensation for txpower
524 */
525 #define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7)
527 /**
528 * Gain tables.
529 *
530 * The following tables contain pair of values for setting txpower, i.e.
531 * gain settings for the output of the device's digital signal processor (DSP),
532 * and for the analog gain structure of the transmitter.
533 *
534 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
535 * are *relative* steps, not indications of absolute output power. Output
536 * power varies with temperature, voltage, and channel frequency, and also
537 * requires consideration of average power (to satisfy regulatory constraints),
538 * and peak power (to avoid distortion of the output signal).
539 *
540 * Each entry contains two values:
541 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
542 * linear value that multiplies the output of the digital signal processor,
543 * before being sent to the analog radio.
544 * 2) Radio gain. This sets the analog gain of the radio Tx path.
545 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
546 *
547 * EEPROM contains factory calibration data for txpower. This maps actual
548 * measured txpower levels to gain settings in the "well known" tables
549 * below ("well-known" means here that both factory calibration *and* the
550 * driver work with the same table).
551 *
552 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
553 * has an extension (into negative idxes), in case the driver needs to
554 * boost power setting for high device temperatures (higher than would be
555 * present during factory calibration). A 5 Ghz EEPROM idx of "40"
556 * corresponds to the 49th entry in the table used by the driver.
557 */
561 /**
562 * 2.4 GHz gain table
563 *
564 * Index Dsp gain Radio gain
565 * 0 110 0x3f (highest gain)
566 * 1 104 0x3f
567 * 2 98 0x3f
568 * 3 110 0x3e
569 * 4 104 0x3e
570 * 5 98 0x3e
571 * 6 110 0x3d
572 * 7 104 0x3d
573 * 8 98 0x3d
574 * 9 110 0x3c
575 * 10 104 0x3c
576 * 11 98 0x3c
577 * 12 110 0x3b
578 * 13 104 0x3b
579 * 14 98 0x3b
580 * 15 110 0x3a
581 * 16 104 0x3a
582 * 17 98 0x3a
583 * 18 110 0x39
584 * 19 104 0x39
585 * 20 98 0x39
586 * 21 110 0x38
587 * 22 104 0x38
588 * 23 98 0x38
589 * 24 110 0x37
590 * 25 104 0x37
591 * 26 98 0x37
592 * 27 110 0x36
593 * 28 104 0x36
594 * 29 98 0x36
595 * 30 110 0x35
596 * 31 104 0x35
597 * 32 98 0x35
598 * 33 110 0x34
599 * 34 104 0x34
600 * 35 98 0x34
601 * 36 110 0x33
602 * 37 104 0x33
603 * 38 98 0x33
604 * 39 110 0x32
605 * 40 104 0x32
606 * 41 98 0x32
607 * 42 110 0x31
608 * 43 104 0x31
609 * 44 98 0x31
610 * 45 110 0x30
611 * 46 104 0x30
612 * 47 98 0x30
613 * 48 110 0x6
614 * 49 104 0x6
615 * 50 98 0x6
616 * 51 110 0x5
617 * 52 104 0x5
618 * 53 98 0x5
619 * 54 110 0x4
620 * 55 104 0x4
621 * 56 98 0x4
622 * 57 110 0x3
623 * 58 104 0x3
624 * 59 98 0x3
625 * 60 110 0x2
626 * 61 104 0x2
627 * 62 98 0x2
628 * 63 110 0x1
629 * 64 104 0x1
630 * 65 98 0x1
631 * 66 110 0x0
632 * 67 104 0x0
633 * 68 98 0x0
634 * 69 97 0
635 * 70 96 0
636 * 71 95 0
637 * 72 94 0
638 * 73 93 0
639 * 74 92 0
640 * 75 91 0
641 * 76 90 0
642 * 77 89 0
643 * 78 88 0
644 * 79 87 0
645 * 80 86 0
646 * 81 85 0
647 * 82 84 0
648 * 83 83 0
649 * 84 82 0
650 * 85 81 0
651 * 86 80 0
652 * 87 79 0
653 * 88 78 0
654 * 89 77 0
655 * 90 76 0
656 * 91 75 0
657 * 92 74 0
658 * 93 73 0
659 * 94 72 0
660 * 95 71 0
661 * 96 70 0
662 * 97 69 0
663 * 98 68 0
664 */
666 /**
667 * 5 GHz gain table
668 *
669 * Index Dsp gain Radio gain
670 * -9 123 0x3F (highest gain)
671 * -8 117 0x3F
672 * -7 110 0x3F
673 * -6 104 0x3F
674 * -5 98 0x3F
675 * -4 110 0x3E
676 * -3 104 0x3E
677 * -2 98 0x3E
678 * -1 110 0x3D
679 * 0 104 0x3D
680 * 1 98 0x3D
681 * 2 110 0x3C
682 * 3 104 0x3C
683 * 4 98 0x3C
684 * 5 110 0x3B
685 * 6 104 0x3B
686 * 7 98 0x3B
687 * 8 110 0x3A
688 * 9 104 0x3A
689 * 10 98 0x3A
690 * 11 110 0x39
691 * 12 104 0x39
692 * 13 98 0x39
693 * 14 110 0x38
694 * 15 104 0x38
695 * 16 98 0x38
696 * 17 110 0x37
697 * 18 104 0x37
698 * 19 98 0x37
699 * 20 110 0x36
700 * 21 104 0x36
701 * 22 98 0x36
702 * 23 110 0x35
703 * 24 104 0x35
704 * 25 98 0x35
705 * 26 110 0x34
706 * 27 104 0x34
707 * 28 98 0x34
708 * 29 110 0x33
709 * 30 104 0x33
710 * 31 98 0x33
711 * 32 110 0x32
712 * 33 104 0x32
713 * 34 98 0x32
714 * 35 110 0x31
715 * 36 104 0x31
716 * 37 98 0x31
717 * 38 110 0x30
718 * 39 104 0x30
719 * 40 98 0x30
720 * 41 110 0x25
721 * 42 104 0x25
722 * 43 98 0x25
723 * 44 110 0x24
724 * 45 104 0x24
725 * 46 98 0x24
726 * 47 110 0x23
727 * 48 104 0x23
728 * 49 98 0x23
729 * 50 110 0x22
730 * 51 104 0x18
731 * 52 98 0x18
732 * 53 110 0x17
733 * 54 104 0x17
734 * 55 98 0x17
735 * 56 110 0x16
736 * 57 104 0x16
737 * 58 98 0x16
738 * 59 110 0x15
739 * 60 104 0x15
740 * 61 98 0x15
741 * 62 110 0x14
742 * 63 104 0x14
743 * 64 98 0x14
744 * 65 110 0x13
745 * 66 104 0x13
746 * 67 98 0x13
747 * 68 110 0x12
748 * 69 104 0x08
749 * 70 98 0x08
750 * 71 110 0x07
751 * 72 104 0x07
752 * 73 98 0x07
753 * 74 110 0x06
754 * 75 104 0x06
755 * 76 98 0x06
756 * 77 110 0x05
757 * 78 104 0x05
758 * 79 98 0x05
759 * 80 110 0x04
760 * 81 104 0x04
761 * 82 98 0x04
762 * 83 110 0x03
763 * 84 104 0x03
764 * 85 98 0x03
765 * 86 110 0x02
766 * 87 104 0x02
767 * 88 98 0x02
768 * 89 110 0x01
769 * 90 104 0x01
770 * 91 98 0x01
771 * 92 110 0x00
772 * 93 104 0x00
773 * 94 98 0x00
774 * 95 93 0x00
775 * 96 88 0x00
776 * 97 83 0x00
777 * 98 78 0x00
778 */
780 /**
781 * Sanity checks and default values for EEPROM regulatory levels.
782 * If EEPROM values fall outside MIN/MAX range, use default values.
783 *
784 * Regulatory limits refer to the maximum average txpower allowed by
785 * regulatory agencies in the geographies in which the device is meant
786 * to be operated. These limits are SKU-specific (i.e. geography-specific),
787 * and channel-specific; each channel has an individual regulatory limit
788 * listed in the EEPROM.
789 *
790 * Units are in half-dBm (i.e. "34" means 17 dBm).
791 */
792 #define IL_TX_POWER_DEFAULT_REGULATORY_24 (34)
793 #define IL_TX_POWER_DEFAULT_REGULATORY_52 (34)
794 #define IL_TX_POWER_REGULATORY_MIN (0)
795 #define IL_TX_POWER_REGULATORY_MAX (34)
797 /**
798 * Sanity checks and default values for EEPROM saturation levels.
799 * If EEPROM values fall outside MIN/MAX range, use default values.
800 *
801 * Saturation is the highest level that the output power amplifier can produce
802 * without significant clipping distortion. This is a "peak" power level.
803 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
804 * require differing amounts of backoff, relative to their average power output,
805 * in order to avoid clipping distortion.
806 *
807 * Driver must make sure that it is violating neither the saturation limit,
808 * nor the regulatory limit, when calculating Tx power settings for various
809 * rates.
810 *
811 * Units are in half-dBm (i.e. "38" means 19 dBm).
812 */
813 #define IL_TX_POWER_DEFAULT_SATURATION_24 (38)
814 #define IL_TX_POWER_DEFAULT_SATURATION_52 (38)
815 #define IL_TX_POWER_SATURATION_MIN (20)
816 #define IL_TX_POWER_SATURATION_MAX (50)
818 /**
819 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
820 * and thermal Txpower calibration.
821 *
822 * When calculating txpower, driver must compensate for current device
823 * temperature; higher temperature requires higher gain. Driver must calculate
824 * current temperature (see "4965 temperature calculation"), then compare vs.
825 * factory calibration temperature in EEPROM; if current temperature is higher
826 * than factory temperature, driver must *increase* gain by proportions shown
827 * in table below. If current temperature is lower than factory, driver must
828 * *decrease* gain.
829 *
830 * Different frequency ranges require different compensation, as shown below.
831 */
832 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
833 #define CALIB_IL_TX_ATTEN_GR1_FCH 34
834 #define CALIB_IL_TX_ATTEN_GR1_LCH 43
836 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
837 #define CALIB_IL_TX_ATTEN_GR2_FCH 44
838 #define CALIB_IL_TX_ATTEN_GR2_LCH 70
840 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
841 #define CALIB_IL_TX_ATTEN_GR3_FCH 71
842 #define CALIB_IL_TX_ATTEN_GR3_LCH 124
844 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
845 #define CALIB_IL_TX_ATTEN_GR4_FCH 125
846 #define CALIB_IL_TX_ATTEN_GR4_LCH 200
848 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
849 #define CALIB_IL_TX_ATTEN_GR5_FCH 1
850 #define CALIB_IL_TX_ATTEN_GR5_LCH 20
858 CALIB_CH_GROUP_MAX
859 };
861 /********************* END TXPOWER *****************************************/
863 /**
864 * Tx/Rx Queues
865 *
866 * Most communication between driver and 4965 is via queues of data buffers.
867 * For example, all commands that the driver issues to device's embedded
868 * controller (uCode) are via the command queue (one of the Tx queues). All
869 * uCode command responses/replies/notifications, including Rx frames, are
870 * conveyed from uCode to driver via the Rx queue.
871 *
872 * Most support for these queues, including handshake support, resides in
873 * structures in host DRAM, shared between the driver and the device. When
874 * allocating this memory, the driver must make sure that data written by
875 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
876 * cache memory), so DRAM and cache are consistent, and the device can
877 * immediately see changes made by the driver.
878 *
879 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
880 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
881 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
882 */
883 #define IL49_NUM_FIFOS 7
884 #define IL49_CMD_FIFO_NUM 4
885 #define IL49_NUM_QUEUES 16
886 #define IL49_NUM_AMPDU_QUEUES 8
888 /**
889 * struct il4965_schedq_bc_tbl
890 *
891 * Byte Count table
892 *
893 * Each Tx queue uses a byte-count table containing 320 entries:
894 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
895 * duplicate the first 64 entries (to avoid wrap-around within a Tx win;
896 * max Tx win is 64 TFDs).
897 *
898 * When driver sets up a new TFD, it must also enter the total byte count
899 * of the frame to be transmitted into the corresponding entry in the byte
900 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver
901 * must duplicate the byte count entry in corresponding idx 256-319.
902 *
903 * padding puts each byte count table on a 1024-byte boundary;
904 * 4965 assumes tables are separated by 1024 bytes.
905 */
911 #define IL4965_RTC_INST_LOWER_BOUND (0x000000)
913 /* RSSI to dBm */
914 #define IL4965_RSSI_OFFSET 44
916 /* PCI registers */
917 #define PCI_CFG_RETRY_TIMEOUT 0x041
919 #define IL4965_DEFAULT_TX_RETRY 15
921 /* EEPROM */
922 #define IL4965_FIRST_AMPDU_QUEUE 10
924 /* Calibration */
930 /* Debug */
931 #ifdef CONFIG_IWLEGACY_DEBUGFS
933 #endif
935 /****************************/
936 /* Flow Handler Definitions */
937 /****************************/
939 /**
940 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
941 * Addresses are offsets from device's PCI hardware base address.
942 */
943 #define FH49_MEM_LOWER_BOUND (0x1000)
944 #define FH49_MEM_UPPER_BOUND (0x2000)
946 /**
947 * Keep-Warm (KW) buffer base address.
948 *
949 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
950 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
951 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
952 * from going into a power-savings mode that would cause higher DRAM latency,
953 * and possible data over/under-runs, before all Tx/Rx is complete.
954 *
955 * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
956 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
957 * automatically invokes keep-warm accesses when normal accesses might not
958 * be sufficient to maintain fast DRAM response.
959 *
960 * Bit fields:
961 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
962 */
963 #define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
965 /**
966 * TFD Circular Buffers Base (CBBC) addresses
967 *
968 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
969 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
970 * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04
971 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
972 * aligned (address bits 0-7 must be 0).
973 *
974 * Bit fields in each pointer register:
975 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
976 */
977 #define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
978 #define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
980 /* Find TFD CB base pointer for given queue (range 0-15). */
981 #define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
983 /**
984 * Rx SRAM Control and Status Registers (RSCSR)
985 *
986 * These registers provide handshake between driver and 4965 for the Rx queue
987 * (this queue handles *all* command responses, notifications, Rx data, etc.
988 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
989 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
990 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
991 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
992 * mapping between RBDs and RBs.
993 *
994 * Driver must allocate host DRAM memory for the following, and set the
995 * physical address of each into 4965 registers:
996 *
997 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
998 * entries (although any power of 2, up to 4096, is selectable by driver).
999 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1000 * (typically 4K, although 8K or 16K are also selectable by driver).
1001 * Driver sets up RB size and number of RBDs in the CB via Rx config
1002 * register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
1003 *
1004 * Bit fields within one RBD:
1005 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1006 *
1007 * Driver sets physical address [35:8] of base of RBD circular buffer
1008 * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1009 *
1010 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
1011 * (RBs) have been filled, via a "write pointer", actually the idx of
1012 * the RB's corresponding RBD within the circular buffer. Driver sets
1013 * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1014 *
1015 * Bit fields in lower dword of Rx status buffer (upper dword not used
1016 * by driver; see struct il4965_shared, val0):
1017 * 31-12: Not used by driver
1018 * 11- 0: Index of last filled Rx buffer descriptor
1019 * (4965 writes, driver reads this value)
1020 *
1021 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
1022 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1023 * and update the 4965's "write" idx register,
1024 * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
1025 *
1026 * This "write" idx corresponds to the *next* RBD that the driver will make
1027 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1028 * the circular buffer. This value should initially be 0 (before preparing any
1029 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1030 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1031 * "read" idx has advanced past 1! See below).
1032 * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8.
1033 *
1034 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
1035 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1036 * to tell the driver the idx of the latest filled RBD. The driver must
1037 * read this "read" idx from DRAM after receiving an Rx interrupt from 4965.
1038 *
1039 * The driver must also internally keep track of a third idx, which is the
1040 * next RBD to process. When receiving an Rx interrupt, driver should process
1041 * all filled but unprocessed RBs up to, but not including, the RB
1042 * corresponding to the "read" idx. For example, if "read" idx becomes "1",
1043 * driver may process the RB pointed to by RBD 0. Depending on volume of
1044 * traffic, there may be many RBs to process.
1045 *
1046 * If read idx == write idx, 4965 thinks there is no room to put new data.
1047 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1048 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1049 * and "read" idxes; that is, make sure that there are no more than 254
1050 * buffers waiting to be filled.
1051 */
1052 #define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
1053 #define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1054 #define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
1056 /**
1057 * Physical base address of 8-byte Rx Status buffer.
1058 * Bit fields:
1059 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1060 */
1061 #define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
1063 /**
1064 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1065 * Bit fields:
1066 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1067 */
1068 #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
1070 /**
1071 * Rx write pointer (idx, really!).
1072 * Bit fields:
1073 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1074 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1075 */
1076 #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
1077 #define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
1079 /**
1080 * Rx Config/Status Registers (RCSR)
1081 * Rx Config Reg for channel 0 (only channel used)
1082 *
1083 * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1084 * normal operation (see bit fields).
1085 *
1086 * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1087 * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for
1088 * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1089 *
1090 * Bit fields:
1091 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1092 * '10' operate normally
1093 * 29-24: reserved
1094 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1095 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1096 * 19-18: reserved
1097 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1098 * '10' 12K, '11' 16K.
1099 * 15-14: reserved
1100 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1101 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1102 * typical value 0x10 (about 1/2 msec)
1103 * 3- 0: reserved
1104 */
1105 #define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1106 #define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
1107 #define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
1109 #define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
1118 #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1119 #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1120 #define RX_RB_TIMEOUT (0x10)
1122 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1123 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1124 #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1126 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1127 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1128 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1129 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1131 #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1132 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1133 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1135 /**
1136 * Rx Shared Status Registers (RSSR)
1137 *
1138 * After stopping Rx DMA channel (writing 0 to
1139 * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1140 * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1141 *
1142 * Bit fields:
1143 * 24: 1 = Channel 0 is idle
1144 *
1145 * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1146 * contain default values that should not be altered by the driver.
1147 */
1148 #define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
1149 #define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1151 #define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
1152 #define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
1153 #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1154 (FH49_MEM_RSSR_LOWER_BOUND + 0x008)
1156 #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1158 #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1160 /* TFDB Area - TFDs buffer table */
1161 #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1162 #define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
1163 #define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
1164 #define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1165 #define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1167 /**
1168 * Transmit DMA Channel Control/Status Registers (TCSR)
1169 *
1170 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1171 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1172 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1173 *
1174 * To use a Tx DMA channel, driver must initialize its
1175 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1176 *
1177 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1178 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1179 *
1180 * All other bits should be 0.
1181 *
1182 * Bit fields:
1183 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1184 * '10' operate normally
1185 * 29- 4: Reserved, set to "0"
1186 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1187 * 2- 0: Reserved, set to "0"
1188 */
1189 #define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1190 #define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
1192 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1193 #define FH49_TCSR_CHNL_NUM (7)
1194 #define FH50_TCSR_CHNL_NUM (8)
1196 /* TCSR: tx_config register values */
1197 #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1198 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1199 #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1200 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1201 #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1202 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1204 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1205 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1207 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1208 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1210 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1211 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1212 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1214 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1215 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1216 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1218 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1219 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1220 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1222 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1223 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1224 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1226 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1227 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1229 /**
1230 * Tx Shared Status Registers (TSSR)
1231 *
1232 * After stopping Tx DMA channel (writing 0 to
1233 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1234 * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
1235 * (channel's buffers empty | no pending requests).
1236 *
1237 * Bit fields:
1238 * 31-24: 1 = Channel buffers empty (channel 7:0)
1239 * 23-16: 1 = No pending requests (channel 7:0)
1240 */
1241 #define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
1242 #define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
1244 #define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
1246 /**
1247 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1248 * 31: Indicates an address error when accessed to internal memory
1249 * uCode/driver must write "1" in order to clear this flag
1250 * 30: Indicates that Host did not send the expected number of dwords to FH
1251 * uCode/driver must write "1" in order to clear this flag
1252 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1253 * command was received from the scheduler while the TRB was already full
1254 * with previous command
1255 * uCode/driver must write "1" in order to clear this flag
1256 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1257 * bit is set, it indicates that the FH has received a full indication
1258 * from the RTC TxFIFO and the current value of the TxCredit counter was
1259 * not equal to zero. This mean that the credit mechanism was not
1260 * synchronized to the TxFIFO status
1261 * uCode/driver must write "1" in order to clear this flag
1262 */
1263 #define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
1265 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1267 /* Tx service channels */
1268 #define FH49_SRVC_CHNL (9)
1269 #define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
1270 #define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1271 #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1272 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1274 #define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
1275 /* Instruct FH to increment the retry count of a packet when
1276 * it is brought from the memory to TX-FIFO
1277 */
1278 #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1280 /* Keep Warm Size */