arch/s390/pci/pci_insn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * s390 specific pci instructions
   4  *
   5  * Copyright IBM Corp. 2013
   6  */
   7
   8 #include <linux/export.h>
   9 #include <linux/errno.h>
  10 #include <linux/delay.h>
  11 #include <asm/facility.h>
  12 #include <asm/pci_insn.h>
  13 #include <asm/pci_debug.h>
  14 #include <asm/processor.h>
  15
  16 #define ZPCI_INSN_BUSY_DELAY    1       /* 1 microsecond */
  17
  18 static inline void zpci_err_insn(u8 cc, u8 status, u64 req, u64 offset)
  19 {
  20         struct {
  21                 u64 req;
  22                 u64 offset;
  23                 u8 cc;
  24                 u8 status;
  25         } __packed data = {req, offset, cc, status};
  26
  27         zpci_err_hex(&data, sizeof(data));
  28 }
  29
  30 /* Modify PCI Function Controls */
  31 static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
  32 {
  33         u8 cc;
  34
  35         asm volatile (
  36                 "       .insn   rxy,0xe300000000d0,%[req],%[fib]\n"
  37                 "       ipm     %[cc]\n"
  38                 "       srl     %[cc],28\n"
  39                 : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
  40                 : : "cc");
  41         *status = req >> 24 & 0xff;
  42         return cc;
  43 }
  44
  45 u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
  46 {
  47         u8 cc;
  48
  49         do {
  50                 cc = __mpcifc(req, fib, status);
  51                 if (cc == 2)
  52                         msleep(ZPCI_INSN_BUSY_DELAY);
  53         } while (cc == 2);
  54
  55         if (cc)
  56                 zpci_err_insn(cc, *status, req, 0);
  57
  58         return cc;
  59 }
  60
  61 /* Refresh PCI Translations */
  62 static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
  63 {
  64         register u64 __addr asm("2") = addr;
  65         register u64 __range asm("3") = range;
  66         u8 cc;
  67
  68         asm volatile (
  69                 "       .insn   rre,0xb9d30000,%[fn],%[addr]\n"
  70                 "       ipm     %[cc]\n"
  71                 "       srl     %[cc],28\n"
  72                 : [cc] "=d" (cc), [fn] "+d" (fn)
  73                 : [addr] "d" (__addr), "d" (__range)
  74                 : "cc");
  75         *status = fn >> 24 & 0xff;
  76         return cc;
  77 }
  78
  79 int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
  80 {
  81         u8 cc, status;
  82
  83         do {
  84                 cc = __rpcit(fn, addr, range, &status);
  85                 if (cc == 2)
  86                         udelay(ZPCI_INSN_BUSY_DELAY);
  87         } while (cc == 2);
  88
  89         if (cc)
  90                 zpci_err_insn(cc, status, addr, range);
  91
  92         if (cc == 1 && (status == 4 || status == 16))
  93                 return -ENOMEM;
  94
  95         return (cc) ? -EIO : 0;
  96 }
  97
  98 /* Set Interruption Controls */
  99 int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc)
 100 {
 101         if (!test_facility(72))
 102                 return -EIO;
 103         asm volatile (
 104                 "       .insn   rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
 105                 : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
 106         return 0;
 107 }
 108
 109 /* PCI Load */
 110 static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
 111 {
 112         register u64 __req asm("2") = req;
 113         register u64 __offset asm("3") = offset;
 114         int cc = -ENXIO;
 115         u64 __data;
 116
 117         asm volatile (
 118                 "       .insn   rre,0xb9d20000,%[data],%[req]\n"
 119                 "0:     ipm     %[cc]\n"
 120                 "       srl     %[cc],28\n"
 121                 "1:\n"
 122                 EX_TABLE(0b, 1b)
 123                 : [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
 124                 :  "d" (__offset)
 125                 : "cc");
 126         *status = __req >> 24 & 0xff;
 127         *data = __data;
 128         return cc;
 129 }
 130
 131 static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
 132 {
 133         u64 __data;
 134         int cc;
 135
 136         cc = ____pcilg(&__data, req, offset, status);
 137         if (!cc)
 138                 *data = __data;
 139
 140         return cc;
 141 }
 142
 143 int zpci_load(u64 *data, u64 req, u64 offset)
 144 {
 145         u8 status;
 146         int cc;
 147
 148         do {
 149                 cc = __pcilg(data, req, offset, &status);
 150                 if (cc == 2)
 151                         udelay(ZPCI_INSN_BUSY_DELAY);
 152         } while (cc == 2);
 153
 154         if (cc)
 155                 zpci_err_insn(cc, status, req, offset);
 156
 157         return (cc > 0) ? -EIO : cc;
 158 }
 159 EXPORT_SYMBOL_GPL(zpci_load);
 160
 161 /* PCI Store */
 162 static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
 163 {
 164         register u64 __req asm("2") = req;
 165         register u64 __offset asm("3") = offset;
 166         int cc = -ENXIO;
 167
 168         asm volatile (
 169                 "       .insn   rre,0xb9d00000,%[data],%[req]\n"
 170                 "0:     ipm     %[cc]\n"
 171                 "       srl     %[cc],28\n"
 172                 "1:\n"
 173                 EX_TABLE(0b, 1b)
 174                 : [cc] "+d" (cc), [req] "+d" (__req)
 175                 : "d" (__offset), [data] "d" (data)
 176                 : "cc");
 177         *status = __req >> 24 & 0xff;
 178         return cc;
 179 }
 180
 181 int zpci_store(u64 data, u64 req, u64 offset)
 182 {
 183         u8 status;
 184         int cc;
 185
 186         do {
 187                 cc = __pcistg(data, req, offset, &status);
 188                 if (cc == 2)
 189                         udelay(ZPCI_INSN_BUSY_DELAY);
 190         } while (cc == 2);
 191
 192         if (cc)
 193                 zpci_err_insn(cc, status, req, offset);
 194
 195         return (cc > 0) ? -EIO : cc;
 196 }
 197 EXPORT_SYMBOL_GPL(zpci_store);
 198
 199 /* PCI Store Block */
 200 static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
 201 {
 202         int cc = -ENXIO;
 203
 204         asm volatile (
 205                 "       .insn   rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
 206                 "0:     ipm     %[cc]\n"
 207                 "       srl     %[cc],28\n"
 208                 "1:\n"
 209                 EX_TABLE(0b, 1b)
 210                 : [cc] "+d" (cc), [req] "+d" (req)
 211                 : [offset] "d" (offset), [data] "Q" (*data)
 212                 : "cc");
 213         *status = req >> 24 & 0xff;
 214         return cc;
 215 }
 216
 217 int zpci_store_block(const u64 *data, u64 req, u64 offset)
 218 {
 219         u8 status;
 220         int cc;
 221
 222         do {
 223                 cc = __pcistb(data, req, offset, &status);
 224                 if (cc == 2)
 225                         udelay(ZPCI_INSN_BUSY_DELAY);
 226         } while (cc == 2);
 227
 228         if (cc)
 229                 zpci_err_insn(cc, status, req, offset);
 230
 231         return (cc > 0) ? -EIO : cc;
 232 }
 233 EXPORT_SYMBOL_GPL(zpci_store_block);