arch/sh/include/cpu-sh4/cpu/dma-register.h

   1 /*
   2  * SH4 CPU-specific DMA definitions, used by both DMA drivers
   3  *
   4  * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef CPU_DMA_REGISTER_H
  11 #define CPU_DMA_REGISTER_H
  12
  13 /* SH7751/7760/7780 DMA IRQ sources */
  14
  15 #ifdef CONFIG_CPU_SH4A
  16
  17 #define DMAOR_INIT      DMAOR_DME
  18
  19 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
  20 #define CHCR_TS_LOW_MASK        0x00000018
  21 #define CHCR_TS_LOW_SHIFT       3
  22 #define CHCR_TS_HIGH_MASK       0
  23 #define CHCR_TS_HIGH_SHIFT      0
  24 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
  25         defined(CONFIG_CPU_SUBTYPE_SH7723) || \
  26         defined(CONFIG_CPU_SUBTYPE_SH7724) || \
  27         defined(CONFIG_CPU_SUBTYPE_SH7730) || \
  28         defined(CONFIG_CPU_SUBTYPE_SH7786)
  29 #define CHCR_TS_LOW_MASK        0x00000018
  30 #define CHCR_TS_LOW_SHIFT       3
  31 #define CHCR_TS_HIGH_MASK       0x00300000
  32 #define CHCR_TS_HIGH_SHIFT      (20 - 2)        /* 2 bits for shifted low TS */
  33 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
  34         defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  35         defined(CONFIG_CPU_SUBTYPE_SH7780) || \
  36         defined(CONFIG_CPU_SUBTYPE_SH7785)
  37 #define CHCR_TS_LOW_MASK        0x00000018
  38 #define CHCR_TS_LOW_SHIFT       3
  39 #define CHCR_TS_HIGH_MASK       0x00100000
  40 #define CHCR_TS_HIGH_SHIFT      (20 - 2)        /* 2 bits for shifted low TS */
  41 #endif
  42
  43 /* Transmit sizes and respective CHCR register values */
  44 enum {
  45         XMIT_SZ_8BIT            = 0,
  46         XMIT_SZ_16BIT           = 1,
  47         XMIT_SZ_32BIT           = 2,
  48         XMIT_SZ_64BIT           = 7,
  49         XMIT_SZ_128BIT          = 3,
  50         XMIT_SZ_256BIT          = 4,
  51         XMIT_SZ_128BIT_BLK      = 0xb,
  52         XMIT_SZ_256BIT_BLK      = 0xc,
  53 };
  54
  55 /* log2(size / 8) - used to calculate number of transfers */
  56 #define TS_SHIFT {                      \
  57         [XMIT_SZ_8BIT]          = 0,    \
  58         [XMIT_SZ_16BIT]         = 1,    \
  59         [XMIT_SZ_32BIT]         = 2,    \
  60         [XMIT_SZ_64BIT]         = 3,    \
  61         [XMIT_SZ_128BIT]        = 4,    \
  62         [XMIT_SZ_256BIT]        = 5,    \
  63         [XMIT_SZ_128BIT_BLK]    = 4,    \
  64         [XMIT_SZ_256BIT_BLK]    = 5,    \
  65 }
  66
  67 #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
  68                          (((i) & 0xc) << CHCR_TS_HIGH_SHIFT))
  69
  70 #else /* CONFIG_CPU_SH4A */
  71
  72 #define DMAOR_INIT      (0x8000 | DMAOR_DME)
  73
  74 #define CHCR_TS_LOW_MASK        0x70
  75 #define CHCR_TS_LOW_SHIFT       4
  76 #define CHCR_TS_HIGH_MASK       0
  77 #define CHCR_TS_HIGH_SHIFT      0
  78
  79 /* Transmit sizes and respective CHCR register values */
  80 enum {
  81         XMIT_SZ_8BIT    = 1,
  82         XMIT_SZ_16BIT   = 2,
  83         XMIT_SZ_32BIT   = 3,
  84         XMIT_SZ_64BIT   = 0,
  85         XMIT_SZ_256BIT  = 4,
  86 };
  87
  88 /* log2(size / 8) - used to calculate number of transfers */
  89 #define TS_SHIFT {                      \
  90         [XMIT_SZ_8BIT]          = 0,    \
  91         [XMIT_SZ_16BIT]         = 1,    \
  92         [XMIT_SZ_32BIT]         = 2,    \
  93         [XMIT_SZ_64BIT]         = 3,    \
  94         [XMIT_SZ_256BIT]        = 5,    \
  95 }
  96
  97 #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
  98
  99 #endif /* CONFIG_CPU_SH4A */
 100
 101 #endif