arch/x86/boot/cpucheck.c

   1 /* -*- linux-c -*- ------------------------------------------------------- *
   2  *
   3  *   Copyright (C) 1991, 1992 Linus Torvalds
   4  *   Copyright 2007 rPath, Inc. - All Rights Reserved
   5  *
   6  *   This file is part of the Linux kernel, and is made available under
   7  *   the terms of the GNU General Public License version 2.
   8  *
   9  * ----------------------------------------------------------------------- */
  10
  11 /*
  12  * Check for obligatory CPU features and abort if the features are not
  13  * present.  This code should be compilable as 16-, 32- or 64-bit
  14  * code, so be very careful with types and inline assembly.
  15  *
  16  * This code should not contain any messages; that requires an
  17  * additional wrapper.
  18  *
  19  * As written, this code is not safe for inclusion into the kernel
  20  * proper (after FPU initialization, in particular).
  21  */
  22
  23 #ifdef _SETUP
  24 # include "boot.h"
  25 #endif
  26 #include <linux/types.h>
  27 #include <asm/intel-family.h>
  28 #include <asm/processor-flags.h>
  29 #include <asm/required-features.h>
  30 #include <asm/msr-index.h>
  31 #include "string.h"
  32
  33 static u32 err_flags[NCAPINTS];
  34
  35 static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
  36
  37 static const u32 req_flags[NCAPINTS] =
  38 {
  39         REQUIRED_MASK0,
  40         REQUIRED_MASK1,
  41         0, /* REQUIRED_MASK2 not implemented in this file */
  42         0, /* REQUIRED_MASK3 not implemented in this file */
  43         REQUIRED_MASK4,
  44         0, /* REQUIRED_MASK5 not implemented in this file */
  45         REQUIRED_MASK6,
  46         0, /* REQUIRED_MASK7 not implemented in this file */
  47         0, /* REQUIRED_MASK8 not implemented in this file */
  48         0, /* REQUIRED_MASK9 not implemented in this file */
  49         0, /* REQUIRED_MASK10 not implemented in this file */
  50         0, /* REQUIRED_MASK11 not implemented in this file */
  51         0, /* REQUIRED_MASK12 not implemented in this file */
  52         0, /* REQUIRED_MASK13 not implemented in this file */
  53         0, /* REQUIRED_MASK14 not implemented in this file */
  54         0, /* REQUIRED_MASK15 not implemented in this file */
  55         REQUIRED_MASK16,
  56 };
  57
  58 #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
  59
  60 static int is_amd(void)
  61 {
  62         return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
  63                cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
  64                cpu_vendor[2] == A32('c', 'A', 'M', 'D');
  65 }
  66
  67 static int is_centaur(void)
  68 {
  69         return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
  70                cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
  71                cpu_vendor[2] == A32('a', 'u', 'l', 's');
  72 }
  73
  74 static int is_transmeta(void)
  75 {
  76         return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
  77                cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
  78                cpu_vendor[2] == A32('M', 'x', '8', '6');
  79 }
  80
  81 static int is_intel(void)
  82 {
  83         return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
  84                cpu_vendor[1] == A32('i', 'n', 'e', 'I') &&
  85                cpu_vendor[2] == A32('n', 't', 'e', 'l');
  86 }
  87
  88 /* Returns a bitmask of which words we have error bits in */
  89 static int check_cpuflags(void)
  90 {
  91         u32 err;
  92         int i;
  93
  94         err = 0;
  95         for (i = 0; i < NCAPINTS; i++) {
  96                 err_flags[i] = req_flags[i] & ~cpu.flags[i];
  97                 if (err_flags[i])
  98                         err |= 1 << i;
  99         }
 100
 101         return err;
 102 }
 103
 104 /*
 105  * Returns -1 on error.
 106  *
 107  * *cpu_level is set to the current CPU level; *req_level to the required
 108  * level.  x86-64 is considered level 64 for this purpose.
 109  *
 110  * *err_flags_ptr is set to the flags error array if there are flags missing.
 111  */
 112 int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
 113 {
 114         int err;
 115
 116         memset(&cpu.flags, 0, sizeof cpu.flags);
 117         cpu.level = 3;
 118
 119         if (has_eflag(X86_EFLAGS_AC))
 120                 cpu.level = 4;
 121
 122         get_cpuflags();
 123         err = check_cpuflags();
 124
 125         if (test_bit(X86_FEATURE_LM, cpu.flags))
 126                 cpu.level = 64;
 127
 128         if (err == 0x01 &&
 129             !(err_flags[0] &
 130               ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
 131             is_amd()) {
 132                 /* If this is an AMD and we're only missing SSE+SSE2, try to
 133                    turn them on */
 134
 135                 u32 ecx = MSR_K7_HWCR;
 136                 u32 eax, edx;
 137
 138                 asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
 139                 eax &= ~(1 << 15);
 140                 asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
 141
 142                 get_cpuflags(); /* Make sure it really did something */
 143                 err = check_cpuflags();
 144         } else if (err == 0x01 &&
 145                    !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
 146                    is_centaur() && cpu.model >= 6) {
 147                 /* If this is a VIA C3, we might have to enable CX8
 148                    explicitly */
 149
 150                 u32 ecx = MSR_VIA_FCR;
 151                 u32 eax, edx;
 152
 153                 asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
 154                 eax |= (1<<1)|(1<<7);
 155                 asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
 156
 157                 set_bit(X86_FEATURE_CX8, cpu.flags);
 158                 err = check_cpuflags();
 159         } else if (err == 0x01 && is_transmeta()) {
 160                 /* Transmeta might have masked feature bits in word 0 */
 161
 162                 u32 ecx = 0x80860004;
 163                 u32 eax, edx;
 164                 u32 level = 1;
 165
 166                 asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
 167                 asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
 168                 asm("cpuid"
 169                     : "+a" (level), "=d" (cpu.flags[0])
 170                     : : "ecx", "ebx");
 171                 asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
 172
 173                 err = check_cpuflags();
 174         } else if (err == 0x01 &&
 175                    !(err_flags[0] & ~(1 << X86_FEATURE_PAE)) &&
 176                    is_intel() && cpu.level == 6 &&
 177                    (cpu.model == 9 || cpu.model == 13)) {
 178                 /* PAE is disabled on this Pentium M but can be forced */
 179                 if (cmdline_find_option_bool("forcepae")) {
 180                         puts("WARNING: Forcing PAE in CPU flags\n");
 181                         set_bit(X86_FEATURE_PAE, cpu.flags);
 182                         err = check_cpuflags();
 183                 }
 184                 else {
 185                         puts("WARNING: PAE disabled. Use parameter 'forcepae' to enable at your own risk!\n");
 186                 }
 187         }
 188         if (!err)
 189                 err = check_knl_erratum();
 190
 191         if (err_flags_ptr)
 192                 *err_flags_ptr = err ? err_flags : NULL;
 193         if (cpu_level_ptr)
 194                 *cpu_level_ptr = cpu.level;
 195         if (req_level_ptr)
 196                 *req_level_ptr = req_level;
 197
 198         return (cpu.level < req_level || err) ? -1 : 0;
 199 }
 200
 201 int check_knl_erratum(void)
 202 {
 203         /*
 204          * First check for the affected model/family:
 205          */
 206         if (!is_intel() ||
 207             cpu.family != 6 ||
 208             cpu.model != INTEL_FAM6_XEON_PHI_KNL)
 209                 return 0;
 210
 211         /*
 212          * This erratum affects the Accessed/Dirty bits, and can
 213          * cause stray bits to be set in !Present PTEs.  We have
 214          * enough bits in our 64-bit PTEs (which we have on real
 215          * 64-bit mode or PAE) to avoid using these troublesome
 216          * bits.  But, we do not have enough space in our 32-bit
 217          * PTEs.  So, refuse to run on 32-bit non-PAE kernels.
 218          */
 219         if (IS_ENABLED(CONFIG_X86_64) || IS_ENABLED(CONFIG_X86_PAE))
 220                 return 0;
 221
 222         puts("This 32-bit kernel can not run on this Xeon Phi x200\n"
 223              "processor due to a processor erratum.  Use a 64-bit\n"
 224              "kernel, or enable PAE in this 32-bit kernel.\n\n");
 225
 226         return -1;
 227 }
 228
 229