arch/x86/events/intel/uncore_snb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */
   3 #include "uncore.h"
   4
   5 /* Uncore IMC PCI IDs */
   6 #define PCI_DEVICE_ID_INTEL_SNB_IMC     0x0100
   7 #define PCI_DEVICE_ID_INTEL_IVB_IMC     0x0154
   8 #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC  0x0150
   9 #define PCI_DEVICE_ID_INTEL_HSW_IMC     0x0c00
  10 #define PCI_DEVICE_ID_INTEL_HSW_U_IMC   0x0a04
  11 #define PCI_DEVICE_ID_INTEL_BDW_IMC     0x1604
  12 #define PCI_DEVICE_ID_INTEL_SKL_U_IMC   0x1904
  13 #define PCI_DEVICE_ID_INTEL_SKL_Y_IMC   0x190c
  14 #define PCI_DEVICE_ID_INTEL_SKL_HD_IMC  0x1900
  15 #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC  0x1910
  16 #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC  0x190f
  17 #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC  0x191f
  18 #define PCI_DEVICE_ID_INTEL_KBL_Y_IMC   0x590c
  19 #define PCI_DEVICE_ID_INTEL_KBL_U_IMC   0x5904
  20 #define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC  0x5914
  21 #define PCI_DEVICE_ID_INTEL_KBL_SD_IMC  0x590f
  22 #define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC  0x591f
  23 #define PCI_DEVICE_ID_INTEL_CFL_2U_IMC  0x3ecc
  24 #define PCI_DEVICE_ID_INTEL_CFL_4U_IMC  0x3ed0
  25 #define PCI_DEVICE_ID_INTEL_CFL_4H_IMC  0x3e10
  26 #define PCI_DEVICE_ID_INTEL_CFL_6H_IMC  0x3ec4
  27 #define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC        0x3e0f
  28 #define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC        0x3e1f
  29 #define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC        0x3ec2
  30 #define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC        0x3e30
  31 #define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC        0x3e18
  32 #define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC        0x3ec6
  33 #define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC        0x3e31
  34 #define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC        0x3e33
  35 #define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC        0x3eca
  36 #define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC        0x3e32
  37
  38 /* SNB event control */
  39 #define SNB_UNC_CTL_EV_SEL_MASK                 0x000000ff
  40 #define SNB_UNC_CTL_UMASK_MASK                  0x0000ff00
  41 #define SNB_UNC_CTL_EDGE_DET                    (1 << 18)
  42 #define SNB_UNC_CTL_EN                          (1 << 22)
  43 #define SNB_UNC_CTL_INVERT                      (1 << 23)
  44 #define SNB_UNC_CTL_CMASK_MASK                  0x1f000000
  45 #define NHM_UNC_CTL_CMASK_MASK                  0xff000000
  46 #define NHM_UNC_FIXED_CTR_CTL_EN                (1 << 0)
  47
  48 #define SNB_UNC_RAW_EVENT_MASK                  (SNB_UNC_CTL_EV_SEL_MASK | \
  49                                                  SNB_UNC_CTL_UMASK_MASK | \
  50                                                  SNB_UNC_CTL_EDGE_DET | \
  51                                                  SNB_UNC_CTL_INVERT | \
  52                                                  SNB_UNC_CTL_CMASK_MASK)
  53
  54 #define NHM_UNC_RAW_EVENT_MASK                  (SNB_UNC_CTL_EV_SEL_MASK | \
  55                                                  SNB_UNC_CTL_UMASK_MASK | \
  56                                                  SNB_UNC_CTL_EDGE_DET | \
  57                                                  SNB_UNC_CTL_INVERT | \
  58                                                  NHM_UNC_CTL_CMASK_MASK)
  59
  60 /* SNB global control register */
  61 #define SNB_UNC_PERF_GLOBAL_CTL                 0x391
  62 #define SNB_UNC_FIXED_CTR_CTRL                  0x394
  63 #define SNB_UNC_FIXED_CTR                       0x395
  64
  65 /* SNB uncore global control */
  66 #define SNB_UNC_GLOBAL_CTL_CORE_ALL             ((1 << 4) - 1)
  67 #define SNB_UNC_GLOBAL_CTL_EN                   (1 << 29)
  68
  69 /* SNB Cbo register */
  70 #define SNB_UNC_CBO_0_PERFEVTSEL0               0x700
  71 #define SNB_UNC_CBO_0_PER_CTR0                  0x706
  72 #define SNB_UNC_CBO_MSR_OFFSET                  0x10
  73
  74 /* SNB ARB register */
  75 #define SNB_UNC_ARB_PER_CTR0                    0x3b0
  76 #define SNB_UNC_ARB_PERFEVTSEL0                 0x3b2
  77 #define SNB_UNC_ARB_MSR_OFFSET                  0x10
  78
  79 /* NHM global control register */
  80 #define NHM_UNC_PERF_GLOBAL_CTL                 0x391
  81 #define NHM_UNC_FIXED_CTR                       0x394
  82 #define NHM_UNC_FIXED_CTR_CTRL                  0x395
  83
  84 /* NHM uncore global control */
  85 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL            ((1ULL << 8) - 1)
  86 #define NHM_UNC_GLOBAL_CTL_EN_FC                (1ULL << 32)
  87
  88 /* NHM uncore register */
  89 #define NHM_UNC_PERFEVTSEL0                     0x3c0
  90 #define NHM_UNC_UNCORE_PMC0                     0x3b0
  91
  92 /* SKL uncore global control */
  93 #define SKL_UNC_PERF_GLOBAL_CTL                 0xe01
  94 #define SKL_UNC_GLOBAL_CTL_CORE_ALL             ((1 << 5) - 1)
  95
  96 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
  97 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
  98 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
  99 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
 100 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
 101 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
 102
 103 /* Sandy Bridge uncore support */
 104 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 105 {
 106         struct hw_perf_event *hwc = &event->hw;
 107
 108         if (hwc->idx < UNCORE_PMC_IDX_FIXED)
 109                 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
 110         else
 111                 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
 112 }
 113
 114 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
 115 {
 116         wrmsrl(event->hw.config_base, 0);
 117 }
 118
 119 static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
 120 {
 121         if (box->pmu->pmu_idx == 0) {
 122                 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
 123                         SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
 124         }
 125 }
 126
 127 static void snb_uncore_msr_enable_box(struct intel_uncore_box *box)
 128 {
 129         wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
 130                 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
 131 }
 132
 133 static void snb_uncore_msr_exit_box(struct intel_uncore_box *box)
 134 {
 135         if (box->pmu->pmu_idx == 0)
 136                 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0);
 137 }
 138
 139 static struct uncore_event_desc snb_uncore_events[] = {
 140         INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
 141         { /* end: all zeroes */ },
 142 };
 143
 144 static struct attribute *snb_uncore_formats_attr[] = {
 145         &format_attr_event.attr,
 146         &format_attr_umask.attr,
 147         &format_attr_edge.attr,
 148         &format_attr_inv.attr,
 149         &format_attr_cmask5.attr,
 150         NULL,
 151 };
 152
 153 static const struct attribute_group snb_uncore_format_group = {
 154         .name           = "format",
 155         .attrs          = snb_uncore_formats_attr,
 156 };
 157
 158 static struct intel_uncore_ops snb_uncore_msr_ops = {
 159         .init_box       = snb_uncore_msr_init_box,
 160         .enable_box     = snb_uncore_msr_enable_box,
 161         .exit_box       = snb_uncore_msr_exit_box,
 162         .disable_event  = snb_uncore_msr_disable_event,
 163         .enable_event   = snb_uncore_msr_enable_event,
 164         .read_counter   = uncore_msr_read_counter,
 165 };
 166
 167 static struct event_constraint snb_uncore_arb_constraints[] = {
 168         UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
 169         UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
 170         EVENT_CONSTRAINT_END
 171 };
 172
 173 static struct intel_uncore_type snb_uncore_cbox = {
 174         .name           = "cbox",
 175         .num_counters   = 2,
 176         .num_boxes      = 4,
 177         .perf_ctr_bits  = 44,
 178         .fixed_ctr_bits = 48,
 179         .perf_ctr       = SNB_UNC_CBO_0_PER_CTR0,
 180         .event_ctl      = SNB_UNC_CBO_0_PERFEVTSEL0,
 181         .fixed_ctr      = SNB_UNC_FIXED_CTR,
 182         .fixed_ctl      = SNB_UNC_FIXED_CTR_CTRL,
 183         .single_fixed   = 1,
 184         .event_mask     = SNB_UNC_RAW_EVENT_MASK,
 185         .msr_offset     = SNB_UNC_CBO_MSR_OFFSET,
 186         .ops            = &snb_uncore_msr_ops,
 187         .format_group   = &snb_uncore_format_group,
 188         .event_descs    = snb_uncore_events,
 189 };
 190
 191 static struct intel_uncore_type snb_uncore_arb = {
 192         .name           = "arb",
 193         .num_counters   = 2,
 194         .num_boxes      = 1,
 195         .perf_ctr_bits  = 44,
 196         .perf_ctr       = SNB_UNC_ARB_PER_CTR0,
 197         .event_ctl      = SNB_UNC_ARB_PERFEVTSEL0,
 198         .event_mask     = SNB_UNC_RAW_EVENT_MASK,
 199         .msr_offset     = SNB_UNC_ARB_MSR_OFFSET,
 200         .constraints    = snb_uncore_arb_constraints,
 201         .ops            = &snb_uncore_msr_ops,
 202         .format_group   = &snb_uncore_format_group,
 203 };
 204
 205 static struct intel_uncore_type *snb_msr_uncores[] = {
 206         &snb_uncore_cbox,
 207         &snb_uncore_arb,
 208         NULL,
 209 };
 210
 211 void snb_uncore_cpu_init(void)
 212 {
 213         uncore_msr_uncores = snb_msr_uncores;
 214         if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
 215                 snb_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
 216 }
 217
 218 static void skl_uncore_msr_init_box(struct intel_uncore_box *box)
 219 {
 220         if (box->pmu->pmu_idx == 0) {
 221                 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
 222                         SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
 223         }
 224 }
 225
 226 static void skl_uncore_msr_enable_box(struct intel_uncore_box *box)
 227 {
 228         wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
 229                 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
 230 }
 231
 232 static void skl_uncore_msr_exit_box(struct intel_uncore_box *box)
 233 {
 234         if (box->pmu->pmu_idx == 0)
 235                 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0);
 236 }
 237
 238 static struct intel_uncore_ops skl_uncore_msr_ops = {
 239         .init_box       = skl_uncore_msr_init_box,
 240         .enable_box     = skl_uncore_msr_enable_box,
 241         .exit_box       = skl_uncore_msr_exit_box,
 242         .disable_event  = snb_uncore_msr_disable_event,
 243         .enable_event   = snb_uncore_msr_enable_event,
 244         .read_counter   = uncore_msr_read_counter,
 245 };
 246
 247 static struct intel_uncore_type skl_uncore_cbox = {
 248         .name           = "cbox",
 249         .num_counters   = 4,
 250         .num_boxes      = 5,
 251         .perf_ctr_bits  = 44,
 252         .fixed_ctr_bits = 48,
 253         .perf_ctr       = SNB_UNC_CBO_0_PER_CTR0,
 254         .event_ctl      = SNB_UNC_CBO_0_PERFEVTSEL0,
 255         .fixed_ctr      = SNB_UNC_FIXED_CTR,
 256         .fixed_ctl      = SNB_UNC_FIXED_CTR_CTRL,
 257         .single_fixed   = 1,
 258         .event_mask     = SNB_UNC_RAW_EVENT_MASK,
 259         .msr_offset     = SNB_UNC_CBO_MSR_OFFSET,
 260         .ops            = &skl_uncore_msr_ops,
 261         .format_group   = &snb_uncore_format_group,
 262         .event_descs    = snb_uncore_events,
 263 };
 264
 265 static struct intel_uncore_type *skl_msr_uncores[] = {
 266         &skl_uncore_cbox,
 267         &snb_uncore_arb,
 268         NULL,
 269 };
 270
 271 void skl_uncore_cpu_init(void)
 272 {
 273         uncore_msr_uncores = skl_msr_uncores;
 274         if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
 275                 skl_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
 276         snb_uncore_arb.ops = &skl_uncore_msr_ops;
 277 }
 278
 279 enum {
 280         SNB_PCI_UNCORE_IMC,
 281 };
 282
 283 static struct uncore_event_desc snb_uncore_imc_events[] = {
 284         INTEL_UNCORE_EVENT_DESC(data_reads,  "event=0x01"),
 285         INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"),
 286         INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"),
 287
 288         INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
 289         INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
 290         INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
 291
 292         { /* end: all zeroes */ },
 293 };
 294
 295 #define SNB_UNCORE_PCI_IMC_EVENT_MASK           0xff
 296 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET           0x48
 297
 298 /* page size multiple covering all config regs */
 299 #define SNB_UNCORE_PCI_IMC_MAP_SIZE             0x6000
 300
 301 #define SNB_UNCORE_PCI_IMC_DATA_READS           0x1
 302 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE      0x5050
 303 #define SNB_UNCORE_PCI_IMC_DATA_WRITES          0x2
 304 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE     0x5054
 305 #define SNB_UNCORE_PCI_IMC_CTR_BASE             SNB_UNCORE_PCI_IMC_DATA_READS_BASE
 306
 307 enum perf_snb_uncore_imc_freerunning_types {
 308         SNB_PCI_UNCORE_IMC_DATA         = 0,
 309         SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
 310 };
 311
 312 static struct freerunning_counters snb_uncore_imc_freerunning[] = {
 313         [SNB_PCI_UNCORE_IMC_DATA]     = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x4, 0x0, 2, 32 },
 314 };
 315
 316 static struct attribute *snb_uncore_imc_formats_attr[] = {
 317         &format_attr_event.attr,
 318         NULL,
 319 };
 320
 321 static const struct attribute_group snb_uncore_imc_format_group = {
 322         .name = "format",
 323         .attrs = snb_uncore_imc_formats_attr,
 324 };
 325
 326 static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
 327 {
 328         struct pci_dev *pdev = box->pci_dev;
 329         int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET;
 330         resource_size_t addr;
 331         u32 pci_dword;
 332
 333         pci_read_config_dword(pdev, where, &pci_dword);
 334         addr = pci_dword;
 335
 336 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 337         pci_read_config_dword(pdev, where + 4, &pci_dword);
 338         addr |= ((resource_size_t)pci_dword << 32);
 339 #endif
 340
 341         addr &= ~(PAGE_SIZE - 1);
 342
 343         box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
 344         box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
 345 }
 346
 347 static void snb_uncore_imc_exit_box(struct intel_uncore_box *box)
 348 {
 349         iounmap(box->io_addr);
 350 }
 351
 352 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
 353 {}
 354
 355 static void snb_uncore_imc_disable_box(struct intel_uncore_box *box)
 356 {}
 357
 358 static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 359 {}
 360
 361 static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event)
 362 {}
 363
 364 static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event)
 365 {
 366         struct hw_perf_event *hwc = &event->hw;
 367
 368         return (u64)*(unsigned int *)(box->io_addr + hwc->event_base);
 369 }
 370
 371 /*
 372  * Keep the custom event_init() function compatible with old event
 373  * encoding for free running counters.
 374  */
 375 static int snb_uncore_imc_event_init(struct perf_event *event)
 376 {
 377         struct intel_uncore_pmu *pmu;
 378         struct intel_uncore_box *box;
 379         struct hw_perf_event *hwc = &event->hw;
 380         u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK;
 381         int idx, base;
 382
 383         if (event->attr.type != event->pmu->type)
 384                 return -ENOENT;
 385
 386         pmu = uncore_event_to_pmu(event);
 387         /* no device found for this pmu */
 388         if (pmu->func_id < 0)
 389                 return -ENOENT;
 390
 391         /* Sampling not supported yet */
 392         if (hwc->sample_period)
 393                 return -EINVAL;
 394
 395         /* unsupported modes and filters */
 396         if (event->attr.exclude_user   ||
 397             event->attr.exclude_kernel ||
 398             event->attr.exclude_hv     ||
 399             event->attr.exclude_idle   ||
 400             event->attr.exclude_host   ||
 401             event->attr.exclude_guest  ||
 402             event->attr.sample_period) /* no sampling */
 403                 return -EINVAL;
 404
 405         /*
 406          * Place all uncore events for a particular physical package
 407          * onto a single cpu
 408          */
 409         if (event->cpu < 0)
 410                 return -EINVAL;
 411
 412         /* check only supported bits are set */
 413         if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK)
 414                 return -EINVAL;
 415
 416         box = uncore_pmu_to_box(pmu, event->cpu);
 417         if (!box || box->cpu < 0)
 418                 return -EINVAL;
 419
 420         event->cpu = box->cpu;
 421         event->pmu_private = box;
 422
 423         event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG;
 424
 425         event->hw.idx = -1;
 426         event->hw.last_tag = ~0ULL;
 427         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 428         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 429         /*
 430          * check event is known (whitelist, determines counter)
 431          */
 432         switch (cfg) {
 433         case SNB_UNCORE_PCI_IMC_DATA_READS:
 434                 base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
 435                 idx = UNCORE_PMC_IDX_FREERUNNING;
 436                 break;
 437         case SNB_UNCORE_PCI_IMC_DATA_WRITES:
 438                 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
 439                 idx = UNCORE_PMC_IDX_FREERUNNING;
 440                 break;
 441         default:
 442                 return -EINVAL;
 443         }
 444
 445         /* must be done before validate_group */
 446         event->hw.event_base = base;
 447         event->hw.idx = idx;
 448
 449         /* Convert to standard encoding format for freerunning counters */
 450         event->hw.config = ((cfg - 1) << 8) | 0x10ff;
 451
 452         /* no group validation needed, we have free running counters */
 453
 454         return 0;
 455 }
 456
 457 static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event)
 458 {
 459         return 0;
 460 }
 461
 462 int snb_pci2phy_map_init(int devid)
 463 {
 464         struct pci_dev *dev = NULL;
 465         struct pci2phy_map *map;
 466         int bus, segment;
 467
 468         dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev);
 469         if (!dev)
 470                 return -ENOTTY;
 471
 472         bus = dev->bus->number;
 473         segment = pci_domain_nr(dev->bus);
 474
 475         raw_spin_lock(&pci2phy_map_lock);
 476         map = __find_pci2phy_map(segment);
 477         if (!map) {
 478                 raw_spin_unlock(&pci2phy_map_lock);
 479                 pci_dev_put(dev);
 480                 return -ENOMEM;
 481         }
 482         map->pbus_to_physid[bus] = 0;
 483         raw_spin_unlock(&pci2phy_map_lock);
 484
 485         pci_dev_put(dev);
 486
 487         return 0;
 488 }
 489
 490 static struct pmu snb_uncore_imc_pmu = {
 491         .task_ctx_nr    = perf_invalid_context,
 492         .event_init     = snb_uncore_imc_event_init,
 493         .add            = uncore_pmu_event_add,
 494         .del            = uncore_pmu_event_del,
 495         .start          = uncore_pmu_event_start,
 496         .stop           = uncore_pmu_event_stop,
 497         .read           = uncore_pmu_event_read,
 498 };
 499
 500 static struct intel_uncore_ops snb_uncore_imc_ops = {
 501         .init_box       = snb_uncore_imc_init_box,
 502         .exit_box       = snb_uncore_imc_exit_box,
 503         .enable_box     = snb_uncore_imc_enable_box,
 504         .disable_box    = snb_uncore_imc_disable_box,
 505         .disable_event  = snb_uncore_imc_disable_event,
 506         .enable_event   = snb_uncore_imc_enable_event,
 507         .hw_config      = snb_uncore_imc_hw_config,
 508         .read_counter   = snb_uncore_imc_read_counter,
 509 };
 510
 511 static struct intel_uncore_type snb_uncore_imc = {
 512         .name           = "imc",
 513         .num_counters   = 2,
 514         .num_boxes      = 1,
 515         .num_freerunning_types  = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
 516         .freerunning    = snb_uncore_imc_freerunning,
 517         .event_descs    = snb_uncore_imc_events,
 518         .format_group   = &snb_uncore_imc_format_group,
 519         .ops            = &snb_uncore_imc_ops,
 520         .pmu            = &snb_uncore_imc_pmu,
 521 };
 522
 523 static struct intel_uncore_type *snb_pci_uncores[] = {
 524         [SNB_PCI_UNCORE_IMC]    = &snb_uncore_imc,
 525         NULL,
 526 };
 527
 528 static const struct pci_device_id snb_uncore_pci_ids[] = {
 529         { /* IMC */
 530                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC),
 531                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 532         },
 533         { /* end: all zeroes */ },
 534 };
 535
 536 static const struct pci_device_id ivb_uncore_pci_ids[] = {
 537         { /* IMC */
 538                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC),
 539                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 540         },
 541         { /* IMC */
 542                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_E3_IMC),
 543                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 544         },
 545         { /* end: all zeroes */ },
 546 };
 547
 548 static const struct pci_device_id hsw_uncore_pci_ids[] = {
 549         { /* IMC */
 550                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),
 551                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 552         },
 553         { /* IMC */
 554                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_U_IMC),
 555                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 556         },
 557         { /* end: all zeroes */ },
 558 };
 559
 560 static const struct pci_device_id bdw_uncore_pci_ids[] = {
 561         { /* IMC */
 562                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_IMC),
 563                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 564         },
 565         { /* end: all zeroes */ },
 566 };
 567
 568 static const struct pci_device_id skl_uncore_pci_ids[] = {
 569         { /* IMC */
 570                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_Y_IMC),
 571                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 572         },
 573         { /* IMC */
 574                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_U_IMC),
 575                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 576         },
 577         { /* IMC */
 578                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HD_IMC),
 579                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 580         },
 581         { /* IMC */
 582                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HQ_IMC),
 583                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 584         },
 585         { /* IMC */
 586                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SD_IMC),
 587                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 588         },
 589         { /* IMC */
 590                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC),
 591                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 592         },
 593         { /* IMC */
 594                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC),
 595                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 596         },
 597         { /* IMC */
 598                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_U_IMC),
 599                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 600         },
 601         { /* IMC */
 602                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_UQ_IMC),
 603                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 604         },
 605         { /* IMC */
 606                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SD_IMC),
 607                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 608         },
 609         { /* IMC */
 610                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SQ_IMC),
 611                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 612         },
 613         { /* IMC */
 614                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2U_IMC),
 615                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 616         },
 617         { /* IMC */
 618                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4U_IMC),
 619                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 620         },
 621         { /* IMC */
 622                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4H_IMC),
 623                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 624         },
 625         { /* IMC */
 626                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6H_IMC),
 627                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 628         },
 629         { /* IMC */
 630                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC),
 631                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 632         },
 633         { /* IMC */
 634                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC),
 635                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 636         },
 637         { /* IMC */
 638                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC),
 639                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 640         },
 641         { /* IMC */
 642                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC),
 643                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 644         },
 645         { /* IMC */
 646                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC),
 647                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 648         },
 649         { /* IMC */
 650                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC),
 651                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 652         },
 653         { /* IMC */
 654                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC),
 655                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 656         },
 657         { /* IMC */
 658                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC),
 659                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 660         },
 661         { /* IMC */
 662                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC),
 663                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 664         },
 665         { /* IMC */
 666                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC),
 667                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 668         },
 669         { /* end: all zeroes */ },
 670 };
 671
 672 static struct pci_driver snb_uncore_pci_driver = {
 673         .name           = "snb_uncore",
 674         .id_table       = snb_uncore_pci_ids,
 675 };
 676
 677 static struct pci_driver ivb_uncore_pci_driver = {
 678         .name           = "ivb_uncore",
 679         .id_table       = ivb_uncore_pci_ids,
 680 };
 681
 682 static struct pci_driver hsw_uncore_pci_driver = {
 683         .name           = "hsw_uncore",
 684         .id_table       = hsw_uncore_pci_ids,
 685 };
 686
 687 static struct pci_driver bdw_uncore_pci_driver = {
 688         .name           = "bdw_uncore",
 689         .id_table       = bdw_uncore_pci_ids,
 690 };
 691
 692 static struct pci_driver skl_uncore_pci_driver = {
 693         .name           = "skl_uncore",
 694         .id_table       = skl_uncore_pci_ids,
 695 };
 696
 697 struct imc_uncore_pci_dev {
 698         __u32 pci_id;
 699         struct pci_driver *driver;
 700 };
 701 #define IMC_DEV(a, d) \
 702         { .pci_id = PCI_DEVICE_ID_INTEL_##a, .driver = (d) }
 703
 704 static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
 705         IMC_DEV(SNB_IMC, &snb_uncore_pci_driver),
 706         IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver),    /* 3rd Gen Core processor */
 707         IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */
 708         IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver),    /* 4th Gen Core Processor */
 709         IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver),  /* 4th Gen Core ULT Mobile Processor */
 710         IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver),    /* 5th Gen Core U */
 711         IMC_DEV(SKL_Y_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core Y */
 712         IMC_DEV(SKL_U_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core U */
 713         IMC_DEV(SKL_HD_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core H Dual Core */
 714         IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core H Quad Core */
 715         IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core S Dual Core */
 716         IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core S Quad Core */
 717         IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core Y */
 718         IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core U */
 719         IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core U Quad Core */
 720         IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core S Dual Core */
 721         IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core S Quad Core */
 722         IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core U 2 Cores */
 723         IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core U 4 Cores */
 724         IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core H 4 Cores */
 725         IMC_DEV(CFL_6H_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core H 6 Cores */
 726         IMC_DEV(CFL_2S_D_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 2 Cores Desktop */
 727         IMC_DEV(CFL_4S_D_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 4 Cores Desktop */
 728         IMC_DEV(CFL_6S_D_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 6 Cores Desktop */
 729         IMC_DEV(CFL_8S_D_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 8 Cores Desktop */
 730         IMC_DEV(CFL_4S_W_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 4 Cores Work Station */
 731         IMC_DEV(CFL_6S_W_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 6 Cores Work Station */
 732         IMC_DEV(CFL_8S_W_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 8 Cores Work Station */
 733         IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 4 Cores Server */
 734         IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 6 Cores Server */
 735         IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 8 Cores Server */
 736         {  /* end marker */ }
 737 };
 738
 739
 740 #define for_each_imc_pci_id(x, t) \
 741         for (x = (t); (x)->pci_id; x++)
 742
 743 static struct pci_driver *imc_uncore_find_dev(void)
 744 {
 745         const struct imc_uncore_pci_dev *p;
 746         int ret;
 747
 748         for_each_imc_pci_id(p, desktop_imc_pci_ids) {
 749                 ret = snb_pci2phy_map_init(p->pci_id);
 750                 if (ret == 0)
 751                         return p->driver;
 752         }
 753         return NULL;
 754 }
 755
 756 static int imc_uncore_pci_init(void)
 757 {
 758         struct pci_driver *imc_drv = imc_uncore_find_dev();
 759
 760         if (!imc_drv)
 761                 return -ENODEV;
 762
 763         uncore_pci_uncores = snb_pci_uncores;
 764         uncore_pci_driver = imc_drv;
 765
 766         return 0;
 767 }
 768
 769 int snb_uncore_pci_init(void)
 770 {
 771         return imc_uncore_pci_init();
 772 }
 773
 774 int ivb_uncore_pci_init(void)
 775 {
 776         return imc_uncore_pci_init();
 777 }
 778 int hsw_uncore_pci_init(void)
 779 {
 780         return imc_uncore_pci_init();
 781 }
 782
 783 int bdw_uncore_pci_init(void)
 784 {
 785         return imc_uncore_pci_init();
 786 }
 787
 788 int skl_uncore_pci_init(void)
 789 {
 790         return imc_uncore_pci_init();
 791 }
 792
 793 /* end of Sandy Bridge uncore support */
 794
 795 /* Nehalem uncore support */
 796 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
 797 {
 798         wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
 799 }
 800
 801 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
 802 {
 803         wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
 804 }
 805
 806 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 807 {
 808         struct hw_perf_event *hwc = &event->hw;
 809
 810         if (hwc->idx < UNCORE_PMC_IDX_FIXED)
 811                 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
 812         else
 813                 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
 814 }
 815
 816 static struct attribute *nhm_uncore_formats_attr[] = {
 817         &format_attr_event.attr,
 818         &format_attr_umask.attr,
 819         &format_attr_edge.attr,
 820         &format_attr_inv.attr,
 821         &format_attr_cmask8.attr,
 822         NULL,
 823 };
 824
 825 static const struct attribute_group nhm_uncore_format_group = {
 826         .name = "format",
 827         .attrs = nhm_uncore_formats_attr,
 828 };
 829
 830 static struct uncore_event_desc nhm_uncore_events[] = {
 831         INTEL_UNCORE_EVENT_DESC(clockticks,                "event=0xff,umask=0x00"),
 832         INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any,       "event=0x2f,umask=0x0f"),
 833         INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any,      "event=0x2c,umask=0x0f"),
 834         INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads,     "event=0x20,umask=0x01"),
 835         INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes,    "event=0x20,umask=0x02"),
 836         INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads,  "event=0x20,umask=0x04"),
 837         INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
 838         INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads,   "event=0x20,umask=0x10"),
 839         INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes,  "event=0x20,umask=0x20"),
 840         { /* end: all zeroes */ },
 841 };
 842
 843 static struct intel_uncore_ops nhm_uncore_msr_ops = {
 844         .disable_box    = nhm_uncore_msr_disable_box,
 845         .enable_box     = nhm_uncore_msr_enable_box,
 846         .disable_event  = snb_uncore_msr_disable_event,
 847         .enable_event   = nhm_uncore_msr_enable_event,
 848         .read_counter   = uncore_msr_read_counter,
 849 };
 850
 851 static struct intel_uncore_type nhm_uncore = {
 852         .name           = "",
 853         .num_counters   = 8,
 854         .num_boxes      = 1,
 855         .perf_ctr_bits  = 48,
 856         .fixed_ctr_bits = 48,
 857         .event_ctl      = NHM_UNC_PERFEVTSEL0,
 858         .perf_ctr       = NHM_UNC_UNCORE_PMC0,
 859         .fixed_ctr      = NHM_UNC_FIXED_CTR,
 860         .fixed_ctl      = NHM_UNC_FIXED_CTR_CTRL,
 861         .event_mask     = NHM_UNC_RAW_EVENT_MASK,
 862         .event_descs    = nhm_uncore_events,
 863         .ops            = &nhm_uncore_msr_ops,
 864         .format_group   = &nhm_uncore_format_group,
 865 };
 866
 867 static struct intel_uncore_type *nhm_msr_uncores[] = {
 868         &nhm_uncore,
 869         NULL,
 870 };
 871
 872 void nhm_uncore_cpu_init(void)
 873 {
 874         uncore_msr_uncores = nhm_msr_uncores;
 875 }
 876
 877 /* end of Nehalem uncore support */