arch/x86/include/asm/mce.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_MCE_H
   3 #define _ASM_X86_MCE_H
   4
   5 #include <uapi/asm/mce.h>
   6
   7 /*
   8  * Machine Check support for x86
   9  */
  10
  11 /* MCG_CAP register defines */
  12 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  13 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  14 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  15 #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  16 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  17 #define MCG_EXT_CNT_SHIFT       16
  18 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  19 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  20 #define MCG_ELOG_P              (1ULL<<26)   /* Extended error log supported */
  21 #define MCG_LMCE_P              (1ULL<<27)   /* Local machine check supported */
  22
  23 /* MCG_STATUS register defines */
  24 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  25 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  26 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  27 #define MCG_STATUS_LMCES (1ULL<<3)   /* LMCE signaled */
  28
  29 /* MCG_EXT_CTL register defines */
  30 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
  31
  32 /* MCi_STATUS register defines */
  33 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  34 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  35 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  36 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  37 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  38 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  39 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  40 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  41 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  42
  43 /* AMD-specific bits */
  44 #define MCI_STATUS_TCC          (1ULL<<55)  /* Task context corrupt */
  45 #define MCI_STATUS_SYNDV        (1ULL<<53)  /* synd reg. valid */
  46 #define MCI_STATUS_DEFERRED     (1ULL<<44)  /* uncorrected error, deferred exception */
  47 #define MCI_STATUS_POISON       (1ULL<<43)  /* access poisonous data */
  48
  49 /*
  50  * McaX field if set indicates a given bank supports MCA extensions:
  51  *  - Deferred error interrupt type is specifiable by bank.
  52  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
  53  *    But should not be used to determine MSR numbers.
  54  *  - TCC bit is present in MCx_STATUS.
  55  */
  56 #define MCI_CONFIG_MCAX         0x1
  57 #define MCI_IPID_MCATYPE        0xFFFF0000
  58 #define MCI_IPID_HWID           0xFFF
  59
  60 /*
  61  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
  62  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
  63  * errors to indicate that errors are being filtered by hardware.
  64  * We should mask out bit 12 when looking for specific signatures
  65  * of uncorrected errors - so the F bit is deliberately skipped
  66  * in this #define.
  67  */
  68 #define MCACOD            0xefff     /* MCA Error Code */
  69
  70 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
  71 #define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
  72 #define MCACOD_SCRUBMSK 0xeff0  /* Skip bit 12 ('F' bit) */
  73 #define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
  74 #define MCACOD_DATA     0x0134  /* Data Load */
  75 #define MCACOD_INSTR    0x0150  /* Instruction Fetch */
  76
  77 /* MCi_MISC register defines */
  78 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
  79 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
  80 #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
  81 #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
  82 #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
  83 #define  MCI_MISC_ADDR_MEM      3       /* memory address */
  84 #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
  85
  86 /* CTL2 register defines */
  87 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
  88 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  89
  90 #define MCJ_CTX_MASK            3
  91 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  92 #define MCJ_CTX_RANDOM          0    /* inject context: random */
  93 #define MCJ_CTX_PROCESS         0x1  /* inject context: process */
  94 #define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
  95 #define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
  96 #define MCJ_EXCEPTION           0x8  /* raise as exception */
  97 #define MCJ_IRQ_BROADCAST       0x10 /* do IRQ broadcasting */
  98
  99 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
 100
 101 #define MCE_LOG_LEN 32
 102 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
 103
 104 /* AMD Scalable MCA */
 105 #define MSR_AMD64_SMCA_MC0_CTL          0xc0002000
 106 #define MSR_AMD64_SMCA_MC0_STATUS       0xc0002001
 107 #define MSR_AMD64_SMCA_MC0_ADDR         0xc0002002
 108 #define MSR_AMD64_SMCA_MC0_MISC0        0xc0002003
 109 #define MSR_AMD64_SMCA_MC0_CONFIG       0xc0002004
 110 #define MSR_AMD64_SMCA_MC0_IPID         0xc0002005
 111 #define MSR_AMD64_SMCA_MC0_SYND         0xc0002006
 112 #define MSR_AMD64_SMCA_MC0_DESTAT       0xc0002008
 113 #define MSR_AMD64_SMCA_MC0_DEADDR       0xc0002009
 114 #define MSR_AMD64_SMCA_MC0_MISC1        0xc000200a
 115 #define MSR_AMD64_SMCA_MCx_CTL(x)       (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
 116 #define MSR_AMD64_SMCA_MCx_STATUS(x)    (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
 117 #define MSR_AMD64_SMCA_MCx_ADDR(x)      (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
 118 #define MSR_AMD64_SMCA_MCx_MISC(x)      (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
 119 #define MSR_AMD64_SMCA_MCx_CONFIG(x)    (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
 120 #define MSR_AMD64_SMCA_MCx_IPID(x)      (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
 121 #define MSR_AMD64_SMCA_MCx_SYND(x)      (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
 122 #define MSR_AMD64_SMCA_MCx_DESTAT(x)    (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
 123 #define MSR_AMD64_SMCA_MCx_DEADDR(x)    (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
 124 #define MSR_AMD64_SMCA_MCx_MISCy(x, y)  ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
 125
 126 /*
 127  * This structure contains all data related to the MCE log.  Also
 128  * carries a signature to make it easier to find from external
 129  * debugging tools.  Each entry is only valid when its finished flag
 130  * is set.
 131  */
 132 struct mce_log_buffer {
 133         char signature[12]; /* "MACHINECHECK" */
 134         unsigned len;       /* = MCE_LOG_LEN */
 135         unsigned next;
 136         unsigned flags;
 137         unsigned recordlen;     /* length of struct mce */
 138         struct mce entry[MCE_LOG_LEN];
 139 };
 140
 141 enum mce_notifier_prios {
 142         MCE_PRIO_FIRST          = INT_MAX,
 143         MCE_PRIO_SRAO           = INT_MAX - 1,
 144         MCE_PRIO_EXTLOG         = INT_MAX - 2,
 145         MCE_PRIO_NFIT           = INT_MAX - 3,
 146         MCE_PRIO_EDAC           = INT_MAX - 4,
 147         MCE_PRIO_MCELOG         = 1,
 148         MCE_PRIO_LOWEST         = 0,
 149 };
 150
 151 struct notifier_block;
 152 extern void mce_register_decode_chain(struct notifier_block *nb);
 153 extern void mce_unregister_decode_chain(struct notifier_block *nb);
 154
 155 #include <linux/percpu.h>
 156 #include <linux/atomic.h>
 157
 158 extern int mce_p5_enabled;
 159
 160 #ifdef CONFIG_X86_MCE
 161 int mcheck_init(void);
 162 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 163 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
 164 void mcheck_vendor_init_severity(void);
 165 #else
 166 static inline int mcheck_init(void) { return 0; }
 167 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 168 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
 169 static inline void mcheck_vendor_init_severity(void) {}
 170 #endif
 171
 172 #ifdef CONFIG_X86_ANCIENT_MCE
 173 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 174 void winchip_mcheck_init(struct cpuinfo_x86 *c);
 175 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 176 #else
 177 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 178 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 179 static inline void enable_p5_mce(void) {}
 180 #endif
 181
 182 void mce_setup(struct mce *m);
 183 void mce_log(struct mce *m);
 184 DECLARE_PER_CPU(struct device *, mce_device);
 185
 186 /*
 187  * Maximum banks number.
 188  * This is the limit of the current register layout on
 189  * Intel CPUs.
 190  */
 191 #define MAX_NR_BANKS 32
 192
 193 #ifdef CONFIG_X86_MCE_INTEL
 194 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 195 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
 196 void cmci_clear(void);
 197 void cmci_reenable(void);
 198 void cmci_rediscover(void);
 199 void cmci_recheck(void);
 200 #else
 201 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 202 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
 203 static inline void cmci_clear(void) {}
 204 static inline void cmci_reenable(void) {}
 205 static inline void cmci_rediscover(void) {}
 206 static inline void cmci_recheck(void) {}
 207 #endif
 208
 209 #ifdef CONFIG_X86_MCE_AMD
 210 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 211 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
 212 #else
 213 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 214 static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
 215 #endif
 216
 217 int mce_available(struct cpuinfo_x86 *c);
 218 bool mce_is_memory_error(struct mce *m);
 219 bool mce_is_correctable(struct mce *m);
 220 int mce_usable_address(struct mce *m);
 221
 222 DECLARE_PER_CPU(unsigned, mce_exception_count);
 223 DECLARE_PER_CPU(unsigned, mce_poll_count);
 224
 225 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 226 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 227
 228 enum mcp_flags {
 229         MCP_TIMESTAMP   = BIT(0),       /* log time stamp */
 230         MCP_UC          = BIT(1),       /* log uncorrected errors */
 231         MCP_DONTLOG     = BIT(2),       /* only clear, don't log */
 232 };
 233 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 234
 235 int mce_notify_irq(void);
 236
 237 DECLARE_PER_CPU(struct mce, injectm);
 238
 239 /* Disable CMCI/polling for MCA bank claimed by firmware */
 240 extern void mce_disable_bank(int bank);
 241
 242 /*
 243  * Exception handler
 244  */
 245
 246 /* Call the installed machine check handler for this CPU setup. */
 247 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 248 void do_machine_check(struct pt_regs *, long);
 249
 250 /*
 251  * Threshold handler
 252  */
 253 extern void (*mce_threshold_vector)(void);
 254
 255 /* Deferred error interrupt handler */
 256 extern void (*deferred_error_int_vector)(void);
 257
 258 /*
 259  * Thermal handler
 260  */
 261
 262 void intel_init_thermal(struct cpuinfo_x86 *c);
 263
 264 /* Interrupt Handler for core thermal thresholds */
 265 extern int (*platform_thermal_notify)(__u64 msr_val);
 266
 267 /* Interrupt Handler for package thermal thresholds */
 268 extern int (*platform_thermal_package_notify)(__u64 msr_val);
 269
 270 /* Callback support of rate control, return true, if
 271  * callback has rate control */
 272 extern bool (*platform_thermal_package_rate_control)(void);
 273
 274 #ifdef CONFIG_X86_THERMAL_VECTOR
 275 extern void mcheck_intel_therm_init(void);
 276 #else
 277 static inline void mcheck_intel_therm_init(void) { }
 278 #endif
 279
 280 /*
 281  * Used by APEI to report memory error via /dev/mcelog
 282  */
 283
 284 struct cper_sec_mem_err;
 285 extern void apei_mce_report_mem_error(int corrected,
 286                                       struct cper_sec_mem_err *mem_err);
 287
 288 /*
 289  * Enumerate new IP types and HWID values in AMD processors which support
 290  * Scalable MCA.
 291  */
 292 #ifdef CONFIG_X86_MCE_AMD
 293
 294 /* These may be used by multiple smca_hwid_mcatypes */
 295 enum smca_bank_types {
 296         SMCA_LS = 0,    /* Load Store */
 297         SMCA_IF,        /* Instruction Fetch */
 298         SMCA_L2_CACHE,  /* L2 Cache */
 299         SMCA_DE,        /* Decoder Unit */
 300         SMCA_RESERVED,  /* Reserved */
 301         SMCA_EX,        /* Execution Unit */
 302         SMCA_FP,        /* Floating Point */
 303         SMCA_L3_CACHE,  /* L3 Cache */
 304         SMCA_CS,        /* Coherent Slave */
 305         SMCA_PIE,       /* Power, Interrupts, etc. */
 306         SMCA_UMC,       /* Unified Memory Controller */
 307         SMCA_PB,        /* Parameter Block */
 308         SMCA_PSP,       /* Platform Security Processor */
 309         SMCA_SMU,       /* System Management Unit */
 310         N_SMCA_BANK_TYPES
 311 };
 312
 313 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
 314
 315 struct smca_hwid {
 316         unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
 317         u32 hwid_mcatype;       /* (hwid,mcatype) tuple */
 318         u32 xec_bitmap;         /* Bitmap of valid ExtErrorCodes; current max is 21. */
 319         u8 count;               /* Number of instances. */
 320 };
 321
 322 struct smca_bank {
 323         struct smca_hwid *hwid;
 324         u32 id;                 /* Value of MCA_IPID[InstanceId]. */
 325         u8 sysfs_id;            /* Value used for sysfs name. */
 326 };
 327
 328 extern struct smca_bank smca_banks[MAX_NR_BANKS];
 329
 330 extern const char *smca_get_long_name(enum smca_bank_types t);
 331 extern bool amd_mce_is_memory_error(struct mce *m);
 332
 333 extern int mce_threshold_create_device(unsigned int cpu);
 334 extern int mce_threshold_remove_device(unsigned int cpu);
 335
 336 #else
 337
 338 static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
 339 static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
 340 static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
 341
 342 #endif
 343
 344 #endif /* _ASM_X86_MCE_H */