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stmmac: fix a filter problem after resuming.
[linux/fpc-iii.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
blob1795c935ff023fcf795008a49a9a4cd0fce63d9c
1 /*
2 * Copyright (C) 2005 - 2015 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 #include <linux/module.h>
19 #include "be.h"
20 #include "be_cmds.h"
21
22 static char *be_port_misconfig_evt_desc[] = {
23 "A valid SFP module detected",
24 "Optics faulted/ incorrectly installed/ not installed.",
25 "Optics of two types installed.",
26 "Incompatible optics.",
27 "Unknown port SFP status"
28 };
29
30 static char *be_port_misconfig_remedy_desc[] = {
31 "",
32 "Reseat optics. If issue not resolved, replace",
33 "Remove one optic or install matching pair of optics",
34 "Replace with compatible optics for card to function",
35 ""
36 };
37
38 static struct be_cmd_priv_map cmd_priv_map[] = {
39 {
40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
41 CMD_SUBSYSTEM_ETH,
42 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
43 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
44 },
45 {
46 OPCODE_COMMON_GET_FLOW_CONTROL,
47 CMD_SUBSYSTEM_COMMON,
48 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
50 },
51 {
52 OPCODE_COMMON_SET_FLOW_CONTROL,
53 CMD_SUBSYSTEM_COMMON,
54 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
56 },
57 {
58 OPCODE_ETH_GET_PPORT_STATS,
59 CMD_SUBSYSTEM_ETH,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
62 },
63 {
64 OPCODE_COMMON_GET_PHY_DETAILS,
65 CMD_SUBSYSTEM_COMMON,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
68 }
69 };
70
71 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
72 {
73 int i;
74 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
75 u32 cmd_privileges = adapter->cmd_privileges;
76
77 for (i = 0; i < num_entries; i++)
78 if (opcode == cmd_priv_map[i].opcode &&
79 subsystem == cmd_priv_map[i].subsystem)
80 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
81 return false;
82
83 return true;
84 }
85
86 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
87 {
88 return wrb->payload.embedded_payload;
89 }
90
91 static int be_mcc_notify(struct be_adapter *adapter)
92 {
93 struct be_queue_info *mccq = &adapter->mcc_obj.q;
94 u32 val = 0;
95
96 if (be_check_error(adapter, BE_ERROR_ANY))
97 return -EIO;
98
99 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
100 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
101
102 wmb();
103 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
104
105 return 0;
106 }
107
108 /* To check if valid bit is set, check the entire word as we don't know
109 * the endianness of the data (old entry is host endian while a new entry is
110 * little endian) */
111 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
112 {
113 u32 flags;
114
115 if (compl->flags != 0) {
116 flags = le32_to_cpu(compl->flags);
117 if (flags & CQE_FLAGS_VALID_MASK) {
118 compl->flags = flags;
119 return true;
120 }
121 }
122 return false;
123 }
124
125 /* Need to reset the entire word that houses the valid bit */
126 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
127 {
128 compl->flags = 0;
129 }
130
131 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
132 {
133 unsigned long addr;
134
135 addr = tag1;
136 addr = ((addr << 16) << 16) | tag0;
137 return (void *)addr;
138 }
139
140 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
141 {
142 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
143 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
144 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
145 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
146 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
147 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
148 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
149 return true;
150 else
151 return false;
152 }
153
154 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
155 * loop (has not issued be_mcc_notify_wait())
156 */
157 static void be_async_cmd_process(struct be_adapter *adapter,
158 struct be_mcc_compl *compl,
159 struct be_cmd_resp_hdr *resp_hdr)
160 {
161 enum mcc_base_status base_status = base_status(compl->status);
162 u8 opcode = 0, subsystem = 0;
163
164 if (resp_hdr) {
165 opcode = resp_hdr->opcode;
166 subsystem = resp_hdr->subsystem;
167 }
168
169 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
170 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
171 complete(&adapter->et_cmd_compl);
172 return;
173 }
174
175 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
176 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
177 complete(&adapter->et_cmd_compl);
178 return;
179 }
180
181 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
182 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
183 subsystem == CMD_SUBSYSTEM_COMMON) {
184 adapter->flash_status = compl->status;
185 complete(&adapter->et_cmd_compl);
186 return;
187 }
188
189 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
190 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
191 subsystem == CMD_SUBSYSTEM_ETH &&
192 base_status == MCC_STATUS_SUCCESS) {
193 be_parse_stats(adapter);
194 adapter->stats_cmd_sent = false;
195 return;
196 }
197
198 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
199 subsystem == CMD_SUBSYSTEM_COMMON) {
200 if (base_status == MCC_STATUS_SUCCESS) {
201 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
202 (void *)resp_hdr;
203 adapter->hwmon_info.be_on_die_temp =
204 resp->on_die_temperature;
205 } else {
206 adapter->be_get_temp_freq = 0;
207 adapter->hwmon_info.be_on_die_temp =
208 BE_INVALID_DIE_TEMP;
209 }
210 return;
211 }
212 }
213
214 static int be_mcc_compl_process(struct be_adapter *adapter,
215 struct be_mcc_compl *compl)
216 {
217 enum mcc_base_status base_status;
218 enum mcc_addl_status addl_status;
219 struct be_cmd_resp_hdr *resp_hdr;
220 u8 opcode = 0, subsystem = 0;
221
222 /* Just swap the status to host endian; mcc tag is opaquely copied
223 * from mcc_wrb */
224 be_dws_le_to_cpu(compl, 4);
225
226 base_status = base_status(compl->status);
227 addl_status = addl_status(compl->status);
228
229 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
230 if (resp_hdr) {
231 opcode = resp_hdr->opcode;
232 subsystem = resp_hdr->subsystem;
233 }
234
235 be_async_cmd_process(adapter, compl, resp_hdr);
236
237 if (base_status != MCC_STATUS_SUCCESS &&
238 !be_skip_err_log(opcode, base_status, addl_status)) {
239 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
240 dev_warn(&adapter->pdev->dev,
241 "VF is not privileged to issue opcode %d-%d\n",
242 opcode, subsystem);
243 } else {
244 dev_err(&adapter->pdev->dev,
245 "opcode %d-%d failed:status %d-%d\n",
246 opcode, subsystem, base_status, addl_status);
247 }
248 }
249 return compl->status;
250 }
251
252 /* Link state evt is a string of bytes; no need for endian swapping */
253 static void be_async_link_state_process(struct be_adapter *adapter,
254 struct be_mcc_compl *compl)
255 {
256 struct be_async_event_link_state *evt =
257 (struct be_async_event_link_state *)compl;
258
259 /* When link status changes, link speed must be re-queried from FW */
260 adapter->phy.link_speed = -1;
261
262 /* On BEx the FW does not send a separate link status
263 * notification for physical and logical link.
264 * On other chips just process the logical link
265 * status notification
266 */
267 if (!BEx_chip(adapter) &&
268 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
269 return;
270
271 /* For the initial link status do not rely on the ASYNC event as
272 * it may not be received in some cases.
273 */
274 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
275 be_link_status_update(adapter,
276 evt->port_link_status & LINK_STATUS_MASK);
277 }
278
279 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
280 struct be_mcc_compl *compl)
281 {
282 struct be_async_event_misconfig_port *evt =
283 (struct be_async_event_misconfig_port *)compl;
284 u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
285 struct device *dev = &adapter->pdev->dev;
286 u8 port_misconfig_evt;
287
288 port_misconfig_evt =
289 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
290
291 /* Log an error message that would allow a user to determine
292 * whether the SFPs have an issue
293 */
294 dev_info(dev, "Port %c: %s %s", adapter->port_name,
295 be_port_misconfig_evt_desc[port_misconfig_evt],
296 be_port_misconfig_remedy_desc[port_misconfig_evt]);
297
298 if (port_misconfig_evt == INCOMPATIBLE_SFP)
299 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
300 }
301
302 /* Grp5 CoS Priority evt */
303 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
304 struct be_mcc_compl *compl)
305 {
306 struct be_async_event_grp5_cos_priority *evt =
307 (struct be_async_event_grp5_cos_priority *)compl;
308
309 if (evt->valid) {
310 adapter->vlan_prio_bmap = evt->available_priority_bmap;
311 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
312 adapter->recommended_prio =
313 evt->reco_default_priority << VLAN_PRIO_SHIFT;
314 }
315 }
316
317 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
318 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
319 struct be_mcc_compl *compl)
320 {
321 struct be_async_event_grp5_qos_link_speed *evt =
322 (struct be_async_event_grp5_qos_link_speed *)compl;
323
324 if (adapter->phy.link_speed >= 0 &&
325 evt->physical_port == adapter->port_num)
326 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
327 }
328
329 /*Grp5 PVID evt*/
330 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
331 struct be_mcc_compl *compl)
332 {
333 struct be_async_event_grp5_pvid_state *evt =
334 (struct be_async_event_grp5_pvid_state *)compl;
335
336 if (evt->enabled) {
337 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
338 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
339 } else {
340 adapter->pvid = 0;
341 }
342 }
343
344 #define MGMT_ENABLE_MASK 0x4
345 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
346 struct be_mcc_compl *compl)
347 {
348 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
349 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
350
351 if (evt_dw1 & MGMT_ENABLE_MASK) {
352 adapter->flags |= BE_FLAGS_OS2BMC;
353 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
354 } else {
355 adapter->flags &= ~BE_FLAGS_OS2BMC;
356 }
357 }
358
359 static void be_async_grp5_evt_process(struct be_adapter *adapter,
360 struct be_mcc_compl *compl)
361 {
362 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
363 ASYNC_EVENT_TYPE_MASK;
364
365 switch (event_type) {
366 case ASYNC_EVENT_COS_PRIORITY:
367 be_async_grp5_cos_priority_process(adapter, compl);
368 break;
369 case ASYNC_EVENT_QOS_SPEED:
370 be_async_grp5_qos_speed_process(adapter, compl);
371 break;
372 case ASYNC_EVENT_PVID_STATE:
373 be_async_grp5_pvid_state_process(adapter, compl);
374 break;
375 /* Async event to disable/enable os2bmc and/or mac-learning */
376 case ASYNC_EVENT_FW_CONTROL:
377 be_async_grp5_fw_control_process(adapter, compl);
378 break;
379 default:
380 break;
381 }
382 }
383
384 static void be_async_dbg_evt_process(struct be_adapter *adapter,
385 struct be_mcc_compl *cmp)
386 {
387 u8 event_type = 0;
388 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
389
390 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
391 ASYNC_EVENT_TYPE_MASK;
392
393 switch (event_type) {
394 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
395 if (evt->valid)
396 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
397 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
398 break;
399 default:
400 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
401 event_type);
402 break;
403 }
404 }
405
406 static void be_async_sliport_evt_process(struct be_adapter *adapter,
407 struct be_mcc_compl *cmp)
408 {
409 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
410 ASYNC_EVENT_TYPE_MASK;
411
412 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
413 be_async_port_misconfig_event_process(adapter, cmp);
414 }
415
416 static inline bool is_link_state_evt(u32 flags)
417 {
418 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
419 ASYNC_EVENT_CODE_LINK_STATE;
420 }
421
422 static inline bool is_grp5_evt(u32 flags)
423 {
424 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
425 ASYNC_EVENT_CODE_GRP_5;
426 }
427
428 static inline bool is_dbg_evt(u32 flags)
429 {
430 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
431 ASYNC_EVENT_CODE_QNQ;
432 }
433
434 static inline bool is_sliport_evt(u32 flags)
435 {
436 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
437 ASYNC_EVENT_CODE_SLIPORT;
438 }
439
440 static void be_mcc_event_process(struct be_adapter *adapter,
441 struct be_mcc_compl *compl)
442 {
443 if (is_link_state_evt(compl->flags))
444 be_async_link_state_process(adapter, compl);
445 else if (is_grp5_evt(compl->flags))
446 be_async_grp5_evt_process(adapter, compl);
447 else if (is_dbg_evt(compl->flags))
448 be_async_dbg_evt_process(adapter, compl);
449 else if (is_sliport_evt(compl->flags))
450 be_async_sliport_evt_process(adapter, compl);
451 }
452
453 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
454 {
455 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
456 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
457
458 if (be_mcc_compl_is_new(compl)) {
459 queue_tail_inc(mcc_cq);
460 return compl;
461 }
462 return NULL;
463 }
464
465 void be_async_mcc_enable(struct be_adapter *adapter)
466 {
467 spin_lock_bh(&adapter->mcc_cq_lock);
468
469 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
470 adapter->mcc_obj.rearm_cq = true;
471
472 spin_unlock_bh(&adapter->mcc_cq_lock);
473 }
474
475 void be_async_mcc_disable(struct be_adapter *adapter)
476 {
477 spin_lock_bh(&adapter->mcc_cq_lock);
478
479 adapter->mcc_obj.rearm_cq = false;
480 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
481
482 spin_unlock_bh(&adapter->mcc_cq_lock);
483 }
484
485 int be_process_mcc(struct be_adapter *adapter)
486 {
487 struct be_mcc_compl *compl;
488 int num = 0, status = 0;
489 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
490
491 spin_lock(&adapter->mcc_cq_lock);
492
493 while ((compl = be_mcc_compl_get(adapter))) {
494 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
495 be_mcc_event_process(adapter, compl);
496 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
497 status = be_mcc_compl_process(adapter, compl);
498 atomic_dec(&mcc_obj->q.used);
499 }
500 be_mcc_compl_use(compl);
501 num++;
502 }
503
504 if (num)
505 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
506
507 spin_unlock(&adapter->mcc_cq_lock);
508 return status;
509 }
510
511 /* Wait till no more pending mcc requests are present */
512 static int be_mcc_wait_compl(struct be_adapter *adapter)
513 {
514 #define mcc_timeout 120000 /* 12s timeout */
515 int i, status = 0;
516 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
517
518 for (i = 0; i < mcc_timeout; i++) {
519 if (be_check_error(adapter, BE_ERROR_ANY))
520 return -EIO;
521
522 local_bh_disable();
523 status = be_process_mcc(adapter);
524 local_bh_enable();
525
526 if (atomic_read(&mcc_obj->q.used) == 0)
527 break;
528 udelay(100);
529 }
530 if (i == mcc_timeout) {
531 dev_err(&adapter->pdev->dev, "FW not responding\n");
532 be_set_error(adapter, BE_ERROR_FW);
533 return -EIO;
534 }
535 return status;
536 }
537
538 /* Notify MCC requests and wait for completion */
539 static int be_mcc_notify_wait(struct be_adapter *adapter)
540 {
541 int status;
542 struct be_mcc_wrb *wrb;
543 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
544 u16 index = mcc_obj->q.head;
545 struct be_cmd_resp_hdr *resp;
546
547 index_dec(&index, mcc_obj->q.len);
548 wrb = queue_index_node(&mcc_obj->q, index);
549
550 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
551
552 status = be_mcc_notify(adapter);
553 if (status)
554 goto out;
555
556 status = be_mcc_wait_compl(adapter);
557 if (status == -EIO)
558 goto out;
559
560 status = (resp->base_status |
561 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
562 CQE_ADDL_STATUS_SHIFT));
563 out:
564 return status;
565 }
566
567 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
568 {
569 int msecs = 0;
570 u32 ready;
571
572 do {
573 if (be_check_error(adapter, BE_ERROR_ANY))
574 return -EIO;
575
576 ready = ioread32(db);
577 if (ready == 0xffffffff)
578 return -1;
579
580 ready &= MPU_MAILBOX_DB_RDY_MASK;
581 if (ready)
582 break;
583
584 if (msecs > 4000) {
585 dev_err(&adapter->pdev->dev, "FW not responding\n");
586 be_set_error(adapter, BE_ERROR_FW);
587 be_detect_error(adapter);
588 return -1;
589 }
590
591 msleep(1);
592 msecs++;
593 } while (true);
594
595 return 0;
596 }
597
598 /*
599 * Insert the mailbox address into the doorbell in two steps
600 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
601 */
602 static int be_mbox_notify_wait(struct be_adapter *adapter)
603 {
604 int status;
605 u32 val = 0;
606 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
607 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
608 struct be_mcc_mailbox *mbox = mbox_mem->va;
609 struct be_mcc_compl *compl = &mbox->compl;
610
611 /* wait for ready to be set */
612 status = be_mbox_db_ready_wait(adapter, db);
613 if (status != 0)
614 return status;
615
616 val |= MPU_MAILBOX_DB_HI_MASK;
617 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
618 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
619 iowrite32(val, db);
620
621 /* wait for ready to be set */
622 status = be_mbox_db_ready_wait(adapter, db);
623 if (status != 0)
624 return status;
625
626 val = 0;
627 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
628 val |= (u32)(mbox_mem->dma >> 4) << 2;
629 iowrite32(val, db);
630
631 status = be_mbox_db_ready_wait(adapter, db);
632 if (status != 0)
633 return status;
634
635 /* A cq entry has been made now */
636 if (be_mcc_compl_is_new(compl)) {
637 status = be_mcc_compl_process(adapter, &mbox->compl);
638 be_mcc_compl_use(compl);
639 if (status)
640 return status;
641 } else {
642 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
643 return -1;
644 }
645 return 0;
646 }
647
648 static u16 be_POST_stage_get(struct be_adapter *adapter)
649 {
650 u32 sem;
651
652 if (BEx_chip(adapter))
653 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
654 else
655 pci_read_config_dword(adapter->pdev,
656 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
657
658 return sem & POST_STAGE_MASK;
659 }
660
661 static int lancer_wait_ready(struct be_adapter *adapter)
662 {
663 #define SLIPORT_READY_TIMEOUT 30
664 u32 sliport_status;
665 int i;
666
667 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
668 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
669 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
670 return 0;
671
672 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
673 !(sliport_status & SLIPORT_STATUS_RN_MASK))
674 return -EIO;
675
676 msleep(1000);
677 }
678
679 return sliport_status ? : -1;
680 }
681
682 int be_fw_wait_ready(struct be_adapter *adapter)
683 {
684 u16 stage;
685 int status, timeout = 0;
686 struct device *dev = &adapter->pdev->dev;
687
688 if (lancer_chip(adapter)) {
689 status = lancer_wait_ready(adapter);
690 if (status) {
691 stage = status;
692 goto err;
693 }
694 return 0;
695 }
696
697 do {
698 /* There's no means to poll POST state on BE2/3 VFs */
699 if (BEx_chip(adapter) && be_virtfn(adapter))
700 return 0;
701
702 stage = be_POST_stage_get(adapter);
703 if (stage == POST_STAGE_ARMFW_RDY)
704 return 0;
705
706 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
707 if (msleep_interruptible(2000)) {
708 dev_err(dev, "Waiting for POST aborted\n");
709 return -EINTR;
710 }
711 timeout += 2;
712 } while (timeout < 60);
713
714 err:
715 dev_err(dev, "POST timeout; stage=%#x\n", stage);
716 return -ETIMEDOUT;
717 }
718
719 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
720 {
721 return &wrb->payload.sgl[0];
722 }
723
724 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
725 {
726 wrb->tag0 = addr & 0xFFFFFFFF;
727 wrb->tag1 = upper_32_bits(addr);
728 }
729
730 /* Don't touch the hdr after it's prepared */
731 /* mem will be NULL for embedded commands */
732 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
733 u8 subsystem, u8 opcode, int cmd_len,
734 struct be_mcc_wrb *wrb,
735 struct be_dma_mem *mem)
736 {
737 struct be_sge *sge;
738
739 req_hdr->opcode = opcode;
740 req_hdr->subsystem = subsystem;
741 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
742 req_hdr->version = 0;
743 fill_wrb_tags(wrb, (ulong) req_hdr);
744 wrb->payload_length = cmd_len;
745 if (mem) {
746 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
747 MCC_WRB_SGE_CNT_SHIFT;
748 sge = nonembedded_sgl(wrb);
749 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
750 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
751 sge->len = cpu_to_le32(mem->size);
752 } else
753 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
754 be_dws_cpu_to_le(wrb, 8);
755 }
756
757 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
758 struct be_dma_mem *mem)
759 {
760 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
761 u64 dma = (u64)mem->dma;
762
763 for (i = 0; i < buf_pages; i++) {
764 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
765 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
766 dma += PAGE_SIZE_4K;
767 }
768 }
769
770 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
771 {
772 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
773 struct be_mcc_wrb *wrb
774 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
775 memset(wrb, 0, sizeof(*wrb));
776 return wrb;
777 }
778
779 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
780 {
781 struct be_queue_info *mccq = &adapter->mcc_obj.q;
782 struct be_mcc_wrb *wrb;
783
784 if (!mccq->created)
785 return NULL;
786
787 if (atomic_read(&mccq->used) >= mccq->len)
788 return NULL;
789
790 wrb = queue_head_node(mccq);
791 queue_head_inc(mccq);
792 atomic_inc(&mccq->used);
793 memset(wrb, 0, sizeof(*wrb));
794 return wrb;
795 }
796
797 static bool use_mcc(struct be_adapter *adapter)
798 {
799 return adapter->mcc_obj.q.created;
800 }
801
802 /* Must be used only in process context */
803 static int be_cmd_lock(struct be_adapter *adapter)
804 {
805 if (use_mcc(adapter)) {
806 spin_lock_bh(&adapter->mcc_lock);
807 return 0;
808 } else {
809 return mutex_lock_interruptible(&adapter->mbox_lock);
810 }
811 }
812
813 /* Must be used only in process context */
814 static void be_cmd_unlock(struct be_adapter *adapter)
815 {
816 if (use_mcc(adapter))
817 spin_unlock_bh(&adapter->mcc_lock);
818 else
819 return mutex_unlock(&adapter->mbox_lock);
820 }
821
822 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
823 struct be_mcc_wrb *wrb)
824 {
825 struct be_mcc_wrb *dest_wrb;
826
827 if (use_mcc(adapter)) {
828 dest_wrb = wrb_from_mccq(adapter);
829 if (!dest_wrb)
830 return NULL;
831 } else {
832 dest_wrb = wrb_from_mbox(adapter);
833 }
834
835 memcpy(dest_wrb, wrb, sizeof(*wrb));
836 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
837 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
838
839 return dest_wrb;
840 }
841
842 /* Must be used only in process context */
843 static int be_cmd_notify_wait(struct be_adapter *adapter,
844 struct be_mcc_wrb *wrb)
845 {
846 struct be_mcc_wrb *dest_wrb;
847 int status;
848
849 status = be_cmd_lock(adapter);
850 if (status)
851 return status;
852
853 dest_wrb = be_cmd_copy(adapter, wrb);
854 if (!dest_wrb) {
855 status = -EBUSY;
856 goto unlock;
857 }
858
859 if (use_mcc(adapter))
860 status = be_mcc_notify_wait(adapter);
861 else
862 status = be_mbox_notify_wait(adapter);
863
864 if (!status)
865 memcpy(wrb, dest_wrb, sizeof(*wrb));
866
867 unlock:
868 be_cmd_unlock(adapter);
869 return status;
870 }
871
872 /* Tell fw we're about to start firing cmds by writing a
873 * special pattern across the wrb hdr; uses mbox
874 */
875 int be_cmd_fw_init(struct be_adapter *adapter)
876 {
877 u8 *wrb;
878 int status;
879
880 if (lancer_chip(adapter))
881 return 0;
882
883 if (mutex_lock_interruptible(&adapter->mbox_lock))
884 return -1;
885
886 wrb = (u8 *)wrb_from_mbox(adapter);
887 *wrb++ = 0xFF;
888 *wrb++ = 0x12;
889 *wrb++ = 0x34;
890 *wrb++ = 0xFF;
891 *wrb++ = 0xFF;
892 *wrb++ = 0x56;
893 *wrb++ = 0x78;
894 *wrb = 0xFF;
895
896 status = be_mbox_notify_wait(adapter);
897
898 mutex_unlock(&adapter->mbox_lock);
899 return status;
900 }
901
902 /* Tell fw we're done with firing cmds by writing a
903 * special pattern across the wrb hdr; uses mbox
904 */
905 int be_cmd_fw_clean(struct be_adapter *adapter)
906 {
907 u8 *wrb;
908 int status;
909
910 if (lancer_chip(adapter))
911 return 0;
912
913 if (mutex_lock_interruptible(&adapter->mbox_lock))
914 return -1;
915
916 wrb = (u8 *)wrb_from_mbox(adapter);
917 *wrb++ = 0xFF;
918 *wrb++ = 0xAA;
919 *wrb++ = 0xBB;
920 *wrb++ = 0xFF;
921 *wrb++ = 0xFF;
922 *wrb++ = 0xCC;
923 *wrb++ = 0xDD;
924 *wrb = 0xFF;
925
926 status = be_mbox_notify_wait(adapter);
927
928 mutex_unlock(&adapter->mbox_lock);
929 return status;
930 }
931
932 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
933 {
934 struct be_mcc_wrb *wrb;
935 struct be_cmd_req_eq_create *req;
936 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
937 int status, ver = 0;
938
939 if (mutex_lock_interruptible(&adapter->mbox_lock))
940 return -1;
941
942 wrb = wrb_from_mbox(adapter);
943 req = embedded_payload(wrb);
944
945 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
946 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
947 NULL);
948
949 /* Support for EQ_CREATEv2 available only SH-R onwards */
950 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
951 ver = 2;
952
953 req->hdr.version = ver;
954 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
955
956 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
957 /* 4byte eqe*/
958 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
959 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
960 __ilog2_u32(eqo->q.len / 256));
961 be_dws_cpu_to_le(req->context, sizeof(req->context));
962
963 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
964
965 status = be_mbox_notify_wait(adapter);
966 if (!status) {
967 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
968
969 eqo->q.id = le16_to_cpu(resp->eq_id);
970 eqo->msix_idx =
971 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
972 eqo->q.created = true;
973 }
974
975 mutex_unlock(&adapter->mbox_lock);
976 return status;
977 }
978
979 /* Use MCC */
980 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
981 bool permanent, u32 if_handle, u32 pmac_id)
982 {
983 struct be_mcc_wrb *wrb;
984 struct be_cmd_req_mac_query *req;
985 int status;
986
987 spin_lock_bh(&adapter->mcc_lock);
988
989 wrb = wrb_from_mccq(adapter);
990 if (!wrb) {
991 status = -EBUSY;
992 goto err;
993 }
994 req = embedded_payload(wrb);
995
996 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
997 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
998 NULL);
999 req->type = MAC_ADDRESS_TYPE_NETWORK;
1000 if (permanent) {
1001 req->permanent = 1;
1002 } else {
1003 req->if_id = cpu_to_le16((u16)if_handle);
1004 req->pmac_id = cpu_to_le32(pmac_id);
1005 req->permanent = 0;
1006 }
1007
1008 status = be_mcc_notify_wait(adapter);
1009 if (!status) {
1010 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1011
1012 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1013 }
1014
1015 err:
1016 spin_unlock_bh(&adapter->mcc_lock);
1017 return status;
1018 }
1019
1020 /* Uses synchronous MCCQ */
1021 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1022 u32 if_id, u32 *pmac_id, u32 domain)
1023 {
1024 struct be_mcc_wrb *wrb;
1025 struct be_cmd_req_pmac_add *req;
1026 int status;
1027
1028 spin_lock_bh(&adapter->mcc_lock);
1029
1030 wrb = wrb_from_mccq(adapter);
1031 if (!wrb) {
1032 status = -EBUSY;
1033 goto err;
1034 }
1035 req = embedded_payload(wrb);
1036
1037 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1038 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1039 NULL);
1040
1041 req->hdr.domain = domain;
1042 req->if_id = cpu_to_le32(if_id);
1043 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1044
1045 status = be_mcc_notify_wait(adapter);
1046 if (!status) {
1047 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1048
1049 *pmac_id = le32_to_cpu(resp->pmac_id);
1050 }
1051
1052 err:
1053 spin_unlock_bh(&adapter->mcc_lock);
1054
1055 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1056 status = -EPERM;
1057
1058 return status;
1059 }
1060
1061 /* Uses synchronous MCCQ */
1062 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1063 {
1064 struct be_mcc_wrb *wrb;
1065 struct be_cmd_req_pmac_del *req;
1066 int status;
1067
1068 if (pmac_id == -1)
1069 return 0;
1070
1071 spin_lock_bh(&adapter->mcc_lock);
1072
1073 wrb = wrb_from_mccq(adapter);
1074 if (!wrb) {
1075 status = -EBUSY;
1076 goto err;
1077 }
1078 req = embedded_payload(wrb);
1079
1080 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1081 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1082 wrb, NULL);
1083
1084 req->hdr.domain = dom;
1085 req->if_id = cpu_to_le32(if_id);
1086 req->pmac_id = cpu_to_le32(pmac_id);
1087
1088 status = be_mcc_notify_wait(adapter);
1089
1090 err:
1091 spin_unlock_bh(&adapter->mcc_lock);
1092 return status;
1093 }
1094
1095 /* Uses Mbox */
1096 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1097 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1098 {
1099 struct be_mcc_wrb *wrb;
1100 struct be_cmd_req_cq_create *req;
1101 struct be_dma_mem *q_mem = &cq->dma_mem;
1102 void *ctxt;
1103 int status;
1104
1105 if (mutex_lock_interruptible(&adapter->mbox_lock))
1106 return -1;
1107
1108 wrb = wrb_from_mbox(adapter);
1109 req = embedded_payload(wrb);
1110 ctxt = &req->context;
1111
1112 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1113 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1114 NULL);
1115
1116 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1117
1118 if (BEx_chip(adapter)) {
1119 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1120 coalesce_wm);
1121 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1122 ctxt, no_delay);
1123 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1124 __ilog2_u32(cq->len / 256));
1125 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1126 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1127 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1128 } else {
1129 req->hdr.version = 2;
1130 req->page_size = 1; /* 1 for 4K */
1131
1132 /* coalesce-wm field in this cmd is not relevant to Lancer.
1133 * Lancer uses COMMON_MODIFY_CQ to set this field
1134 */
1135 if (!lancer_chip(adapter))
1136 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1137 ctxt, coalesce_wm);
1138 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1139 no_delay);
1140 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1141 __ilog2_u32(cq->len / 256));
1142 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1143 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1144 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1145 }
1146
1147 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1148
1149 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1150
1151 status = be_mbox_notify_wait(adapter);
1152 if (!status) {
1153 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1154
1155 cq->id = le16_to_cpu(resp->cq_id);
1156 cq->created = true;
1157 }
1158
1159 mutex_unlock(&adapter->mbox_lock);
1160
1161 return status;
1162 }
1163
1164 static u32 be_encoded_q_len(int q_len)
1165 {
1166 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1167
1168 if (len_encoded == 16)
1169 len_encoded = 0;
1170 return len_encoded;
1171 }
1172
1173 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1174 struct be_queue_info *mccq,
1175 struct be_queue_info *cq)
1176 {
1177 struct be_mcc_wrb *wrb;
1178 struct be_cmd_req_mcc_ext_create *req;
1179 struct be_dma_mem *q_mem = &mccq->dma_mem;
1180 void *ctxt;
1181 int status;
1182
1183 if (mutex_lock_interruptible(&adapter->mbox_lock))
1184 return -1;
1185
1186 wrb = wrb_from_mbox(adapter);
1187 req = embedded_payload(wrb);
1188 ctxt = &req->context;
1189
1190 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1191 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1192 NULL);
1193
1194 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1195 if (BEx_chip(adapter)) {
1196 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1197 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1198 be_encoded_q_len(mccq->len));
1199 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1200 } else {
1201 req->hdr.version = 1;
1202 req->cq_id = cpu_to_le16(cq->id);
1203
1204 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1205 be_encoded_q_len(mccq->len));
1206 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1207 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1208 ctxt, cq->id);
1209 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1210 ctxt, 1);
1211 }
1212
1213 /* Subscribe to Link State, Sliport Event and Group 5 Events
1214 * (bits 1, 5 and 17 set)
1215 */
1216 req->async_event_bitmap[0] =
1217 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1218 BIT(ASYNC_EVENT_CODE_GRP_5) |
1219 BIT(ASYNC_EVENT_CODE_QNQ) |
1220 BIT(ASYNC_EVENT_CODE_SLIPORT));
1221
1222 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1223
1224 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1225
1226 status = be_mbox_notify_wait(adapter);
1227 if (!status) {
1228 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1229
1230 mccq->id = le16_to_cpu(resp->id);
1231 mccq->created = true;
1232 }
1233 mutex_unlock(&adapter->mbox_lock);
1234
1235 return status;
1236 }
1237
1238 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1239 struct be_queue_info *mccq,
1240 struct be_queue_info *cq)
1241 {
1242 struct be_mcc_wrb *wrb;
1243 struct be_cmd_req_mcc_create *req;
1244 struct be_dma_mem *q_mem = &mccq->dma_mem;
1245 void *ctxt;
1246 int status;
1247
1248 if (mutex_lock_interruptible(&adapter->mbox_lock))
1249 return -1;
1250
1251 wrb = wrb_from_mbox(adapter);
1252 req = embedded_payload(wrb);
1253 ctxt = &req->context;
1254
1255 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1256 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1257 NULL);
1258
1259 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1260
1261 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1262 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1263 be_encoded_q_len(mccq->len));
1264 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1265
1266 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1267
1268 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1269
1270 status = be_mbox_notify_wait(adapter);
1271 if (!status) {
1272 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1273
1274 mccq->id = le16_to_cpu(resp->id);
1275 mccq->created = true;
1276 }
1277
1278 mutex_unlock(&adapter->mbox_lock);
1279 return status;
1280 }
1281
1282 int be_cmd_mccq_create(struct be_adapter *adapter,
1283 struct be_queue_info *mccq, struct be_queue_info *cq)
1284 {
1285 int status;
1286
1287 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1288 if (status && BEx_chip(adapter)) {
1289 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1290 "or newer to avoid conflicting priorities between NIC "
1291 "and FCoE traffic");
1292 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1293 }
1294 return status;
1295 }
1296
1297 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1298 {
1299 struct be_mcc_wrb wrb = {0};
1300 struct be_cmd_req_eth_tx_create *req;
1301 struct be_queue_info *txq = &txo->q;
1302 struct be_queue_info *cq = &txo->cq;
1303 struct be_dma_mem *q_mem = &txq->dma_mem;
1304 int status, ver = 0;
1305
1306 req = embedded_payload(&wrb);
1307 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1308 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1309
1310 if (lancer_chip(adapter)) {
1311 req->hdr.version = 1;
1312 } else if (BEx_chip(adapter)) {
1313 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1314 req->hdr.version = 2;
1315 } else { /* For SH */
1316 req->hdr.version = 2;
1317 }
1318
1319 if (req->hdr.version > 0)
1320 req->if_id = cpu_to_le16(adapter->if_handle);
1321 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1322 req->ulp_num = BE_ULP1_NUM;
1323 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1324 req->cq_id = cpu_to_le16(cq->id);
1325 req->queue_size = be_encoded_q_len(txq->len);
1326 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1327 ver = req->hdr.version;
1328
1329 status = be_cmd_notify_wait(adapter, &wrb);
1330 if (!status) {
1331 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1332
1333 txq->id = le16_to_cpu(resp->cid);
1334 if (ver == 2)
1335 txo->db_offset = le32_to_cpu(resp->db_offset);
1336 else
1337 txo->db_offset = DB_TXULP1_OFFSET;
1338 txq->created = true;
1339 }
1340
1341 return status;
1342 }
1343
1344 /* Uses MCC */
1345 int be_cmd_rxq_create(struct be_adapter *adapter,
1346 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1347 u32 if_id, u32 rss, u8 *rss_id)
1348 {
1349 struct be_mcc_wrb *wrb;
1350 struct be_cmd_req_eth_rx_create *req;
1351 struct be_dma_mem *q_mem = &rxq->dma_mem;
1352 int status;
1353
1354 spin_lock_bh(&adapter->mcc_lock);
1355
1356 wrb = wrb_from_mccq(adapter);
1357 if (!wrb) {
1358 status = -EBUSY;
1359 goto err;
1360 }
1361 req = embedded_payload(wrb);
1362
1363 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1364 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1365
1366 req->cq_id = cpu_to_le16(cq_id);
1367 req->frag_size = fls(frag_size) - 1;
1368 req->num_pages = 2;
1369 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1370 req->interface_id = cpu_to_le32(if_id);
1371 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1372 req->rss_queue = cpu_to_le32(rss);
1373
1374 status = be_mcc_notify_wait(adapter);
1375 if (!status) {
1376 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1377
1378 rxq->id = le16_to_cpu(resp->id);
1379 rxq->created = true;
1380 *rss_id = resp->rss_id;
1381 }
1382
1383 err:
1384 spin_unlock_bh(&adapter->mcc_lock);
1385 return status;
1386 }
1387
1388 /* Generic destroyer function for all types of queues
1389 * Uses Mbox
1390 */
1391 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1392 int queue_type)
1393 {
1394 struct be_mcc_wrb *wrb;
1395 struct be_cmd_req_q_destroy *req;
1396 u8 subsys = 0, opcode = 0;
1397 int status;
1398
1399 if (mutex_lock_interruptible(&adapter->mbox_lock))
1400 return -1;
1401
1402 wrb = wrb_from_mbox(adapter);
1403 req = embedded_payload(wrb);
1404
1405 switch (queue_type) {
1406 case QTYPE_EQ:
1407 subsys = CMD_SUBSYSTEM_COMMON;
1408 opcode = OPCODE_COMMON_EQ_DESTROY;
1409 break;
1410 case QTYPE_CQ:
1411 subsys = CMD_SUBSYSTEM_COMMON;
1412 opcode = OPCODE_COMMON_CQ_DESTROY;
1413 break;
1414 case QTYPE_TXQ:
1415 subsys = CMD_SUBSYSTEM_ETH;
1416 opcode = OPCODE_ETH_TX_DESTROY;
1417 break;
1418 case QTYPE_RXQ:
1419 subsys = CMD_SUBSYSTEM_ETH;
1420 opcode = OPCODE_ETH_RX_DESTROY;
1421 break;
1422 case QTYPE_MCCQ:
1423 subsys = CMD_SUBSYSTEM_COMMON;
1424 opcode = OPCODE_COMMON_MCC_DESTROY;
1425 break;
1426 default:
1427 BUG();
1428 }
1429
1430 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1431 NULL);
1432 req->id = cpu_to_le16(q->id);
1433
1434 status = be_mbox_notify_wait(adapter);
1435 q->created = false;
1436
1437 mutex_unlock(&adapter->mbox_lock);
1438 return status;
1439 }
1440
1441 /* Uses MCC */
1442 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1443 {
1444 struct be_mcc_wrb *wrb;
1445 struct be_cmd_req_q_destroy *req;
1446 int status;
1447
1448 spin_lock_bh(&adapter->mcc_lock);
1449
1450 wrb = wrb_from_mccq(adapter);
1451 if (!wrb) {
1452 status = -EBUSY;
1453 goto err;
1454 }
1455 req = embedded_payload(wrb);
1456
1457 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1458 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1459 req->id = cpu_to_le16(q->id);
1460
1461 status = be_mcc_notify_wait(adapter);
1462 q->created = false;
1463
1464 err:
1465 spin_unlock_bh(&adapter->mcc_lock);
1466 return status;
1467 }
1468
1469 /* Create an rx filtering policy configuration on an i/f
1470 * Will use MBOX only if MCCQ has not been created.
1471 */
1472 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1473 u32 *if_handle, u32 domain)
1474 {
1475 struct be_mcc_wrb wrb = {0};
1476 struct be_cmd_req_if_create *req;
1477 int status;
1478
1479 req = embedded_payload(&wrb);
1480 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1481 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1482 sizeof(*req), &wrb, NULL);
1483 req->hdr.domain = domain;
1484 req->capability_flags = cpu_to_le32(cap_flags);
1485 req->enable_flags = cpu_to_le32(en_flags);
1486 req->pmac_invalid = true;
1487
1488 status = be_cmd_notify_wait(adapter, &wrb);
1489 if (!status) {
1490 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1491
1492 *if_handle = le32_to_cpu(resp->interface_id);
1493
1494 /* Hack to retrieve VF's pmac-id on BE3 */
1495 if (BE3_chip(adapter) && be_virtfn(adapter))
1496 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1497 }
1498 return status;
1499 }
1500
1501 /* Uses MCCQ */
1502 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1503 {
1504 struct be_mcc_wrb *wrb;
1505 struct be_cmd_req_if_destroy *req;
1506 int status;
1507
1508 if (interface_id == -1)
1509 return 0;
1510
1511 spin_lock_bh(&adapter->mcc_lock);
1512
1513 wrb = wrb_from_mccq(adapter);
1514 if (!wrb) {
1515 status = -EBUSY;
1516 goto err;
1517 }
1518 req = embedded_payload(wrb);
1519
1520 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1521 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1522 sizeof(*req), wrb, NULL);
1523 req->hdr.domain = domain;
1524 req->interface_id = cpu_to_le32(interface_id);
1525
1526 status = be_mcc_notify_wait(adapter);
1527 err:
1528 spin_unlock_bh(&adapter->mcc_lock);
1529 return status;
1530 }
1531
1532 /* Get stats is a non embedded command: the request is not embedded inside
1533 * WRB but is a separate dma memory block
1534 * Uses asynchronous MCC
1535 */
1536 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1537 {
1538 struct be_mcc_wrb *wrb;
1539 struct be_cmd_req_hdr *hdr;
1540 int status = 0;
1541
1542 spin_lock_bh(&adapter->mcc_lock);
1543
1544 wrb = wrb_from_mccq(adapter);
1545 if (!wrb) {
1546 status = -EBUSY;
1547 goto err;
1548 }
1549 hdr = nonemb_cmd->va;
1550
1551 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1552 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1553 nonemb_cmd);
1554
1555 /* version 1 of the cmd is not supported only by BE2 */
1556 if (BE2_chip(adapter))
1557 hdr->version = 0;
1558 if (BE3_chip(adapter) || lancer_chip(adapter))
1559 hdr->version = 1;
1560 else
1561 hdr->version = 2;
1562
1563 status = be_mcc_notify(adapter);
1564 if (status)
1565 goto err;
1566
1567 adapter->stats_cmd_sent = true;
1568
1569 err:
1570 spin_unlock_bh(&adapter->mcc_lock);
1571 return status;
1572 }
1573
1574 /* Lancer Stats */
1575 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1576 struct be_dma_mem *nonemb_cmd)
1577 {
1578 struct be_mcc_wrb *wrb;
1579 struct lancer_cmd_req_pport_stats *req;
1580 int status = 0;
1581
1582 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1583 CMD_SUBSYSTEM_ETH))
1584 return -EPERM;
1585
1586 spin_lock_bh(&adapter->mcc_lock);
1587
1588 wrb = wrb_from_mccq(adapter);
1589 if (!wrb) {
1590 status = -EBUSY;
1591 goto err;
1592 }
1593 req = nonemb_cmd->va;
1594
1595 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1596 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1597 wrb, nonemb_cmd);
1598
1599 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1600 req->cmd_params.params.reset_stats = 0;
1601
1602 status = be_mcc_notify(adapter);
1603 if (status)
1604 goto err;
1605
1606 adapter->stats_cmd_sent = true;
1607
1608 err:
1609 spin_unlock_bh(&adapter->mcc_lock);
1610 return status;
1611 }
1612
1613 static int be_mac_to_link_speed(int mac_speed)
1614 {
1615 switch (mac_speed) {
1616 case PHY_LINK_SPEED_ZERO:
1617 return 0;
1618 case PHY_LINK_SPEED_10MBPS:
1619 return 10;
1620 case PHY_LINK_SPEED_100MBPS:
1621 return 100;
1622 case PHY_LINK_SPEED_1GBPS:
1623 return 1000;
1624 case PHY_LINK_SPEED_10GBPS:
1625 return 10000;
1626 case PHY_LINK_SPEED_20GBPS:
1627 return 20000;
1628 case PHY_LINK_SPEED_25GBPS:
1629 return 25000;
1630 case PHY_LINK_SPEED_40GBPS:
1631 return 40000;
1632 }
1633 return 0;
1634 }
1635
1636 /* Uses synchronous mcc
1637 * Returns link_speed in Mbps
1638 */
1639 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1640 u8 *link_status, u32 dom)
1641 {
1642 struct be_mcc_wrb *wrb;
1643 struct be_cmd_req_link_status *req;
1644 int status;
1645
1646 spin_lock_bh(&adapter->mcc_lock);
1647
1648 if (link_status)
1649 *link_status = LINK_DOWN;
1650
1651 wrb = wrb_from_mccq(adapter);
1652 if (!wrb) {
1653 status = -EBUSY;
1654 goto err;
1655 }
1656 req = embedded_payload(wrb);
1657
1658 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1659 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1660 sizeof(*req), wrb, NULL);
1661
1662 /* version 1 of the cmd is not supported only by BE2 */
1663 if (!BE2_chip(adapter))
1664 req->hdr.version = 1;
1665
1666 req->hdr.domain = dom;
1667
1668 status = be_mcc_notify_wait(adapter);
1669 if (!status) {
1670 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1671
1672 if (link_speed) {
1673 *link_speed = resp->link_speed ?
1674 le16_to_cpu(resp->link_speed) * 10 :
1675 be_mac_to_link_speed(resp->mac_speed);
1676
1677 if (!resp->logical_link_status)
1678 *link_speed = 0;
1679 }
1680 if (link_status)
1681 *link_status = resp->logical_link_status;
1682 }
1683
1684 err:
1685 spin_unlock_bh(&adapter->mcc_lock);
1686 return status;
1687 }
1688
1689 /* Uses synchronous mcc */
1690 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1691 {
1692 struct be_mcc_wrb *wrb;
1693 struct be_cmd_req_get_cntl_addnl_attribs *req;
1694 int status = 0;
1695
1696 spin_lock_bh(&adapter->mcc_lock);
1697
1698 wrb = wrb_from_mccq(adapter);
1699 if (!wrb) {
1700 status = -EBUSY;
1701 goto err;
1702 }
1703 req = embedded_payload(wrb);
1704
1705 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1706 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1707 sizeof(*req), wrb, NULL);
1708
1709 status = be_mcc_notify(adapter);
1710 err:
1711 spin_unlock_bh(&adapter->mcc_lock);
1712 return status;
1713 }
1714
1715 /* Uses synchronous mcc */
1716 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1717 {
1718 struct be_mcc_wrb *wrb;
1719 struct be_cmd_req_get_fat *req;
1720 int status;
1721
1722 spin_lock_bh(&adapter->mcc_lock);
1723
1724 wrb = wrb_from_mccq(adapter);
1725 if (!wrb) {
1726 status = -EBUSY;
1727 goto err;
1728 }
1729 req = embedded_payload(wrb);
1730
1731 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1732 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1733 NULL);
1734 req->fat_operation = cpu_to_le32(QUERY_FAT);
1735 status = be_mcc_notify_wait(adapter);
1736 if (!status) {
1737 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1738
1739 if (log_size && resp->log_size)
1740 *log_size = le32_to_cpu(resp->log_size) -
1741 sizeof(u32);
1742 }
1743 err:
1744 spin_unlock_bh(&adapter->mcc_lock);
1745 return status;
1746 }
1747
1748 int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1749 {
1750 struct be_dma_mem get_fat_cmd;
1751 struct be_mcc_wrb *wrb;
1752 struct be_cmd_req_get_fat *req;
1753 u32 offset = 0, total_size, buf_size,
1754 log_offset = sizeof(u32), payload_len;
1755 int status = 0;
1756
1757 if (buf_len == 0)
1758 return -EIO;
1759
1760 total_size = buf_len;
1761
1762 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1763 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1764 get_fat_cmd.size,
1765 &get_fat_cmd.dma, GFP_ATOMIC);
1766 if (!get_fat_cmd.va) {
1767 dev_err(&adapter->pdev->dev,
1768 "Memory allocation failure while reading FAT data\n");
1769 return -ENOMEM;
1770 }
1771
1772 spin_lock_bh(&adapter->mcc_lock);
1773
1774 while (total_size) {
1775 buf_size = min(total_size, (u32)60*1024);
1776 total_size -= buf_size;
1777
1778 wrb = wrb_from_mccq(adapter);
1779 if (!wrb) {
1780 status = -EBUSY;
1781 goto err;
1782 }
1783 req = get_fat_cmd.va;
1784
1785 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1786 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1787 OPCODE_COMMON_MANAGE_FAT, payload_len,
1788 wrb, &get_fat_cmd);
1789
1790 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1791 req->read_log_offset = cpu_to_le32(log_offset);
1792 req->read_log_length = cpu_to_le32(buf_size);
1793 req->data_buffer_size = cpu_to_le32(buf_size);
1794
1795 status = be_mcc_notify_wait(adapter);
1796 if (!status) {
1797 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1798
1799 memcpy(buf + offset,
1800 resp->data_buffer,
1801 le32_to_cpu(resp->read_log_length));
1802 } else {
1803 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1804 goto err;
1805 }
1806 offset += buf_size;
1807 log_offset += buf_size;
1808 }
1809 err:
1810 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1811 get_fat_cmd.va, get_fat_cmd.dma);
1812 spin_unlock_bh(&adapter->mcc_lock);
1813 return status;
1814 }
1815
1816 /* Uses synchronous mcc */
1817 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1818 {
1819 struct be_mcc_wrb *wrb;
1820 struct be_cmd_req_get_fw_version *req;
1821 int status;
1822
1823 spin_lock_bh(&adapter->mcc_lock);
1824
1825 wrb = wrb_from_mccq(adapter);
1826 if (!wrb) {
1827 status = -EBUSY;
1828 goto err;
1829 }
1830
1831 req = embedded_payload(wrb);
1832
1833 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1834 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1835 NULL);
1836 status = be_mcc_notify_wait(adapter);
1837 if (!status) {
1838 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1839
1840 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1841 sizeof(adapter->fw_ver));
1842 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1843 sizeof(adapter->fw_on_flash));
1844 }
1845 err:
1846 spin_unlock_bh(&adapter->mcc_lock);
1847 return status;
1848 }
1849
1850 /* set the EQ delay interval of an EQ to specified value
1851 * Uses async mcc
1852 */
1853 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1854 struct be_set_eqd *set_eqd, int num)
1855 {
1856 struct be_mcc_wrb *wrb;
1857 struct be_cmd_req_modify_eq_delay *req;
1858 int status = 0, i;
1859
1860 spin_lock_bh(&adapter->mcc_lock);
1861
1862 wrb = wrb_from_mccq(adapter);
1863 if (!wrb) {
1864 status = -EBUSY;
1865 goto err;
1866 }
1867 req = embedded_payload(wrb);
1868
1869 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1870 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1871 NULL);
1872
1873 req->num_eq = cpu_to_le32(num);
1874 for (i = 0; i < num; i++) {
1875 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1876 req->set_eqd[i].phase = 0;
1877 req->set_eqd[i].delay_multiplier =
1878 cpu_to_le32(set_eqd[i].delay_multiplier);
1879 }
1880
1881 status = be_mcc_notify(adapter);
1882 err:
1883 spin_unlock_bh(&adapter->mcc_lock);
1884 return status;
1885 }
1886
1887 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1888 int num)
1889 {
1890 int num_eqs, i = 0;
1891
1892 while (num) {
1893 num_eqs = min(num, 8);
1894 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1895 i += num_eqs;
1896 num -= num_eqs;
1897 }
1898
1899 return 0;
1900 }
1901
1902 /* Uses sycnhronous mcc */
1903 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1904 u32 num, u32 domain)
1905 {
1906 struct be_mcc_wrb *wrb;
1907 struct be_cmd_req_vlan_config *req;
1908 int status;
1909
1910 spin_lock_bh(&adapter->mcc_lock);
1911
1912 wrb = wrb_from_mccq(adapter);
1913 if (!wrb) {
1914 status = -EBUSY;
1915 goto err;
1916 }
1917 req = embedded_payload(wrb);
1918
1919 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1920 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1921 wrb, NULL);
1922 req->hdr.domain = domain;
1923
1924 req->interface_id = if_id;
1925 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1926 req->num_vlan = num;
1927 memcpy(req->normal_vlan, vtag_array,
1928 req->num_vlan * sizeof(vtag_array[0]));
1929
1930 status = be_mcc_notify_wait(adapter);
1931 err:
1932 spin_unlock_bh(&adapter->mcc_lock);
1933 return status;
1934 }
1935
1936 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1937 {
1938 struct be_mcc_wrb *wrb;
1939 struct be_dma_mem *mem = &adapter->rx_filter;
1940 struct be_cmd_req_rx_filter *req = mem->va;
1941 int status;
1942
1943 spin_lock_bh(&adapter->mcc_lock);
1944
1945 wrb = wrb_from_mccq(adapter);
1946 if (!wrb) {
1947 status = -EBUSY;
1948 goto err;
1949 }
1950 memset(req, 0, sizeof(*req));
1951 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1952 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1953 wrb, mem);
1954
1955 req->if_id = cpu_to_le32(adapter->if_handle);
1956 req->if_flags_mask = cpu_to_le32(flags);
1957 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1958
1959 if (flags & BE_IF_FLAGS_MULTICAST) {
1960 struct netdev_hw_addr *ha;
1961 int i = 0;
1962
1963 /* Reset mcast promisc mode if already set by setting mask
1964 * and not setting flags field
1965 */
1966 req->if_flags_mask |=
1967 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1968 be_if_cap_flags(adapter));
1969 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1970 netdev_for_each_mc_addr(ha, adapter->netdev)
1971 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1972 }
1973
1974 status = be_mcc_notify_wait(adapter);
1975 err:
1976 spin_unlock_bh(&adapter->mcc_lock);
1977 return status;
1978 }
1979
1980 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1981 {
1982 struct device *dev = &adapter->pdev->dev;
1983
1984 if ((flags & be_if_cap_flags(adapter)) != flags) {
1985 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1986 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1987 be_if_cap_flags(adapter));
1988 }
1989 flags &= be_if_cap_flags(adapter);
1990 if (!flags)
1991 return -ENOTSUPP;
1992
1993 return __be_cmd_rx_filter(adapter, flags, value);
1994 }
1995
1996 /* Uses synchrounous mcc */
1997 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1998 {
1999 struct be_mcc_wrb *wrb;
2000 struct be_cmd_req_set_flow_control *req;
2001 int status;
2002
2003 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2004 CMD_SUBSYSTEM_COMMON))
2005 return -EPERM;
2006
2007 spin_lock_bh(&adapter->mcc_lock);
2008
2009 wrb = wrb_from_mccq(adapter);
2010 if (!wrb) {
2011 status = -EBUSY;
2012 goto err;
2013 }
2014 req = embedded_payload(wrb);
2015
2016 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2017 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2018 wrb, NULL);
2019
2020 req->hdr.version = 1;
2021 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2022 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2023
2024 status = be_mcc_notify_wait(adapter);
2025
2026 err:
2027 spin_unlock_bh(&adapter->mcc_lock);
2028
2029 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2030 return -EOPNOTSUPP;
2031
2032 return status;
2033 }
2034
2035 /* Uses sycn mcc */
2036 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2037 {
2038 struct be_mcc_wrb *wrb;
2039 struct be_cmd_req_get_flow_control *req;
2040 int status;
2041
2042 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2043 CMD_SUBSYSTEM_COMMON))
2044 return -EPERM;
2045
2046 spin_lock_bh(&adapter->mcc_lock);
2047
2048 wrb = wrb_from_mccq(adapter);
2049 if (!wrb) {
2050 status = -EBUSY;
2051 goto err;
2052 }
2053 req = embedded_payload(wrb);
2054
2055 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2056 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2057 wrb, NULL);
2058
2059 status = be_mcc_notify_wait(adapter);
2060 if (!status) {
2061 struct be_cmd_resp_get_flow_control *resp =
2062 embedded_payload(wrb);
2063
2064 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2065 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2066 }
2067
2068 err:
2069 spin_unlock_bh(&adapter->mcc_lock);
2070 return status;
2071 }
2072
2073 /* Uses mbox */
2074 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2075 {
2076 struct be_mcc_wrb *wrb;
2077 struct be_cmd_req_query_fw_cfg *req;
2078 int status;
2079
2080 if (mutex_lock_interruptible(&adapter->mbox_lock))
2081 return -1;
2082
2083 wrb = wrb_from_mbox(adapter);
2084 req = embedded_payload(wrb);
2085
2086 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2087 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2088 sizeof(*req), wrb, NULL);
2089
2090 status = be_mbox_notify_wait(adapter);
2091 if (!status) {
2092 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2093
2094 adapter->port_num = le32_to_cpu(resp->phys_port);
2095 adapter->function_mode = le32_to_cpu(resp->function_mode);
2096 adapter->function_caps = le32_to_cpu(resp->function_caps);
2097 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2098 dev_info(&adapter->pdev->dev,
2099 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2100 adapter->function_mode, adapter->function_caps);
2101 }
2102
2103 mutex_unlock(&adapter->mbox_lock);
2104 return status;
2105 }
2106
2107 /* Uses mbox */
2108 int be_cmd_reset_function(struct be_adapter *adapter)
2109 {
2110 struct be_mcc_wrb *wrb;
2111 struct be_cmd_req_hdr *req;
2112 int status;
2113
2114 if (lancer_chip(adapter)) {
2115 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2116 adapter->db + SLIPORT_CONTROL_OFFSET);
2117 status = lancer_wait_ready(adapter);
2118 if (status)
2119 dev_err(&adapter->pdev->dev,
2120 "Adapter in non recoverable error\n");
2121 return status;
2122 }
2123
2124 if (mutex_lock_interruptible(&adapter->mbox_lock))
2125 return -1;
2126
2127 wrb = wrb_from_mbox(adapter);
2128 req = embedded_payload(wrb);
2129
2130 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2131 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2132 NULL);
2133
2134 status = be_mbox_notify_wait(adapter);
2135
2136 mutex_unlock(&adapter->mbox_lock);
2137 return status;
2138 }
2139
2140 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2141 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2142 {
2143 struct be_mcc_wrb *wrb;
2144 struct be_cmd_req_rss_config *req;
2145 int status;
2146
2147 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2148 return 0;
2149
2150 spin_lock_bh(&adapter->mcc_lock);
2151
2152 wrb = wrb_from_mccq(adapter);
2153 if (!wrb) {
2154 status = -EBUSY;
2155 goto err;
2156 }
2157 req = embedded_payload(wrb);
2158
2159 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2160 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2161
2162 req->if_id = cpu_to_le32(adapter->if_handle);
2163 req->enable_rss = cpu_to_le16(rss_hash_opts);
2164 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2165
2166 if (!BEx_chip(adapter))
2167 req->hdr.version = 1;
2168
2169 memcpy(req->cpu_table, rsstable, table_size);
2170 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2171 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2172
2173 status = be_mcc_notify_wait(adapter);
2174 err:
2175 spin_unlock_bh(&adapter->mcc_lock);
2176 return status;
2177 }
2178
2179 /* Uses sync mcc */
2180 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2181 u8 bcn, u8 sts, u8 state)
2182 {
2183 struct be_mcc_wrb *wrb;
2184 struct be_cmd_req_enable_disable_beacon *req;
2185 int status;
2186
2187 spin_lock_bh(&adapter->mcc_lock);
2188
2189 wrb = wrb_from_mccq(adapter);
2190 if (!wrb) {
2191 status = -EBUSY;
2192 goto err;
2193 }
2194 req = embedded_payload(wrb);
2195
2196 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2197 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2198 sizeof(*req), wrb, NULL);
2199
2200 req->port_num = port_num;
2201 req->beacon_state = state;
2202 req->beacon_duration = bcn;
2203 req->status_duration = sts;
2204
2205 status = be_mcc_notify_wait(adapter);
2206
2207 err:
2208 spin_unlock_bh(&adapter->mcc_lock);
2209 return status;
2210 }
2211
2212 /* Uses sync mcc */
2213 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2214 {
2215 struct be_mcc_wrb *wrb;
2216 struct be_cmd_req_get_beacon_state *req;
2217 int status;
2218
2219 spin_lock_bh(&adapter->mcc_lock);
2220
2221 wrb = wrb_from_mccq(adapter);
2222 if (!wrb) {
2223 status = -EBUSY;
2224 goto err;
2225 }
2226 req = embedded_payload(wrb);
2227
2228 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2229 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2230 wrb, NULL);
2231
2232 req->port_num = port_num;
2233
2234 status = be_mcc_notify_wait(adapter);
2235 if (!status) {
2236 struct be_cmd_resp_get_beacon_state *resp =
2237 embedded_payload(wrb);
2238
2239 *state = resp->beacon_state;
2240 }
2241
2242 err:
2243 spin_unlock_bh(&adapter->mcc_lock);
2244 return status;
2245 }
2246
2247 /* Uses sync mcc */
2248 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2249 u8 page_num, u8 *data)
2250 {
2251 struct be_dma_mem cmd;
2252 struct be_mcc_wrb *wrb;
2253 struct be_cmd_req_port_type *req;
2254 int status;
2255
2256 if (page_num > TR_PAGE_A2)
2257 return -EINVAL;
2258
2259 cmd.size = sizeof(struct be_cmd_resp_port_type);
2260 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2261 GFP_ATOMIC);
2262 if (!cmd.va) {
2263 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2264 return -ENOMEM;
2265 }
2266
2267 spin_lock_bh(&adapter->mcc_lock);
2268
2269 wrb = wrb_from_mccq(adapter);
2270 if (!wrb) {
2271 status = -EBUSY;
2272 goto err;
2273 }
2274 req = cmd.va;
2275
2276 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2277 OPCODE_COMMON_READ_TRANSRECV_DATA,
2278 cmd.size, wrb, &cmd);
2279
2280 req->port = cpu_to_le32(adapter->hba_port_num);
2281 req->page_num = cpu_to_le32(page_num);
2282 status = be_mcc_notify_wait(adapter);
2283 if (!status) {
2284 struct be_cmd_resp_port_type *resp = cmd.va;
2285
2286 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2287 }
2288 err:
2289 spin_unlock_bh(&adapter->mcc_lock);
2290 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2291 return status;
2292 }
2293
2294 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2295 u32 data_size, u32 data_offset,
2296 const char *obj_name, u32 *data_written,
2297 u8 *change_status, u8 *addn_status)
2298 {
2299 struct be_mcc_wrb *wrb;
2300 struct lancer_cmd_req_write_object *req;
2301 struct lancer_cmd_resp_write_object *resp;
2302 void *ctxt = NULL;
2303 int status;
2304
2305 spin_lock_bh(&adapter->mcc_lock);
2306 adapter->flash_status = 0;
2307
2308 wrb = wrb_from_mccq(adapter);
2309 if (!wrb) {
2310 status = -EBUSY;
2311 goto err_unlock;
2312 }
2313
2314 req = embedded_payload(wrb);
2315
2316 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2317 OPCODE_COMMON_WRITE_OBJECT,
2318 sizeof(struct lancer_cmd_req_write_object), wrb,
2319 NULL);
2320
2321 ctxt = &req->context;
2322 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2323 write_length, ctxt, data_size);
2324
2325 if (data_size == 0)
2326 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2327 eof, ctxt, 1);
2328 else
2329 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2330 eof, ctxt, 0);
2331
2332 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2333 req->write_offset = cpu_to_le32(data_offset);
2334 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2335 req->descriptor_count = cpu_to_le32(1);
2336 req->buf_len = cpu_to_le32(data_size);
2337 req->addr_low = cpu_to_le32((cmd->dma +
2338 sizeof(struct lancer_cmd_req_write_object))
2339 & 0xFFFFFFFF);
2340 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2341 sizeof(struct lancer_cmd_req_write_object)));
2342
2343 status = be_mcc_notify(adapter);
2344 if (status)
2345 goto err_unlock;
2346
2347 spin_unlock_bh(&adapter->mcc_lock);
2348
2349 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2350 msecs_to_jiffies(60000)))
2351 status = -ETIMEDOUT;
2352 else
2353 status = adapter->flash_status;
2354
2355 resp = embedded_payload(wrb);
2356 if (!status) {
2357 *data_written = le32_to_cpu(resp->actual_write_len);
2358 *change_status = resp->change_status;
2359 } else {
2360 *addn_status = resp->additional_status;
2361 }
2362
2363 return status;
2364
2365 err_unlock:
2366 spin_unlock_bh(&adapter->mcc_lock);
2367 return status;
2368 }
2369
2370 int be_cmd_query_cable_type(struct be_adapter *adapter)
2371 {
2372 u8 page_data[PAGE_DATA_LEN];
2373 int status;
2374
2375 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2376 page_data);
2377 if (!status) {
2378 switch (adapter->phy.interface_type) {
2379 case PHY_TYPE_QSFP:
2380 adapter->phy.cable_type =
2381 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2382 break;
2383 case PHY_TYPE_SFP_PLUS_10GB:
2384 adapter->phy.cable_type =
2385 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2386 break;
2387 default:
2388 adapter->phy.cable_type = 0;
2389 break;
2390 }
2391 }
2392 return status;
2393 }
2394
2395 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2396 {
2397 u8 page_data[PAGE_DATA_LEN];
2398 int status;
2399
2400 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2401 page_data);
2402 if (!status) {
2403 strlcpy(adapter->phy.vendor_name, page_data +
2404 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2405 strlcpy(adapter->phy.vendor_pn,
2406 page_data + SFP_VENDOR_PN_OFFSET,
2407 SFP_VENDOR_NAME_LEN - 1);
2408 }
2409
2410 return status;
2411 }
2412
2413 int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2414 {
2415 struct lancer_cmd_req_delete_object *req;
2416 struct be_mcc_wrb *wrb;
2417 int status;
2418
2419 spin_lock_bh(&adapter->mcc_lock);
2420
2421 wrb = wrb_from_mccq(adapter);
2422 if (!wrb) {
2423 status = -EBUSY;
2424 goto err;
2425 }
2426
2427 req = embedded_payload(wrb);
2428
2429 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2430 OPCODE_COMMON_DELETE_OBJECT,
2431 sizeof(*req), wrb, NULL);
2432
2433 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2434
2435 status = be_mcc_notify_wait(adapter);
2436 err:
2437 spin_unlock_bh(&adapter->mcc_lock);
2438 return status;
2439 }
2440
2441 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2442 u32 data_size, u32 data_offset, const char *obj_name,
2443 u32 *data_read, u32 *eof, u8 *addn_status)
2444 {
2445 struct be_mcc_wrb *wrb;
2446 struct lancer_cmd_req_read_object *req;
2447 struct lancer_cmd_resp_read_object *resp;
2448 int status;
2449
2450 spin_lock_bh(&adapter->mcc_lock);
2451
2452 wrb = wrb_from_mccq(adapter);
2453 if (!wrb) {
2454 status = -EBUSY;
2455 goto err_unlock;
2456 }
2457
2458 req = embedded_payload(wrb);
2459
2460 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2461 OPCODE_COMMON_READ_OBJECT,
2462 sizeof(struct lancer_cmd_req_read_object), wrb,
2463 NULL);
2464
2465 req->desired_read_len = cpu_to_le32(data_size);
2466 req->read_offset = cpu_to_le32(data_offset);
2467 strcpy(req->object_name, obj_name);
2468 req->descriptor_count = cpu_to_le32(1);
2469 req->buf_len = cpu_to_le32(data_size);
2470 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2471 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2472
2473 status = be_mcc_notify_wait(adapter);
2474
2475 resp = embedded_payload(wrb);
2476 if (!status) {
2477 *data_read = le32_to_cpu(resp->actual_read_len);
2478 *eof = le32_to_cpu(resp->eof);
2479 } else {
2480 *addn_status = resp->additional_status;
2481 }
2482
2483 err_unlock:
2484 spin_unlock_bh(&adapter->mcc_lock);
2485 return status;
2486 }
2487
2488 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2489 u32 flash_type, u32 flash_opcode, u32 img_offset,
2490 u32 buf_size)
2491 {
2492 struct be_mcc_wrb *wrb;
2493 struct be_cmd_write_flashrom *req;
2494 int status;
2495
2496 spin_lock_bh(&adapter->mcc_lock);
2497 adapter->flash_status = 0;
2498
2499 wrb = wrb_from_mccq(adapter);
2500 if (!wrb) {
2501 status = -EBUSY;
2502 goto err_unlock;
2503 }
2504 req = cmd->va;
2505
2506 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2507 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2508 cmd);
2509
2510 req->params.op_type = cpu_to_le32(flash_type);
2511 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2512 req->params.offset = cpu_to_le32(img_offset);
2513
2514 req->params.op_code = cpu_to_le32(flash_opcode);
2515 req->params.data_buf_size = cpu_to_le32(buf_size);
2516
2517 status = be_mcc_notify(adapter);
2518 if (status)
2519 goto err_unlock;
2520
2521 spin_unlock_bh(&adapter->mcc_lock);
2522
2523 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2524 msecs_to_jiffies(40000)))
2525 status = -ETIMEDOUT;
2526 else
2527 status = adapter->flash_status;
2528
2529 return status;
2530
2531 err_unlock:
2532 spin_unlock_bh(&adapter->mcc_lock);
2533 return status;
2534 }
2535
2536 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2537 u16 img_optype, u32 img_offset, u32 crc_offset)
2538 {
2539 struct be_cmd_read_flash_crc *req;
2540 struct be_mcc_wrb *wrb;
2541 int status;
2542
2543 spin_lock_bh(&adapter->mcc_lock);
2544
2545 wrb = wrb_from_mccq(adapter);
2546 if (!wrb) {
2547 status = -EBUSY;
2548 goto err;
2549 }
2550 req = embedded_payload(wrb);
2551
2552 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2553 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2554 wrb, NULL);
2555
2556 req->params.op_type = cpu_to_le32(img_optype);
2557 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2558 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2559 else
2560 req->params.offset = cpu_to_le32(crc_offset);
2561
2562 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2563 req->params.data_buf_size = cpu_to_le32(0x4);
2564
2565 status = be_mcc_notify_wait(adapter);
2566 if (!status)
2567 memcpy(flashed_crc, req->crc, 4);
2568
2569 err:
2570 spin_unlock_bh(&adapter->mcc_lock);
2571 return status;
2572 }
2573
2574 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2575 struct be_dma_mem *nonemb_cmd)
2576 {
2577 struct be_mcc_wrb *wrb;
2578 struct be_cmd_req_acpi_wol_magic_config *req;
2579 int status;
2580
2581 spin_lock_bh(&adapter->mcc_lock);
2582
2583 wrb = wrb_from_mccq(adapter);
2584 if (!wrb) {
2585 status = -EBUSY;
2586 goto err;
2587 }
2588 req = nonemb_cmd->va;
2589
2590 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2591 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2592 wrb, nonemb_cmd);
2593 memcpy(req->magic_mac, mac, ETH_ALEN);
2594
2595 status = be_mcc_notify_wait(adapter);
2596
2597 err:
2598 spin_unlock_bh(&adapter->mcc_lock);
2599 return status;
2600 }
2601
2602 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2603 u8 loopback_type, u8 enable)
2604 {
2605 struct be_mcc_wrb *wrb;
2606 struct be_cmd_req_set_lmode *req;
2607 int status;
2608
2609 spin_lock_bh(&adapter->mcc_lock);
2610
2611 wrb = wrb_from_mccq(adapter);
2612 if (!wrb) {
2613 status = -EBUSY;
2614 goto err_unlock;
2615 }
2616
2617 req = embedded_payload(wrb);
2618
2619 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2620 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2621 wrb, NULL);
2622
2623 req->src_port = port_num;
2624 req->dest_port = port_num;
2625 req->loopback_type = loopback_type;
2626 req->loopback_state = enable;
2627
2628 status = be_mcc_notify(adapter);
2629 if (status)
2630 goto err_unlock;
2631
2632 spin_unlock_bh(&adapter->mcc_lock);
2633
2634 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2635 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
2636 status = -ETIMEDOUT;
2637
2638 return status;
2639
2640 err_unlock:
2641 spin_unlock_bh(&adapter->mcc_lock);
2642 return status;
2643 }
2644
2645 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2646 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2647 u64 pattern)
2648 {
2649 struct be_mcc_wrb *wrb;
2650 struct be_cmd_req_loopback_test *req;
2651 struct be_cmd_resp_loopback_test *resp;
2652 int status;
2653
2654 spin_lock_bh(&adapter->mcc_lock);
2655
2656 wrb = wrb_from_mccq(adapter);
2657 if (!wrb) {
2658 status = -EBUSY;
2659 goto err;
2660 }
2661
2662 req = embedded_payload(wrb);
2663
2664 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2665 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2666 NULL);
2667
2668 req->hdr.timeout = cpu_to_le32(15);
2669 req->pattern = cpu_to_le64(pattern);
2670 req->src_port = cpu_to_le32(port_num);
2671 req->dest_port = cpu_to_le32(port_num);
2672 req->pkt_size = cpu_to_le32(pkt_size);
2673 req->num_pkts = cpu_to_le32(num_pkts);
2674 req->loopback_type = cpu_to_le32(loopback_type);
2675
2676 status = be_mcc_notify(adapter);
2677 if (status)
2678 goto err;
2679
2680 spin_unlock_bh(&adapter->mcc_lock);
2681
2682 wait_for_completion(&adapter->et_cmd_compl);
2683 resp = embedded_payload(wrb);
2684 status = le32_to_cpu(resp->status);
2685
2686 return status;
2687 err:
2688 spin_unlock_bh(&adapter->mcc_lock);
2689 return status;
2690 }
2691
2692 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2693 u32 byte_cnt, struct be_dma_mem *cmd)
2694 {
2695 struct be_mcc_wrb *wrb;
2696 struct be_cmd_req_ddrdma_test *req;
2697 int status;
2698 int i, j = 0;
2699
2700 spin_lock_bh(&adapter->mcc_lock);
2701
2702 wrb = wrb_from_mccq(adapter);
2703 if (!wrb) {
2704 status = -EBUSY;
2705 goto err;
2706 }
2707 req = cmd->va;
2708 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2709 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2710 cmd);
2711
2712 req->pattern = cpu_to_le64(pattern);
2713 req->byte_count = cpu_to_le32(byte_cnt);
2714 for (i = 0; i < byte_cnt; i++) {
2715 req->snd_buff[i] = (u8)(pattern >> (j*8));
2716 j++;
2717 if (j > 7)
2718 j = 0;
2719 }
2720
2721 status = be_mcc_notify_wait(adapter);
2722
2723 if (!status) {
2724 struct be_cmd_resp_ddrdma_test *resp;
2725
2726 resp = cmd->va;
2727 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2728 resp->snd_err) {
2729 status = -1;
2730 }
2731 }
2732
2733 err:
2734 spin_unlock_bh(&adapter->mcc_lock);
2735 return status;
2736 }
2737
2738 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2739 struct be_dma_mem *nonemb_cmd)
2740 {
2741 struct be_mcc_wrb *wrb;
2742 struct be_cmd_req_seeprom_read *req;
2743 int status;
2744
2745 spin_lock_bh(&adapter->mcc_lock);
2746
2747 wrb = wrb_from_mccq(adapter);
2748 if (!wrb) {
2749 status = -EBUSY;
2750 goto err;
2751 }
2752 req = nonemb_cmd->va;
2753
2754 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2755 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2756 nonemb_cmd);
2757
2758 status = be_mcc_notify_wait(adapter);
2759
2760 err:
2761 spin_unlock_bh(&adapter->mcc_lock);
2762 return status;
2763 }
2764
2765 int be_cmd_get_phy_info(struct be_adapter *adapter)
2766 {
2767 struct be_mcc_wrb *wrb;
2768 struct be_cmd_req_get_phy_info *req;
2769 struct be_dma_mem cmd;
2770 int status;
2771
2772 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2773 CMD_SUBSYSTEM_COMMON))
2774 return -EPERM;
2775
2776 spin_lock_bh(&adapter->mcc_lock);
2777
2778 wrb = wrb_from_mccq(adapter);
2779 if (!wrb) {
2780 status = -EBUSY;
2781 goto err;
2782 }
2783 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2784 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2785 GFP_ATOMIC);
2786 if (!cmd.va) {
2787 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2788 status = -ENOMEM;
2789 goto err;
2790 }
2791
2792 req = cmd.va;
2793
2794 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2795 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2796 wrb, &cmd);
2797
2798 status = be_mcc_notify_wait(adapter);
2799 if (!status) {
2800 struct be_phy_info *resp_phy_info =
2801 cmd.va + sizeof(struct be_cmd_req_hdr);
2802
2803 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2804 adapter->phy.interface_type =
2805 le16_to_cpu(resp_phy_info->interface_type);
2806 adapter->phy.auto_speeds_supported =
2807 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2808 adapter->phy.fixed_speeds_supported =
2809 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2810 adapter->phy.misc_params =
2811 le32_to_cpu(resp_phy_info->misc_params);
2812
2813 if (BE2_chip(adapter)) {
2814 adapter->phy.fixed_speeds_supported =
2815 BE_SUPPORTED_SPEED_10GBPS |
2816 BE_SUPPORTED_SPEED_1GBPS;
2817 }
2818 }
2819 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2820 err:
2821 spin_unlock_bh(&adapter->mcc_lock);
2822 return status;
2823 }
2824
2825 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2826 {
2827 struct be_mcc_wrb *wrb;
2828 struct be_cmd_req_set_qos *req;
2829 int status;
2830
2831 spin_lock_bh(&adapter->mcc_lock);
2832
2833 wrb = wrb_from_mccq(adapter);
2834 if (!wrb) {
2835 status = -EBUSY;
2836 goto err;
2837 }
2838
2839 req = embedded_payload(wrb);
2840
2841 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2842 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2843
2844 req->hdr.domain = domain;
2845 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2846 req->max_bps_nic = cpu_to_le32(bps);
2847
2848 status = be_mcc_notify_wait(adapter);
2849
2850 err:
2851 spin_unlock_bh(&adapter->mcc_lock);
2852 return status;
2853 }
2854
2855 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2856 {
2857 struct be_mcc_wrb *wrb;
2858 struct be_cmd_req_cntl_attribs *req;
2859 struct be_cmd_resp_cntl_attribs *resp;
2860 int status, i;
2861 int payload_len = max(sizeof(*req), sizeof(*resp));
2862 struct mgmt_controller_attrib *attribs;
2863 struct be_dma_mem attribs_cmd;
2864 u32 *serial_num;
2865
2866 if (mutex_lock_interruptible(&adapter->mbox_lock))
2867 return -1;
2868
2869 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2870 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2871 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
2872 attribs_cmd.size,
2873 &attribs_cmd.dma, GFP_ATOMIC);
2874 if (!attribs_cmd.va) {
2875 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
2876 status = -ENOMEM;
2877 goto err;
2878 }
2879
2880 wrb = wrb_from_mbox(adapter);
2881 if (!wrb) {
2882 status = -EBUSY;
2883 goto err;
2884 }
2885 req = attribs_cmd.va;
2886
2887 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2888 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2889 wrb, &attribs_cmd);
2890
2891 status = be_mbox_notify_wait(adapter);
2892 if (!status) {
2893 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2894 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2895 adapter->pci_func_num = attribs->pci_func_num;
2896 serial_num = attribs->hba_attribs.controller_serial_number;
2897 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
2898 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
2899 (BIT_MASK(16) - 1);
2900 }
2901
2902 err:
2903 mutex_unlock(&adapter->mbox_lock);
2904 if (attribs_cmd.va)
2905 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
2906 attribs_cmd.va, attribs_cmd.dma);
2907 return status;
2908 }
2909
2910 /* Uses mbox */
2911 int be_cmd_req_native_mode(struct be_adapter *adapter)
2912 {
2913 struct be_mcc_wrb *wrb;
2914 struct be_cmd_req_set_func_cap *req;
2915 int status;
2916
2917 if (mutex_lock_interruptible(&adapter->mbox_lock))
2918 return -1;
2919
2920 wrb = wrb_from_mbox(adapter);
2921 if (!wrb) {
2922 status = -EBUSY;
2923 goto err;
2924 }
2925
2926 req = embedded_payload(wrb);
2927
2928 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2929 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2930 sizeof(*req), wrb, NULL);
2931
2932 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2933 CAPABILITY_BE3_NATIVE_ERX_API);
2934 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2935
2936 status = be_mbox_notify_wait(adapter);
2937 if (!status) {
2938 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2939
2940 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2941 CAPABILITY_BE3_NATIVE_ERX_API;
2942 if (!adapter->be3_native)
2943 dev_warn(&adapter->pdev->dev,
2944 "adapter not in advanced mode\n");
2945 }
2946 err:
2947 mutex_unlock(&adapter->mbox_lock);
2948 return status;
2949 }
2950
2951 /* Get privilege(s) for a function */
2952 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2953 u32 domain)
2954 {
2955 struct be_mcc_wrb *wrb;
2956 struct be_cmd_req_get_fn_privileges *req;
2957 int status;
2958
2959 spin_lock_bh(&adapter->mcc_lock);
2960
2961 wrb = wrb_from_mccq(adapter);
2962 if (!wrb) {
2963 status = -EBUSY;
2964 goto err;
2965 }
2966
2967 req = embedded_payload(wrb);
2968
2969 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2970 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2971 wrb, NULL);
2972
2973 req->hdr.domain = domain;
2974
2975 status = be_mcc_notify_wait(adapter);
2976 if (!status) {
2977 struct be_cmd_resp_get_fn_privileges *resp =
2978 embedded_payload(wrb);
2979
2980 *privilege = le32_to_cpu(resp->privilege_mask);
2981
2982 /* In UMC mode FW does not return right privileges.
2983 * Override with correct privilege equivalent to PF.
2984 */
2985 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2986 be_physfn(adapter))
2987 *privilege = MAX_PRIVILEGES;
2988 }
2989
2990 err:
2991 spin_unlock_bh(&adapter->mcc_lock);
2992 return status;
2993 }
2994
2995 /* Set privilege(s) for a function */
2996 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2997 u32 domain)
2998 {
2999 struct be_mcc_wrb *wrb;
3000 struct be_cmd_req_set_fn_privileges *req;
3001 int status;
3002
3003 spin_lock_bh(&adapter->mcc_lock);
3004
3005 wrb = wrb_from_mccq(adapter);
3006 if (!wrb) {
3007 status = -EBUSY;
3008 goto err;
3009 }
3010
3011 req = embedded_payload(wrb);
3012 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3013 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3014 wrb, NULL);
3015 req->hdr.domain = domain;
3016 if (lancer_chip(adapter))
3017 req->privileges_lancer = cpu_to_le32(privileges);
3018 else
3019 req->privileges = cpu_to_le32(privileges);
3020
3021 status = be_mcc_notify_wait(adapter);
3022 err:
3023 spin_unlock_bh(&adapter->mcc_lock);
3024 return status;
3025 }
3026
3027 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3028 * pmac_id_valid: false => pmac_id or MAC address is requested.
3029 * If pmac_id is returned, pmac_id_valid is returned as true
3030 */
3031 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3032 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3033 u8 domain)
3034 {
3035 struct be_mcc_wrb *wrb;
3036 struct be_cmd_req_get_mac_list *req;
3037 int status;
3038 int mac_count;
3039 struct be_dma_mem get_mac_list_cmd;
3040 int i;
3041
3042 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3043 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3044 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3045 get_mac_list_cmd.size,
3046 &get_mac_list_cmd.dma,
3047 GFP_ATOMIC);
3048
3049 if (!get_mac_list_cmd.va) {
3050 dev_err(&adapter->pdev->dev,
3051 "Memory allocation failure during GET_MAC_LIST\n");
3052 return -ENOMEM;
3053 }
3054
3055 spin_lock_bh(&adapter->mcc_lock);
3056
3057 wrb = wrb_from_mccq(adapter);
3058 if (!wrb) {
3059 status = -EBUSY;
3060 goto out;
3061 }
3062
3063 req = get_mac_list_cmd.va;
3064
3065 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3066 OPCODE_COMMON_GET_MAC_LIST,
3067 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3068 req->hdr.domain = domain;
3069 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3070 if (*pmac_id_valid) {
3071 req->mac_id = cpu_to_le32(*pmac_id);
3072 req->iface_id = cpu_to_le16(if_handle);
3073 req->perm_override = 0;
3074 } else {
3075 req->perm_override = 1;
3076 }
3077
3078 status = be_mcc_notify_wait(adapter);
3079 if (!status) {
3080 struct be_cmd_resp_get_mac_list *resp =
3081 get_mac_list_cmd.va;
3082
3083 if (*pmac_id_valid) {
3084 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3085 ETH_ALEN);
3086 goto out;
3087 }
3088
3089 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3090 /* Mac list returned could contain one or more active mac_ids
3091 * or one or more true or pseudo permanent mac addresses.
3092 * If an active mac_id is present, return first active mac_id
3093 * found.
3094 */
3095 for (i = 0; i < mac_count; i++) {
3096 struct get_list_macaddr *mac_entry;
3097 u16 mac_addr_size;
3098 u32 mac_id;
3099
3100 mac_entry = &resp->macaddr_list[i];
3101 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3102 /* mac_id is a 32 bit value and mac_addr size
3103 * is 6 bytes
3104 */
3105 if (mac_addr_size == sizeof(u32)) {
3106 *pmac_id_valid = true;
3107 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3108 *pmac_id = le32_to_cpu(mac_id);
3109 goto out;
3110 }
3111 }
3112 /* If no active mac_id found, return first mac addr */
3113 *pmac_id_valid = false;
3114 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3115 ETH_ALEN);
3116 }
3117
3118 out:
3119 spin_unlock_bh(&adapter->mcc_lock);
3120 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3121 get_mac_list_cmd.va, get_mac_list_cmd.dma);
3122 return status;
3123 }
3124
3125 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3126 u8 *mac, u32 if_handle, bool active, u32 domain)
3127 {
3128 if (!active)
3129 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3130 if_handle, domain);
3131 if (BEx_chip(adapter))
3132 return be_cmd_mac_addr_query(adapter, mac, false,
3133 if_handle, curr_pmac_id);
3134 else
3135 /* Fetch the MAC address using pmac_id */
3136 return be_cmd_get_mac_from_list(adapter, mac, &active,
3137 &curr_pmac_id,
3138 if_handle, domain);
3139 }
3140
3141 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3142 {
3143 int status;
3144 bool pmac_valid = false;
3145
3146 eth_zero_addr(mac);
3147
3148 if (BEx_chip(adapter)) {
3149 if (be_physfn(adapter))
3150 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3151 0);
3152 else
3153 status = be_cmd_mac_addr_query(adapter, mac, false,
3154 adapter->if_handle, 0);
3155 } else {
3156 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3157 NULL, adapter->if_handle, 0);
3158 }
3159
3160 return status;
3161 }
3162
3163 /* Uses synchronous MCCQ */
3164 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3165 u8 mac_count, u32 domain)
3166 {
3167 struct be_mcc_wrb *wrb;
3168 struct be_cmd_req_set_mac_list *req;
3169 int status;
3170 struct be_dma_mem cmd;
3171
3172 memset(&cmd, 0, sizeof(struct be_dma_mem));
3173 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3174 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3175 GFP_KERNEL);
3176 if (!cmd.va)
3177 return -ENOMEM;
3178
3179 spin_lock_bh(&adapter->mcc_lock);
3180
3181 wrb = wrb_from_mccq(adapter);
3182 if (!wrb) {
3183 status = -EBUSY;
3184 goto err;
3185 }
3186
3187 req = cmd.va;
3188 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3189 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3190 wrb, &cmd);
3191
3192 req->hdr.domain = domain;
3193 req->mac_count = mac_count;
3194 if (mac_count)
3195 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3196
3197 status = be_mcc_notify_wait(adapter);
3198
3199 err:
3200 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3201 spin_unlock_bh(&adapter->mcc_lock);
3202 return status;
3203 }
3204
3205 /* Wrapper to delete any active MACs and provision the new mac.
3206 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3207 * current list are active.
3208 */
3209 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3210 {
3211 bool active_mac = false;
3212 u8 old_mac[ETH_ALEN];
3213 u32 pmac_id;
3214 int status;
3215
3216 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3217 &pmac_id, if_id, dom);
3218
3219 if (!status && active_mac)
3220 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3221
3222 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3223 }
3224
3225 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3226 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3227 {
3228 struct be_mcc_wrb *wrb;
3229 struct be_cmd_req_set_hsw_config *req;
3230 void *ctxt;
3231 int status;
3232
3233 spin_lock_bh(&adapter->mcc_lock);
3234
3235 wrb = wrb_from_mccq(adapter);
3236 if (!wrb) {
3237 status = -EBUSY;
3238 goto err;
3239 }
3240
3241 req = embedded_payload(wrb);
3242 ctxt = &req->context;
3243
3244 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3245 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3246 NULL);
3247
3248 req->hdr.domain = domain;
3249 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3250 if (pvid) {
3251 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3252 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3253 }
3254 if (!BEx_chip(adapter) && hsw_mode) {
3255 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3256 ctxt, adapter->hba_port_num);
3257 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3258 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3259 ctxt, hsw_mode);
3260 }
3261
3262 /* Enable/disable both mac and vlan spoof checking */
3263 if (!BEx_chip(adapter) && spoofchk) {
3264 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3265 ctxt, spoofchk);
3266 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3267 ctxt, spoofchk);
3268 }
3269
3270 be_dws_cpu_to_le(req->context, sizeof(req->context));
3271 status = be_mcc_notify_wait(adapter);
3272
3273 err:
3274 spin_unlock_bh(&adapter->mcc_lock);
3275 return status;
3276 }
3277
3278 /* Get Hyper switch config */
3279 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3280 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3281 {
3282 struct be_mcc_wrb *wrb;
3283 struct be_cmd_req_get_hsw_config *req;
3284 void *ctxt;
3285 int status;
3286 u16 vid;
3287
3288 spin_lock_bh(&adapter->mcc_lock);
3289
3290 wrb = wrb_from_mccq(adapter);
3291 if (!wrb) {
3292 status = -EBUSY;
3293 goto err;
3294 }
3295
3296 req = embedded_payload(wrb);
3297 ctxt = &req->context;
3298
3299 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3300 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3301 NULL);
3302
3303 req->hdr.domain = domain;
3304 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3305 ctxt, intf_id);
3306 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3307
3308 if (!BEx_chip(adapter) && mode) {
3309 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3310 ctxt, adapter->hba_port_num);
3311 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3312 }
3313 be_dws_cpu_to_le(req->context, sizeof(req->context));
3314
3315 status = be_mcc_notify_wait(adapter);
3316 if (!status) {
3317 struct be_cmd_resp_get_hsw_config *resp =
3318 embedded_payload(wrb);
3319
3320 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3321 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3322 pvid, &resp->context);
3323 if (pvid)
3324 *pvid = le16_to_cpu(vid);
3325 if (mode)
3326 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3327 port_fwd_type, &resp->context);
3328 if (spoofchk)
3329 *spoofchk =
3330 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3331 spoofchk, &resp->context);
3332 }
3333
3334 err:
3335 spin_unlock_bh(&adapter->mcc_lock);
3336 return status;
3337 }
3338
3339 static bool be_is_wol_excluded(struct be_adapter *adapter)
3340 {
3341 struct pci_dev *pdev = adapter->pdev;
3342
3343 if (be_virtfn(adapter))
3344 return true;
3345
3346 switch (pdev->subsystem_device) {
3347 case OC_SUBSYS_DEVICE_ID1:
3348 case OC_SUBSYS_DEVICE_ID2:
3349 case OC_SUBSYS_DEVICE_ID3:
3350 case OC_SUBSYS_DEVICE_ID4:
3351 return true;
3352 default:
3353 return false;
3354 }
3355 }
3356
3357 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3358 {
3359 struct be_mcc_wrb *wrb;
3360 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3361 int status = 0;
3362 struct be_dma_mem cmd;
3363
3364 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3365 CMD_SUBSYSTEM_ETH))
3366 return -EPERM;
3367
3368 if (be_is_wol_excluded(adapter))
3369 return status;
3370
3371 if (mutex_lock_interruptible(&adapter->mbox_lock))
3372 return -1;
3373
3374 memset(&cmd, 0, sizeof(struct be_dma_mem));
3375 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3376 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3377 GFP_ATOMIC);
3378 if (!cmd.va) {
3379 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3380 status = -ENOMEM;
3381 goto err;
3382 }
3383
3384 wrb = wrb_from_mbox(adapter);
3385 if (!wrb) {
3386 status = -EBUSY;
3387 goto err;
3388 }
3389
3390 req = cmd.va;
3391
3392 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3393 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3394 sizeof(*req), wrb, &cmd);
3395
3396 req->hdr.version = 1;
3397 req->query_options = BE_GET_WOL_CAP;
3398
3399 status = be_mbox_notify_wait(adapter);
3400 if (!status) {
3401 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3402
3403 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
3404
3405 adapter->wol_cap = resp->wol_settings;
3406 if (adapter->wol_cap & BE_WOL_CAP)
3407 adapter->wol_en = true;
3408 }
3409 err:
3410 mutex_unlock(&adapter->mbox_lock);
3411 if (cmd.va)
3412 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3413 cmd.dma);
3414 return status;
3415
3416 }
3417
3418 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3419 {
3420 struct be_dma_mem extfat_cmd;
3421 struct be_fat_conf_params *cfgs;
3422 int status;
3423 int i, j;
3424
3425 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3426 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3427 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3428 extfat_cmd.size, &extfat_cmd.dma,
3429 GFP_ATOMIC);
3430 if (!extfat_cmd.va)
3431 return -ENOMEM;
3432
3433 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3434 if (status)
3435 goto err;
3436
3437 cfgs = (struct be_fat_conf_params *)
3438 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3439 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3440 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3441
3442 for (j = 0; j < num_modes; j++) {
3443 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3444 cfgs->module[i].trace_lvl[j].dbg_lvl =
3445 cpu_to_le32(level);
3446 }
3447 }
3448
3449 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3450 err:
3451 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
3452 extfat_cmd.dma);
3453 return status;
3454 }
3455
3456 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3457 {
3458 struct be_dma_mem extfat_cmd;
3459 struct be_fat_conf_params *cfgs;
3460 int status, j;
3461 int level = 0;
3462
3463 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3464 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3465 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3466 extfat_cmd.size, &extfat_cmd.dma,
3467 GFP_ATOMIC);
3468
3469 if (!extfat_cmd.va) {
3470 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3471 __func__);
3472 goto err;
3473 }
3474
3475 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3476 if (!status) {
3477 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3478 sizeof(struct be_cmd_resp_hdr));
3479
3480 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3481 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3482 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3483 }
3484 }
3485 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
3486 extfat_cmd.dma);
3487 err:
3488 return level;
3489 }
3490
3491 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3492 struct be_dma_mem *cmd)
3493 {
3494 struct be_mcc_wrb *wrb;
3495 struct be_cmd_req_get_ext_fat_caps *req;
3496 int status;
3497
3498 if (mutex_lock_interruptible(&adapter->mbox_lock))
3499 return -1;
3500
3501 wrb = wrb_from_mbox(adapter);
3502 if (!wrb) {
3503 status = -EBUSY;
3504 goto err;
3505 }
3506
3507 req = cmd->va;
3508 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3509 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3510 cmd->size, wrb, cmd);
3511 req->parameter_type = cpu_to_le32(1);
3512
3513 status = be_mbox_notify_wait(adapter);
3514 err:
3515 mutex_unlock(&adapter->mbox_lock);
3516 return status;
3517 }
3518
3519 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3520 struct be_dma_mem *cmd,
3521 struct be_fat_conf_params *configs)
3522 {
3523 struct be_mcc_wrb *wrb;
3524 struct be_cmd_req_set_ext_fat_caps *req;
3525 int status;
3526
3527 spin_lock_bh(&adapter->mcc_lock);
3528
3529 wrb = wrb_from_mccq(adapter);
3530 if (!wrb) {
3531 status = -EBUSY;
3532 goto err;
3533 }
3534
3535 req = cmd->va;
3536 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3537 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3538 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3539 cmd->size, wrb, cmd);
3540
3541 status = be_mcc_notify_wait(adapter);
3542 err:
3543 spin_unlock_bh(&adapter->mcc_lock);
3544 return status;
3545 }
3546
3547 int be_cmd_query_port_name(struct be_adapter *adapter)
3548 {
3549 struct be_cmd_req_get_port_name *req;
3550 struct be_mcc_wrb *wrb;
3551 int status;
3552
3553 if (mutex_lock_interruptible(&adapter->mbox_lock))
3554 return -1;
3555
3556 wrb = wrb_from_mbox(adapter);
3557 req = embedded_payload(wrb);
3558
3559 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3560 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3561 NULL);
3562 if (!BEx_chip(adapter))
3563 req->hdr.version = 1;
3564
3565 status = be_mbox_notify_wait(adapter);
3566 if (!status) {
3567 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3568
3569 adapter->port_name = resp->port_name[adapter->hba_port_num];
3570 } else {
3571 adapter->port_name = adapter->hba_port_num + '0';
3572 }
3573
3574 mutex_unlock(&adapter->mbox_lock);
3575 return status;
3576 }
3577
3578 /* Descriptor type */
3579 enum {
3580 FUNC_DESC = 1,
3581 VFT_DESC = 2
3582 };
3583
3584 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3585 int desc_type)
3586 {
3587 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3588 struct be_nic_res_desc *nic;
3589 int i;
3590
3591 for (i = 0; i < desc_count; i++) {
3592 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3593 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3594 nic = (struct be_nic_res_desc *)hdr;
3595 if (desc_type == FUNC_DESC ||
3596 (desc_type == VFT_DESC &&
3597 nic->flags & (1 << VFT_SHIFT)))
3598 return nic;
3599 }
3600
3601 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3602 hdr = (void *)hdr + hdr->desc_len;
3603 }
3604 return NULL;
3605 }
3606
3607 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3608 {
3609 return be_get_nic_desc(buf, desc_count, VFT_DESC);
3610 }
3611
3612 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3613 {
3614 return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3615 }
3616
3617 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3618 u32 desc_count)
3619 {
3620 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3621 struct be_pcie_res_desc *pcie;
3622 int i;
3623
3624 for (i = 0; i < desc_count; i++) {
3625 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3626 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3627 pcie = (struct be_pcie_res_desc *)hdr;
3628 if (pcie->pf_num == devfn)
3629 return pcie;
3630 }
3631
3632 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3633 hdr = (void *)hdr + hdr->desc_len;
3634 }
3635 return NULL;
3636 }
3637
3638 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3639 {
3640 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3641 int i;
3642
3643 for (i = 0; i < desc_count; i++) {
3644 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3645 return (struct be_port_res_desc *)hdr;
3646
3647 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3648 hdr = (void *)hdr + hdr->desc_len;
3649 }
3650 return NULL;
3651 }
3652
3653 static void be_copy_nic_desc(struct be_resources *res,
3654 struct be_nic_res_desc *desc)
3655 {
3656 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3657 res->max_vlans = le16_to_cpu(desc->vlan_count);
3658 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3659 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3660 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3661 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3662 res->max_evt_qs = le16_to_cpu(desc->eq_count);
3663 res->max_cq_count = le16_to_cpu(desc->cq_count);
3664 res->max_iface_count = le16_to_cpu(desc->iface_count);
3665 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
3666 /* Clear flags that driver is not interested in */
3667 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3668 BE_IF_CAP_FLAGS_WANT;
3669 }
3670
3671 /* Uses Mbox */
3672 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3673 {
3674 struct be_mcc_wrb *wrb;
3675 struct be_cmd_req_get_func_config *req;
3676 int status;
3677 struct be_dma_mem cmd;
3678
3679 if (mutex_lock_interruptible(&adapter->mbox_lock))
3680 return -1;
3681
3682 memset(&cmd, 0, sizeof(struct be_dma_mem));
3683 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3684 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3685 GFP_ATOMIC);
3686 if (!cmd.va) {
3687 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3688 status = -ENOMEM;
3689 goto err;
3690 }
3691
3692 wrb = wrb_from_mbox(adapter);
3693 if (!wrb) {
3694 status = -EBUSY;
3695 goto err;
3696 }
3697
3698 req = cmd.va;
3699
3700 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3701 OPCODE_COMMON_GET_FUNC_CONFIG,
3702 cmd.size, wrb, &cmd);
3703
3704 if (skyhawk_chip(adapter))
3705 req->hdr.version = 1;
3706
3707 status = be_mbox_notify_wait(adapter);
3708 if (!status) {
3709 struct be_cmd_resp_get_func_config *resp = cmd.va;
3710 u32 desc_count = le32_to_cpu(resp->desc_count);
3711 struct be_nic_res_desc *desc;
3712
3713 desc = be_get_func_nic_desc(resp->func_param, desc_count);
3714 if (!desc) {
3715 status = -EINVAL;
3716 goto err;
3717 }
3718 adapter->pf_number = desc->pf_num;
3719 be_copy_nic_desc(res, desc);
3720 }
3721 err:
3722 mutex_unlock(&adapter->mbox_lock);
3723 if (cmd.va)
3724 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3725 cmd.dma);
3726 return status;
3727 }
3728
3729 /* Will use MBOX only if MCCQ has not been created
3730 * non-zero domain => a PF is querying this on behalf of a VF
3731 * zero domain => a PF or a VF is querying this for itself
3732 */
3733 int be_cmd_get_profile_config(struct be_adapter *adapter,
3734 struct be_resources *res, u8 query, u8 domain)
3735 {
3736 struct be_cmd_resp_get_profile_config *resp;
3737 struct be_cmd_req_get_profile_config *req;
3738 struct be_nic_res_desc *vf_res;
3739 struct be_pcie_res_desc *pcie;
3740 struct be_port_res_desc *port;
3741 struct be_nic_res_desc *nic;
3742 struct be_mcc_wrb wrb = {0};
3743 struct be_dma_mem cmd;
3744 u16 desc_count;
3745 int status;
3746
3747 memset(&cmd, 0, sizeof(struct be_dma_mem));
3748 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3749 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3750 GFP_ATOMIC);
3751 if (!cmd.va)
3752 return -ENOMEM;
3753
3754 req = cmd.va;
3755 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3756 OPCODE_COMMON_GET_PROFILE_CONFIG,
3757 cmd.size, &wrb, &cmd);
3758
3759 if (!lancer_chip(adapter))
3760 req->hdr.version = 1;
3761 req->type = ACTIVE_PROFILE_TYPE;
3762 /* When a function is querying profile information relating to
3763 * itself hdr.pf_number must be set to it's pci_func_num + 1
3764 */
3765 req->hdr.domain = domain;
3766 if (domain == 0)
3767 req->hdr.pf_num = adapter->pci_func_num + 1;
3768
3769 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
3770 * descriptors with all bits set to "1" for the fields which can be
3771 * modified using SET_PROFILE_CONFIG cmd.
3772 */
3773 if (query == RESOURCE_MODIFIABLE)
3774 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
3775
3776 status = be_cmd_notify_wait(adapter, &wrb);
3777 if (status)
3778 goto err;
3779
3780 resp = cmd.va;
3781 desc_count = le16_to_cpu(resp->desc_count);
3782
3783 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3784 desc_count);
3785 if (pcie)
3786 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3787
3788 port = be_get_port_desc(resp->func_param, desc_count);
3789 if (port)
3790 adapter->mc_type = port->mc_type;
3791
3792 nic = be_get_func_nic_desc(resp->func_param, desc_count);
3793 if (nic)
3794 be_copy_nic_desc(res, nic);
3795
3796 vf_res = be_get_vft_desc(resp->func_param, desc_count);
3797 if (vf_res)
3798 res->vf_if_cap_flags = vf_res->cap_flags;
3799 err:
3800 if (cmd.va)
3801 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3802 cmd.dma);
3803 return status;
3804 }
3805
3806 /* Will use MBOX only if MCCQ has not been created */
3807 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3808 int size, int count, u8 version, u8 domain)
3809 {
3810 struct be_cmd_req_set_profile_config *req;
3811 struct be_mcc_wrb wrb = {0};
3812 struct be_dma_mem cmd;
3813 int status;
3814
3815 memset(&cmd, 0, sizeof(struct be_dma_mem));
3816 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
3817 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3818 GFP_ATOMIC);
3819 if (!cmd.va)
3820 return -ENOMEM;
3821
3822 req = cmd.va;
3823 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3824 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3825 &wrb, &cmd);
3826 req->hdr.version = version;
3827 req->hdr.domain = domain;
3828 req->desc_count = cpu_to_le32(count);
3829 memcpy(req->desc, desc, size);
3830
3831 status = be_cmd_notify_wait(adapter, &wrb);
3832
3833 if (cmd.va)
3834 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
3835 cmd.dma);
3836 return status;
3837 }
3838
3839 /* Mark all fields invalid */
3840 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
3841 {
3842 memset(nic, 0, sizeof(*nic));
3843 nic->unicast_mac_count = 0xFFFF;
3844 nic->mcc_count = 0xFFFF;
3845 nic->vlan_count = 0xFFFF;
3846 nic->mcast_mac_count = 0xFFFF;
3847 nic->txq_count = 0xFFFF;
3848 nic->rq_count = 0xFFFF;
3849 nic->rssq_count = 0xFFFF;
3850 nic->lro_count = 0xFFFF;
3851 nic->cq_count = 0xFFFF;
3852 nic->toe_conn_count = 0xFFFF;
3853 nic->eq_count = 0xFFFF;
3854 nic->iface_count = 0xFFFF;
3855 nic->link_param = 0xFF;
3856 nic->channel_id_param = cpu_to_le16(0xF000);
3857 nic->acpi_params = 0xFF;
3858 nic->wol_param = 0x0F;
3859 nic->tunnel_iface_count = 0xFFFF;
3860 nic->direct_tenant_iface_count = 0xFFFF;
3861 nic->bw_min = 0xFFFFFFFF;
3862 nic->bw_max = 0xFFFFFFFF;
3863 }
3864
3865 /* Mark all fields invalid */
3866 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3867 {
3868 memset(pcie, 0, sizeof(*pcie));
3869 pcie->sriov_state = 0xFF;
3870 pcie->pf_state = 0xFF;
3871 pcie->pf_type = 0xFF;
3872 pcie->num_vfs = 0xFFFF;
3873 }
3874
3875 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3876 u8 domain)
3877 {
3878 struct be_nic_res_desc nic_desc;
3879 u32 bw_percent;
3880 u16 version = 0;
3881
3882 if (BE3_chip(adapter))
3883 return be_cmd_set_qos(adapter, max_rate / 10, domain);
3884
3885 be_reset_nic_desc(&nic_desc);
3886 nic_desc.pf_num = adapter->pf_number;
3887 nic_desc.vf_num = domain;
3888 nic_desc.bw_min = 0;
3889 if (lancer_chip(adapter)) {
3890 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3891 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3892 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3893 (1 << NOSV_SHIFT);
3894 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
3895 } else {
3896 version = 1;
3897 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3898 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3899 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3900 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3901 nic_desc.bw_max = cpu_to_le32(bw_percent);
3902 }
3903
3904 return be_cmd_set_profile_config(adapter, &nic_desc,
3905 nic_desc.hdr.desc_len,
3906 1, version, domain);
3907 }
3908
3909 static void be_fill_vf_res_template(struct be_adapter *adapter,
3910 struct be_resources pool_res,
3911 u16 num_vfs, u16 num_vf_qs,
3912 struct be_nic_res_desc *nic_vft)
3913 {
3914 u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
3915 struct be_resources res_mod = {0};
3916
3917 /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
3918 * which are modifiable using SET_PROFILE_CONFIG cmd.
3919 */
3920 be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
3921
3922 /* If RSS IFACE capability flags are modifiable for a VF, set the
3923 * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
3924 * more than 1 RSSQ is available for a VF.
3925 * Otherwise, provision only 1 queue pair for VF.
3926 */
3927 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3928 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
3929 if (num_vf_qs > 1) {
3930 vf_if_cap_flags |= BE_IF_FLAGS_RSS;
3931 if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
3932 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
3933 } else {
3934 vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
3935 BE_IF_FLAGS_DEFQ_RSS);
3936 }
3937 } else {
3938 num_vf_qs = 1;
3939 }
3940
3941 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_VLAN_PROMISCUOUS) {
3942 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
3943 vf_if_cap_flags &= ~BE_IF_FLAGS_VLAN_PROMISCUOUS;
3944 }
3945
3946 nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
3947 nic_vft->rq_count = cpu_to_le16(num_vf_qs);
3948 nic_vft->txq_count = cpu_to_le16(num_vf_qs);
3949 nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
3950 nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
3951 (num_vfs + 1));
3952
3953 /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
3954 * among the PF and it's VFs, if the fields are changeable
3955 */
3956 if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
3957 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
3958 (num_vfs + 1));
3959
3960 if (res_mod.max_vlans == FIELD_MODIFIABLE)
3961 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
3962 (num_vfs + 1));
3963
3964 if (res_mod.max_iface_count == FIELD_MODIFIABLE)
3965 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
3966 (num_vfs + 1));
3967
3968 if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
3969 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
3970 (num_vfs + 1));
3971 }
3972
3973 int be_cmd_set_sriov_config(struct be_adapter *adapter,
3974 struct be_resources pool_res, u16 num_vfs,
3975 u16 num_vf_qs)
3976 {
3977 struct {
3978 struct be_pcie_res_desc pcie;
3979 struct be_nic_res_desc nic_vft;
3980 } __packed desc;
3981
3982 /* PF PCIE descriptor */
3983 be_reset_pcie_desc(&desc.pcie);
3984 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3985 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3986 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
3987 desc.pcie.pf_num = adapter->pdev->devfn;
3988 desc.pcie.sriov_state = num_vfs ? 1 : 0;
3989 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3990
3991 /* VF NIC Template descriptor */
3992 be_reset_nic_desc(&desc.nic_vft);
3993 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3994 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3995 desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
3996 desc.nic_vft.pf_num = adapter->pdev->devfn;
3997 desc.nic_vft.vf_num = 0;
3998
3999 be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
4000 &desc.nic_vft);
4001
4002 return be_cmd_set_profile_config(adapter, &desc,
4003 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4004 }
4005
4006 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4007 {
4008 struct be_mcc_wrb *wrb;
4009 struct be_cmd_req_manage_iface_filters *req;
4010 int status;
4011
4012 if (iface == 0xFFFFFFFF)
4013 return -1;
4014
4015 spin_lock_bh(&adapter->mcc_lock);
4016
4017 wrb = wrb_from_mccq(adapter);
4018 if (!wrb) {
4019 status = -EBUSY;
4020 goto err;
4021 }
4022 req = embedded_payload(wrb);
4023
4024 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4025 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4026 wrb, NULL);
4027 req->op = op;
4028 req->target_iface_id = cpu_to_le32(iface);
4029
4030 status = be_mcc_notify_wait(adapter);
4031 err:
4032 spin_unlock_bh(&adapter->mcc_lock);
4033 return status;
4034 }
4035
4036 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4037 {
4038 struct be_port_res_desc port_desc;
4039
4040 memset(&port_desc, 0, sizeof(port_desc));
4041 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4042 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4043 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4044 port_desc.link_num = adapter->hba_port_num;
4045 if (port) {
4046 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4047 (1 << RCVID_SHIFT);
4048 port_desc.nv_port = swab16(port);
4049 } else {
4050 port_desc.nv_flags = NV_TYPE_DISABLED;
4051 port_desc.nv_port = 0;
4052 }
4053
4054 return be_cmd_set_profile_config(adapter, &port_desc,
4055 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4056 }
4057
4058 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4059 int vf_num)
4060 {
4061 struct be_mcc_wrb *wrb;
4062 struct be_cmd_req_get_iface_list *req;
4063 struct be_cmd_resp_get_iface_list *resp;
4064 int status;
4065
4066 spin_lock_bh(&adapter->mcc_lock);
4067
4068 wrb = wrb_from_mccq(adapter);
4069 if (!wrb) {
4070 status = -EBUSY;
4071 goto err;
4072 }
4073 req = embedded_payload(wrb);
4074
4075 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4076 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4077 wrb, NULL);
4078 req->hdr.domain = vf_num + 1;
4079
4080 status = be_mcc_notify_wait(adapter);
4081 if (!status) {
4082 resp = (struct be_cmd_resp_get_iface_list *)req;
4083 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4084 }
4085
4086 err:
4087 spin_unlock_bh(&adapter->mcc_lock);
4088 return status;
4089 }
4090
4091 static int lancer_wait_idle(struct be_adapter *adapter)
4092 {
4093 #define SLIPORT_IDLE_TIMEOUT 30
4094 u32 reg_val;
4095 int status = 0, i;
4096
4097 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4098 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4099 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4100 break;
4101
4102 ssleep(1);
4103 }
4104
4105 if (i == SLIPORT_IDLE_TIMEOUT)
4106 status = -1;
4107
4108 return status;
4109 }
4110
4111 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4112 {
4113 int status = 0;
4114
4115 status = lancer_wait_idle(adapter);
4116 if (status)
4117 return status;
4118
4119 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4120
4121 return status;
4122 }
4123
4124 /* Routine to check whether dump image is present or not */
4125 bool dump_present(struct be_adapter *adapter)
4126 {
4127 u32 sliport_status = 0;
4128
4129 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4130 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4131 }
4132
4133 int lancer_initiate_dump(struct be_adapter *adapter)
4134 {
4135 struct device *dev = &adapter->pdev->dev;
4136 int status;
4137
4138 if (dump_present(adapter)) {
4139 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4140 return -EEXIST;
4141 }
4142
4143 /* give firmware reset and diagnostic dump */
4144 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4145 PHYSDEV_CONTROL_DD_MASK);
4146 if (status < 0) {
4147 dev_err(dev, "FW reset failed\n");
4148 return status;
4149 }
4150
4151 status = lancer_wait_idle(adapter);
4152 if (status)
4153 return status;
4154
4155 if (!dump_present(adapter)) {
4156 dev_err(dev, "FW dump not generated\n");
4157 return -EIO;
4158 }
4159
4160 return 0;
4161 }
4162
4163 int lancer_delete_dump(struct be_adapter *adapter)
4164 {
4165 int status;
4166
4167 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4168 return be_cmd_status(status);
4169 }
4170
4171 /* Uses sync mcc */
4172 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4173 {
4174 struct be_mcc_wrb *wrb;
4175 struct be_cmd_enable_disable_vf *req;
4176 int status;
4177
4178 if (BEx_chip(adapter))
4179 return 0;
4180
4181 spin_lock_bh(&adapter->mcc_lock);
4182
4183 wrb = wrb_from_mccq(adapter);
4184 if (!wrb) {
4185 status = -EBUSY;
4186 goto err;
4187 }
4188
4189 req = embedded_payload(wrb);
4190
4191 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4192 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4193 wrb, NULL);
4194
4195 req->hdr.domain = domain;
4196 req->enable = 1;
4197 status = be_mcc_notify_wait(adapter);
4198 err:
4199 spin_unlock_bh(&adapter->mcc_lock);
4200 return status;
4201 }
4202
4203 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4204 {
4205 struct be_mcc_wrb *wrb;
4206 struct be_cmd_req_intr_set *req;
4207 int status;
4208
4209 if (mutex_lock_interruptible(&adapter->mbox_lock))
4210 return -1;
4211
4212 wrb = wrb_from_mbox(adapter);
4213
4214 req = embedded_payload(wrb);
4215
4216 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4217 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4218 wrb, NULL);
4219
4220 req->intr_enabled = intr_enable;
4221
4222 status = be_mbox_notify_wait(adapter);
4223
4224 mutex_unlock(&adapter->mbox_lock);
4225 return status;
4226 }
4227
4228 /* Uses MBOX */
4229 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4230 {
4231 struct be_cmd_req_get_active_profile *req;
4232 struct be_mcc_wrb *wrb;
4233 int status;
4234
4235 if (mutex_lock_interruptible(&adapter->mbox_lock))
4236 return -1;
4237
4238 wrb = wrb_from_mbox(adapter);
4239 if (!wrb) {
4240 status = -EBUSY;
4241 goto err;
4242 }
4243
4244 req = embedded_payload(wrb);
4245
4246 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4247 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4248 wrb, NULL);
4249
4250 status = be_mbox_notify_wait(adapter);
4251 if (!status) {
4252 struct be_cmd_resp_get_active_profile *resp =
4253 embedded_payload(wrb);
4254
4255 *profile_id = le16_to_cpu(resp->active_profile_id);
4256 }
4257
4258 err:
4259 mutex_unlock(&adapter->mbox_lock);
4260 return status;
4261 }
4262
4263 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4264 int link_state, u8 domain)
4265 {
4266 struct be_mcc_wrb *wrb;
4267 struct be_cmd_req_set_ll_link *req;
4268 int status;
4269
4270 if (BEx_chip(adapter) || lancer_chip(adapter))
4271 return -EOPNOTSUPP;
4272
4273 spin_lock_bh(&adapter->mcc_lock);
4274
4275 wrb = wrb_from_mccq(adapter);
4276 if (!wrb) {
4277 status = -EBUSY;
4278 goto err;
4279 }
4280
4281 req = embedded_payload(wrb);
4282
4283 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4284 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4285 sizeof(*req), wrb, NULL);
4286
4287 req->hdr.version = 1;
4288 req->hdr.domain = domain;
4289
4290 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4291 req->link_config |= 1;
4292
4293 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4294 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4295
4296 status = be_mcc_notify_wait(adapter);
4297 err:
4298 spin_unlock_bh(&adapter->mcc_lock);
4299 return status;
4300 }
4301
4302 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
4303 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
4304 {
4305 struct be_adapter *adapter = netdev_priv(netdev_handle);
4306 struct be_mcc_wrb *wrb;
4307 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
4308 struct be_cmd_req_hdr *req;
4309 struct be_cmd_resp_hdr *resp;
4310 int status;
4311
4312 spin_lock_bh(&adapter->mcc_lock);
4313
4314 wrb = wrb_from_mccq(adapter);
4315 if (!wrb) {
4316 status = -EBUSY;
4317 goto err;
4318 }
4319 req = embedded_payload(wrb);
4320 resp = embedded_payload(wrb);
4321
4322 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4323 hdr->opcode, wrb_payload_size, wrb, NULL);
4324 memcpy(req, wrb_payload, wrb_payload_size);
4325 be_dws_cpu_to_le(req, wrb_payload_size);
4326
4327 status = be_mcc_notify_wait(adapter);
4328 if (cmd_status)
4329 *cmd_status = (status & 0xffff);
4330 if (ext_status)
4331 *ext_status = 0;
4332 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4333 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4334 err:
4335 spin_unlock_bh(&adapter->mcc_lock);
4336 return status;
4337 }
4338 EXPORT_SYMBOL(be_roce_mcc_cmd);
Linux with added FPC-III support