drivers/gpio/gpio-xlp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2003-2015 Broadcom Corporation
   4  * All Rights Reserved
   5  */
   6
   7 #include <linux/gpio/driver.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/of_device.h>
  10 #include <linux/module.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irqchip/chained_irq.h>
  14 #include <linux/acpi.h>
  15
  16 /*
  17  * XLP GPIO has multiple 32 bit registers for each feature where each register
  18  * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
  19  * require 3 32-bit registers for each feature.
  20  * Here we only define offset of the first register for each feature. Offset of
  21  * the registers for pins greater than 32 can be calculated as following(Use
  22  * GPIO_INT_STAT as example):
  23  *
  24  * offset = (gpio / XLP_GPIO_REGSZ) * 4;
  25  * reg_addr = addr + offset;
  26  *
  27  * where addr is base address of the that feature register and gpio is the pin.
  28  */
  29 #define GPIO_OUTPUT_EN          0x00
  30 #define GPIO_PADDRV             0x08
  31 #define GPIO_INT_EN00           0x18
  32 #define GPIO_INT_EN10           0x20
  33 #define GPIO_INT_EN20           0x28
  34 #define GPIO_INT_EN30           0x30
  35 #define GPIO_INT_POL            0x38
  36 #define GPIO_INT_TYPE           0x40
  37 #define GPIO_INT_STAT           0x48
  38
  39 #define GPIO_9XX_BYTESWAP       0X00
  40 #define GPIO_9XX_CTRL           0X04
  41 #define GPIO_9XX_OUTPUT_EN      0x14
  42 #define GPIO_9XX_PADDRV         0x24
  43 /*
  44  * Only for 4 interrupt enable reg are defined for now,
  45  * total reg available are 12.
  46  */
  47 #define GPIO_9XX_INT_EN00       0x44
  48 #define GPIO_9XX_INT_EN10       0x54
  49 #define GPIO_9XX_INT_EN20       0x64
  50 #define GPIO_9XX_INT_EN30       0x74
  51 #define GPIO_9XX_INT_POL        0x104
  52 #define GPIO_9XX_INT_TYPE       0x114
  53 #define GPIO_9XX_INT_STAT       0x124
  54
  55 #define GPIO_3XX_INT_EN00       0x18
  56 #define GPIO_3XX_INT_EN10       0x20
  57 #define GPIO_3XX_INT_EN20       0x28
  58 #define GPIO_3XX_INT_EN30       0x30
  59 #define GPIO_3XX_INT_POL        0x78
  60 #define GPIO_3XX_INT_TYPE       0x80
  61 #define GPIO_3XX_INT_STAT       0x88
  62
  63 /* Interrupt type register mask */
  64 #define XLP_GPIO_IRQ_TYPE_LVL   0x0
  65 #define XLP_GPIO_IRQ_TYPE_EDGE  0x1
  66
  67 /* Interrupt polarity register mask */
  68 #define XLP_GPIO_IRQ_POL_HIGH   0x0
  69 #define XLP_GPIO_IRQ_POL_LOW    0x1
  70
  71 #define XLP_GPIO_REGSZ          32
  72 #define XLP_GPIO_IRQ_BASE       768
  73 #define XLP_MAX_NR_GPIO         96
  74
  75 /* XLP variants supported by this driver */
  76 enum {
  77         XLP_GPIO_VARIANT_XLP832 = 1,
  78         XLP_GPIO_VARIANT_XLP316,
  79         XLP_GPIO_VARIANT_XLP208,
  80         XLP_GPIO_VARIANT_XLP980,
  81         XLP_GPIO_VARIANT_XLP532,
  82         GPIO_VARIANT_VULCAN
  83 };
  84
  85 struct xlp_gpio_priv {
  86         struct gpio_chip chip;
  87         DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
  88         void __iomem *gpio_intr_en;     /* pointer to first intr enable reg */
  89         void __iomem *gpio_intr_stat;   /* pointer to first intr status reg */
  90         void __iomem *gpio_intr_type;   /* pointer to first intr type reg */
  91         void __iomem *gpio_intr_pol;    /* pointer to first intr polarity reg */
  92         void __iomem *gpio_out_en;      /* pointer to first output enable reg */
  93         void __iomem *gpio_paddrv;      /* pointer to first pad drive reg */
  94         spinlock_t lock;
  95 };
  96
  97 static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
  98 {
  99         u32 pos, regset;
 100
 101         pos = gpio % XLP_GPIO_REGSZ;
 102         regset = (gpio / XLP_GPIO_REGSZ) * 4;
 103         return !!(readl(addr + regset) & BIT(pos));
 104 }
 105
 106 static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
 107 {
 108         u32 value, pos, regset;
 109
 110         pos = gpio % XLP_GPIO_REGSZ;
 111         regset = (gpio / XLP_GPIO_REGSZ) * 4;
 112         value = readl(addr + regset);
 113
 114         if (state)
 115                 value |= BIT(pos);
 116         else
 117                 value &= ~BIT(pos);
 118
 119         writel(value, addr + regset);
 120 }
 121
 122 static void xlp_gpio_irq_disable(struct irq_data *d)
 123 {
 124         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 125         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&priv->lock, flags);
 129         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
 130         __clear_bit(d->hwirq, priv->gpio_enabled_mask);
 131         spin_unlock_irqrestore(&priv->lock, flags);
 132 }
 133
 134 static void xlp_gpio_irq_mask_ack(struct irq_data *d)
 135 {
 136         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 137         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 138         unsigned long flags;
 139
 140         spin_lock_irqsave(&priv->lock, flags);
 141         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
 142         xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
 143         __clear_bit(d->hwirq, priv->gpio_enabled_mask);
 144         spin_unlock_irqrestore(&priv->lock, flags);
 145 }
 146
 147 static void xlp_gpio_irq_unmask(struct irq_data *d)
 148 {
 149         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 150         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 151         unsigned long flags;
 152
 153         spin_lock_irqsave(&priv->lock, flags);
 154         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
 155         __set_bit(d->hwirq, priv->gpio_enabled_mask);
 156         spin_unlock_irqrestore(&priv->lock, flags);
 157 }
 158
 159 static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 160 {
 161         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 162         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 163         int pol, irq_type;
 164
 165         switch (type) {
 166         case IRQ_TYPE_EDGE_RISING:
 167                 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
 168                 pol = XLP_GPIO_IRQ_POL_HIGH;
 169                 break;
 170         case IRQ_TYPE_EDGE_FALLING:
 171                 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
 172                 pol = XLP_GPIO_IRQ_POL_LOW;
 173                 break;
 174         case IRQ_TYPE_LEVEL_HIGH:
 175                 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
 176                 pol = XLP_GPIO_IRQ_POL_HIGH;
 177                 break;
 178         case IRQ_TYPE_LEVEL_LOW:
 179                 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
 180                 pol = XLP_GPIO_IRQ_POL_LOW;
 181                 break;
 182         default:
 183                 return -EINVAL;
 184         }
 185
 186         xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
 187         xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
 188
 189         return 0;
 190 }
 191
 192 static struct irq_chip xlp_gpio_irq_chip = {
 193         .name           = "XLP-GPIO",
 194         .irq_mask_ack   = xlp_gpio_irq_mask_ack,
 195         .irq_disable    = xlp_gpio_irq_disable,
 196         .irq_set_type   = xlp_gpio_set_irq_type,
 197         .irq_unmask     = xlp_gpio_irq_unmask,
 198         .flags          = IRQCHIP_ONESHOT_SAFE,
 199 };
 200
 201 static void xlp_gpio_generic_handler(struct irq_desc *desc)
 202 {
 203         struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
 204         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 205         int gpio, regoff;
 206         u32 gpio_stat;
 207
 208         regoff = -1;
 209         gpio_stat = 0;
 210
 211         chained_irq_enter(irqchip, desc);
 212         for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
 213                 if (regoff != gpio / XLP_GPIO_REGSZ) {
 214                         regoff = gpio / XLP_GPIO_REGSZ;
 215                         gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
 216                 }
 217
 218                 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
 219                         generic_handle_irq(irq_find_mapping(
 220                                                 priv->chip.irq.domain, gpio));
 221         }
 222         chained_irq_exit(irqchip, desc);
 223 }
 224
 225 static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
 226 {
 227         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 228
 229         BUG_ON(gpio >= gc->ngpio);
 230         xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
 231
 232         return 0;
 233 }
 234
 235 static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
 236 {
 237         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 238
 239         BUG_ON(gpio >= gc->ngpio);
 240         xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
 241
 242         return 0;
 243 }
 244
 245 static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
 246 {
 247         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 248
 249         BUG_ON(gpio >= gc->ngpio);
 250         return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
 251 }
 252
 253 static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
 254 {
 255         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 256
 257         BUG_ON(gpio >= gc->ngpio);
 258         xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
 259 }
 260
 261 static const struct of_device_id xlp_gpio_of_ids[] = {
 262         {
 263                 .compatible = "netlogic,xlp832-gpio",
 264                 .data       = (void *)XLP_GPIO_VARIANT_XLP832,
 265         },
 266         {
 267                 .compatible = "netlogic,xlp316-gpio",
 268                 .data       = (void *)XLP_GPIO_VARIANT_XLP316,
 269         },
 270         {
 271                 .compatible = "netlogic,xlp208-gpio",
 272                 .data       = (void *)XLP_GPIO_VARIANT_XLP208,
 273         },
 274         {
 275                 .compatible = "netlogic,xlp980-gpio",
 276                 .data       = (void *)XLP_GPIO_VARIANT_XLP980,
 277         },
 278         {
 279                 .compatible = "netlogic,xlp532-gpio",
 280                 .data       = (void *)XLP_GPIO_VARIANT_XLP532,
 281         },
 282         {
 283                 .compatible = "brcm,vulcan-gpio",
 284                 .data       = (void *)GPIO_VARIANT_VULCAN,
 285         },
 286         { /* sentinel */ },
 287 };
 288 MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
 289
 290 static int xlp_gpio_probe(struct platform_device *pdev)
 291 {
 292         struct gpio_chip *gc;
 293         struct resource *iores;
 294         struct xlp_gpio_priv *priv;
 295         void __iomem *gpio_base;
 296         int irq_base, irq, err;
 297         int ngpio;
 298         u32 soc_type;
 299
 300         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 301         if (!iores)
 302                 return -ENODEV;
 303
 304         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 305         if (!priv)
 306                 return -ENOMEM;
 307
 308         gpio_base = devm_ioremap_resource(&pdev->dev, iores);
 309         if (IS_ERR(gpio_base))
 310                 return PTR_ERR(gpio_base);
 311
 312         irq = platform_get_irq(pdev, 0);
 313         if (irq < 0)
 314                 return irq;
 315
 316         if (pdev->dev.of_node) {
 317                 soc_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
 318         } else {
 319                 const struct acpi_device_id *acpi_id;
 320
 321                 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
 322                                                 &pdev->dev);
 323                 if (!acpi_id || !acpi_id->driver_data) {
 324                         dev_err(&pdev->dev, "Unable to match ACPI ID\n");
 325                         return -ENODEV;
 326                 }
 327                 soc_type = (uintptr_t) acpi_id->driver_data;
 328         }
 329
 330         switch (soc_type) {
 331         case XLP_GPIO_VARIANT_XLP832:
 332                 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
 333                 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
 334                 priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
 335                 priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
 336                 priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
 337                 priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
 338                 ngpio = 41;
 339                 break;
 340         case XLP_GPIO_VARIANT_XLP208:
 341         case XLP_GPIO_VARIANT_XLP316:
 342                 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
 343                 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
 344                 priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
 345                 priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
 346                 priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
 347                 priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
 348
 349                 ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
 350                 break;
 351         case XLP_GPIO_VARIANT_XLP980:
 352         case XLP_GPIO_VARIANT_XLP532:
 353         case GPIO_VARIANT_VULCAN:
 354                 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
 355                 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
 356                 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
 357                 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
 358                 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
 359                 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
 360
 361                 if (soc_type == XLP_GPIO_VARIANT_XLP980)
 362                         ngpio = 66;
 363                 else if (soc_type == XLP_GPIO_VARIANT_XLP532)
 364                         ngpio = 67;
 365                 else
 366                         ngpio = 70;
 367                 break;
 368         default:
 369                 dev_err(&pdev->dev, "Unknown Processor type!\n");
 370                 return -ENODEV;
 371         }
 372
 373         bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
 374
 375         gc = &priv->chip;
 376
 377         gc->owner = THIS_MODULE;
 378         gc->label = dev_name(&pdev->dev);
 379         gc->base = 0;
 380         gc->parent = &pdev->dev;
 381         gc->ngpio = ngpio;
 382         gc->of_node = pdev->dev.of_node;
 383         gc->direction_output = xlp_gpio_dir_output;
 384         gc->direction_input = xlp_gpio_dir_input;
 385         gc->set = xlp_gpio_set;
 386         gc->get = xlp_gpio_get;
 387
 388         spin_lock_init(&priv->lock);
 389
 390         /* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */
 391         if (soc_type != GPIO_VARIANT_VULCAN) {
 392                 irq_base = devm_irq_alloc_descs(&pdev->dev, -1,
 393                                                 XLP_GPIO_IRQ_BASE,
 394                                                 gc->ngpio, 0);
 395                 if (irq_base < 0) {
 396                         dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
 397                         return irq_base;
 398                 }
 399         } else {
 400                 irq_base = 0;
 401         }
 402
 403         err = gpiochip_add_data(gc, priv);
 404         if (err < 0)
 405                 return err;
 406
 407         err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base,
 408                                 handle_level_irq, IRQ_TYPE_NONE);
 409         if (err) {
 410                 dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n");
 411                 goto out_gpio_remove;
 412         }
 413
 414         gpiochip_set_chained_irqchip(gc, &xlp_gpio_irq_chip, irq,
 415                         xlp_gpio_generic_handler);
 416
 417         dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
 418
 419         return 0;
 420
 421 out_gpio_remove:
 422         gpiochip_remove(gc);
 423         return err;
 424 }
 425
 426 #ifdef CONFIG_ACPI
 427 static const struct acpi_device_id xlp_gpio_acpi_match[] = {
 428         { "BRCM9006", GPIO_VARIANT_VULCAN },
 429         { "CAV9006",  GPIO_VARIANT_VULCAN },
 430         {},
 431 };
 432 MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
 433 #endif
 434
 435 static struct platform_driver xlp_gpio_driver = {
 436         .driver         = {
 437                 .name   = "xlp-gpio",
 438                 .of_match_table = xlp_gpio_of_ids,
 439                 .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
 440         },
 441         .probe          = xlp_gpio_probe,
 442 };
 443 module_platform_driver(xlp_gpio_driver);
 444
 445 MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
 446 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
 447 MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
 448 MODULE_LICENSE("GPL v2");