drivers/mailbox/tegra-hsp.c

   1 /*
   2  * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/mailbox_controller.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm.h>
  22 #include <linux/slab.h>
  23
  24 #include <dt-bindings/mailbox/tegra186-hsp.h>
  25
  26 #include "mailbox.h"
  27
  28 #define HSP_INT_IE(x)           (0x100 + ((x) * 4))
  29 #define HSP_INT_IV              0x300
  30 #define HSP_INT_IR              0x304
  31
  32 #define HSP_INT_EMPTY_SHIFT     0
  33 #define HSP_INT_EMPTY_MASK      0xff
  34 #define HSP_INT_FULL_SHIFT      8
  35 #define HSP_INT_FULL_MASK       0xff
  36
  37 #define HSP_INT_DIMENSIONING    0x380
  38 #define HSP_nSM_SHIFT           0
  39 #define HSP_nSS_SHIFT           4
  40 #define HSP_nAS_SHIFT           8
  41 #define HSP_nDB_SHIFT           12
  42 #define HSP_nSI_SHIFT           16
  43 #define HSP_nINT_MASK           0xf
  44
  45 #define HSP_DB_TRIGGER  0x0
  46 #define HSP_DB_ENABLE   0x4
  47 #define HSP_DB_RAW      0x8
  48 #define HSP_DB_PENDING  0xc
  49
  50 #define HSP_SM_SHRD_MBOX        0x0
  51 #define HSP_SM_SHRD_MBOX_FULL   BIT(31)
  52 #define HSP_SM_SHRD_MBOX_FULL_INT_IE    0x04
  53 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE   0x08
  54
  55 #define HSP_DB_CCPLEX           1
  56 #define HSP_DB_BPMP             3
  57 #define HSP_DB_MAX              7
  58
  59 struct tegra_hsp_channel;
  60 struct tegra_hsp;
  61
  62 struct tegra_hsp_channel {
  63         struct tegra_hsp *hsp;
  64         struct mbox_chan *chan;
  65         void __iomem *regs;
  66 };
  67
  68 struct tegra_hsp_doorbell {
  69         struct tegra_hsp_channel channel;
  70         struct list_head list;
  71         const char *name;
  72         unsigned int master;
  73         unsigned int index;
  74 };
  75
  76 struct tegra_hsp_mailbox {
  77         struct tegra_hsp_channel channel;
  78         unsigned int index;
  79         bool producer;
  80 };
  81
  82 struct tegra_hsp_db_map {
  83         const char *name;
  84         unsigned int master;
  85         unsigned int index;
  86 };
  87
  88 struct tegra_hsp_soc {
  89         const struct tegra_hsp_db_map *map;
  90         bool has_per_mb_ie;
  91 };
  92
  93 struct tegra_hsp {
  94         struct device *dev;
  95         const struct tegra_hsp_soc *soc;
  96         struct mbox_controller mbox_db;
  97         struct mbox_controller mbox_sm;
  98         void __iomem *regs;
  99         unsigned int doorbell_irq;
 100         unsigned int *shared_irqs;
 101         unsigned int shared_irq;
 102         unsigned int num_sm;
 103         unsigned int num_as;
 104         unsigned int num_ss;
 105         unsigned int num_db;
 106         unsigned int num_si;
 107         spinlock_t lock;
 108
 109         struct list_head doorbells;
 110         struct tegra_hsp_mailbox *mailboxes;
 111
 112         unsigned long mask;
 113 };
 114
 115 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
 116 {
 117         return readl(hsp->regs + offset);
 118 }
 119
 120 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
 121                                     unsigned int offset)
 122 {
 123         writel(value, hsp->regs + offset);
 124 }
 125
 126 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
 127                                           unsigned int offset)
 128 {
 129         return readl(channel->regs + offset);
 130 }
 131
 132 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
 133                                             u32 value, unsigned int offset)
 134 {
 135         writel(value, channel->regs + offset);
 136 }
 137
 138 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
 139 {
 140         u32 value;
 141
 142         value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
 143
 144         return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
 145 }
 146
 147 static struct tegra_hsp_doorbell *
 148 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
 149 {
 150         struct tegra_hsp_doorbell *entry;
 151
 152         list_for_each_entry(entry, &hsp->doorbells, list)
 153                 if (entry->master == master)
 154                         return entry;
 155
 156         return NULL;
 157 }
 158
 159 static struct tegra_hsp_doorbell *
 160 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
 161 {
 162         struct tegra_hsp_doorbell *db;
 163         unsigned long flags;
 164
 165         spin_lock_irqsave(&hsp->lock, flags);
 166         db = __tegra_hsp_doorbell_get(hsp, master);
 167         spin_unlock_irqrestore(&hsp->lock, flags);
 168
 169         return db;
 170 }
 171
 172 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
 173 {
 174         struct tegra_hsp *hsp = data;
 175         struct tegra_hsp_doorbell *db;
 176         unsigned long master, value;
 177
 178         db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
 179         if (!db)
 180                 return IRQ_NONE;
 181
 182         value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
 183         tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
 184
 185         spin_lock(&hsp->lock);
 186
 187         for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
 188                 struct tegra_hsp_doorbell *db;
 189
 190                 db = __tegra_hsp_doorbell_get(hsp, master);
 191                 /*
 192                  * Depending on the bootloader chain, the CCPLEX doorbell will
 193                  * have some doorbells enabled, which means that requesting an
 194                  * interrupt will immediately fire.
 195                  *
 196                  * In that case, db->channel.chan will still be NULL here and
 197                  * cause a crash if not properly guarded.
 198                  *
 199                  * It remains to be seen if ignoring the doorbell in that case
 200                  * is the correct solution.
 201                  */
 202                 if (db && db->channel.chan)
 203                         mbox_chan_received_data(db->channel.chan, NULL);
 204         }
 205
 206         spin_unlock(&hsp->lock);
 207
 208         return IRQ_HANDLED;
 209 }
 210
 211 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
 212 {
 213         struct tegra_hsp *hsp = data;
 214         unsigned long bit, mask;
 215         u32 status, value;
 216         void *msg;
 217
 218         status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
 219
 220         /* process EMPTY interrupts first */
 221         mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
 222
 223         for_each_set_bit(bit, &mask, hsp->num_sm) {
 224                 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
 225
 226                 if (mb->producer) {
 227                         /*
 228                          * Disable EMPTY interrupts until data is sent with
 229                          * the next message. These interrupts are level-
 230                          * triggered, so if we kept them enabled they would
 231                          * constantly trigger until we next write data into
 232                          * the message.
 233                          */
 234                         spin_lock(&hsp->lock);
 235
 236                         hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
 237                         tegra_hsp_writel(hsp, hsp->mask,
 238                                          HSP_INT_IE(hsp->shared_irq));
 239
 240                         spin_unlock(&hsp->lock);
 241
 242                         mbox_chan_txdone(mb->channel.chan, 0);
 243                 }
 244         }
 245
 246         /* process FULL interrupts */
 247         mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
 248
 249         for_each_set_bit(bit, &mask, hsp->num_sm) {
 250                 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
 251
 252                 if (!mb->producer) {
 253                         value = tegra_hsp_channel_readl(&mb->channel,
 254                                                         HSP_SM_SHRD_MBOX);
 255                         value &= ~HSP_SM_SHRD_MBOX_FULL;
 256                         msg = (void *)(unsigned long)value;
 257                         mbox_chan_received_data(mb->channel.chan, msg);
 258
 259                         /*
 260                          * Need to clear all bits here since some producers,
 261                          * such as TCU, depend on fields in the register
 262                          * getting cleared by the consumer.
 263                          *
 264                          * The mailbox API doesn't give the consumers a way
 265                          * of doing that explicitly, so we have to make sure
 266                          * we cover all possible cases.
 267                          */
 268                         tegra_hsp_channel_writel(&mb->channel, 0x0,
 269                                                  HSP_SM_SHRD_MBOX);
 270                 }
 271         }
 272
 273         return IRQ_HANDLED;
 274 }
 275
 276 static struct tegra_hsp_channel *
 277 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
 278                           unsigned int master, unsigned int index)
 279 {
 280         struct tegra_hsp_doorbell *db;
 281         unsigned int offset;
 282         unsigned long flags;
 283
 284         db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
 285         if (!db)
 286                 return ERR_PTR(-ENOMEM);
 287
 288         offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
 289         offset += index * 0x100;
 290
 291         db->channel.regs = hsp->regs + offset;
 292         db->channel.hsp = hsp;
 293
 294         db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
 295         db->master = master;
 296         db->index = index;
 297
 298         spin_lock_irqsave(&hsp->lock, flags);
 299         list_add_tail(&db->list, &hsp->doorbells);
 300         spin_unlock_irqrestore(&hsp->lock, flags);
 301
 302         return &db->channel;
 303 }
 304
 305 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
 306 {
 307         struct tegra_hsp_doorbell *db = chan->con_priv;
 308
 309         tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
 310
 311         return 0;
 312 }
 313
 314 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
 315 {
 316         struct tegra_hsp_doorbell *db = chan->con_priv;
 317         struct tegra_hsp *hsp = db->channel.hsp;
 318         struct tegra_hsp_doorbell *ccplex;
 319         unsigned long flags;
 320         u32 value;
 321
 322         if (db->master >= chan->mbox->num_chans) {
 323                 dev_err(chan->mbox->dev,
 324                         "invalid master ID %u for HSP channel\n",
 325                         db->master);
 326                 return -EINVAL;
 327         }
 328
 329         ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
 330         if (!ccplex)
 331                 return -ENODEV;
 332
 333         if (!tegra_hsp_doorbell_can_ring(db))
 334                 return -ENODEV;
 335
 336         spin_lock_irqsave(&hsp->lock, flags);
 337
 338         value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
 339         value |= BIT(db->master);
 340         tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
 341
 342         spin_unlock_irqrestore(&hsp->lock, flags);
 343
 344         return 0;
 345 }
 346
 347 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
 348 {
 349         struct tegra_hsp_doorbell *db = chan->con_priv;
 350         struct tegra_hsp *hsp = db->channel.hsp;
 351         struct tegra_hsp_doorbell *ccplex;
 352         unsigned long flags;
 353         u32 value;
 354
 355         ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
 356         if (!ccplex)
 357                 return;
 358
 359         spin_lock_irqsave(&hsp->lock, flags);
 360
 361         value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
 362         value &= ~BIT(db->master);
 363         tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
 364
 365         spin_unlock_irqrestore(&hsp->lock, flags);
 366 }
 367
 368 static const struct mbox_chan_ops tegra_hsp_db_ops = {
 369         .send_data = tegra_hsp_doorbell_send_data,
 370         .startup = tegra_hsp_doorbell_startup,
 371         .shutdown = tegra_hsp_doorbell_shutdown,
 372 };
 373
 374 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
 375 {
 376         struct tegra_hsp_mailbox *mb = chan->con_priv;
 377         struct tegra_hsp *hsp = mb->channel.hsp;
 378         unsigned long flags;
 379         u32 value;
 380
 381         if (WARN_ON(!mb->producer))
 382                 return -EPERM;
 383
 384         /* copy data and mark mailbox full */
 385         value = (u32)(unsigned long)data;
 386         value |= HSP_SM_SHRD_MBOX_FULL;
 387
 388         tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
 389
 390         /* enable EMPTY interrupt for the shared mailbox */
 391         spin_lock_irqsave(&hsp->lock, flags);
 392
 393         hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
 394         tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
 395
 396         spin_unlock_irqrestore(&hsp->lock, flags);
 397
 398         return 0;
 399 }
 400
 401 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
 402                                    unsigned long timeout)
 403 {
 404         struct tegra_hsp_mailbox *mb = chan->con_priv;
 405         struct tegra_hsp_channel *ch = &mb->channel;
 406         u32 value;
 407
 408         timeout = jiffies + msecs_to_jiffies(timeout);
 409
 410         while (time_before(jiffies, timeout)) {
 411                 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
 412                 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
 413                         mbox_chan_txdone(chan, 0);
 414                         return 0;
 415                 }
 416
 417                 udelay(1);
 418         }
 419
 420         return -ETIME;
 421 }
 422
 423 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
 424 {
 425         struct tegra_hsp_mailbox *mb = chan->con_priv;
 426         struct tegra_hsp_channel *ch = &mb->channel;
 427         struct tegra_hsp *hsp = mb->channel.hsp;
 428         unsigned long flags;
 429
 430         chan->txdone_method = TXDONE_BY_IRQ;
 431
 432         /*
 433          * Shared mailboxes start out as consumers by default. FULL and EMPTY
 434          * interrupts are coalesced at the same shared interrupt.
 435          *
 436          * Keep EMPTY interrupts disabled at startup and only enable them when
 437          * the mailbox is actually full. This is required because the FULL and
 438          * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
 439          * enabled all the time would cause an interrupt storm while mailboxes
 440          * are idle.
 441          */
 442
 443         spin_lock_irqsave(&hsp->lock, flags);
 444
 445         if (mb->producer)
 446                 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
 447         else
 448                 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
 449
 450         tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
 451
 452         spin_unlock_irqrestore(&hsp->lock, flags);
 453
 454         if (hsp->soc->has_per_mb_ie) {
 455                 if (mb->producer)
 456                         tegra_hsp_channel_writel(ch, 0x0,
 457                                                  HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
 458                 else
 459                         tegra_hsp_channel_writel(ch, 0x1,
 460                                                  HSP_SM_SHRD_MBOX_FULL_INT_IE);
 461         }
 462
 463         return 0;
 464 }
 465
 466 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
 467 {
 468         struct tegra_hsp_mailbox *mb = chan->con_priv;
 469         struct tegra_hsp_channel *ch = &mb->channel;
 470         struct tegra_hsp *hsp = mb->channel.hsp;
 471         unsigned long flags;
 472
 473         if (hsp->soc->has_per_mb_ie) {
 474                 if (mb->producer)
 475                         tegra_hsp_channel_writel(ch, 0x0,
 476                                                  HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
 477                 else
 478                         tegra_hsp_channel_writel(ch, 0x0,
 479                                                  HSP_SM_SHRD_MBOX_FULL_INT_IE);
 480         }
 481
 482         spin_lock_irqsave(&hsp->lock, flags);
 483
 484         if (mb->producer)
 485                 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
 486         else
 487                 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
 488
 489         tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
 490
 491         spin_unlock_irqrestore(&hsp->lock, flags);
 492 }
 493
 494 static const struct mbox_chan_ops tegra_hsp_sm_ops = {
 495         .send_data = tegra_hsp_mailbox_send_data,
 496         .flush = tegra_hsp_mailbox_flush,
 497         .startup = tegra_hsp_mailbox_startup,
 498         .shutdown = tegra_hsp_mailbox_shutdown,
 499 };
 500
 501 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
 502                                             const struct of_phandle_args *args)
 503 {
 504         struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
 505         unsigned int type = args->args[0], master = args->args[1];
 506         struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
 507         struct tegra_hsp_doorbell *db;
 508         struct mbox_chan *chan;
 509         unsigned long flags;
 510         unsigned int i;
 511
 512         if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
 513                 return ERR_PTR(-ENODEV);
 514
 515         db = tegra_hsp_doorbell_get(hsp, master);
 516         if (db)
 517                 channel = &db->channel;
 518
 519         if (IS_ERR(channel))
 520                 return ERR_CAST(channel);
 521
 522         spin_lock_irqsave(&hsp->lock, flags);
 523
 524         for (i = 0; i < mbox->num_chans; i++) {
 525                 chan = &mbox->chans[i];
 526                 if (!chan->con_priv) {
 527                         channel->chan = chan;
 528                         chan->con_priv = db;
 529                         break;
 530                 }
 531
 532                 chan = NULL;
 533         }
 534
 535         spin_unlock_irqrestore(&hsp->lock, flags);
 536
 537         return chan ?: ERR_PTR(-EBUSY);
 538 }
 539
 540 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
 541                                             const struct of_phandle_args *args)
 542 {
 543         struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
 544         unsigned int type = args->args[0], index;
 545         struct tegra_hsp_mailbox *mb;
 546
 547         index = args->args[1] & TEGRA_HSP_SM_MASK;
 548
 549         if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
 550             index >= hsp->num_sm)
 551                 return ERR_PTR(-ENODEV);
 552
 553         mb = &hsp->mailboxes[index];
 554
 555         if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
 556                 mb->producer = false;
 557         else
 558                 mb->producer = true;
 559
 560         return mb->channel.chan;
 561 }
 562
 563 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
 564 {
 565         const struct tegra_hsp_db_map *map = hsp->soc->map;
 566         struct tegra_hsp_channel *channel;
 567
 568         while (map->name) {
 569                 channel = tegra_hsp_doorbell_create(hsp, map->name,
 570                                                     map->master, map->index);
 571                 if (IS_ERR(channel))
 572                         return PTR_ERR(channel);
 573
 574                 map++;
 575         }
 576
 577         return 0;
 578 }
 579
 580 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
 581 {
 582         int i;
 583
 584         hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
 585                                       GFP_KERNEL);
 586         if (!hsp->mailboxes)
 587                 return -ENOMEM;
 588
 589         for (i = 0; i < hsp->num_sm; i++) {
 590                 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
 591
 592                 mb->index = i;
 593
 594                 mb->channel.hsp = hsp;
 595                 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
 596                 mb->channel.chan = &hsp->mbox_sm.chans[i];
 597                 mb->channel.chan->con_priv = mb;
 598         }
 599
 600         return 0;
 601 }
 602
 603 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
 604 {
 605         unsigned int i, irq = 0;
 606         int err;
 607
 608         for (i = 0; i < hsp->num_si; i++) {
 609                 irq = hsp->shared_irqs[i];
 610                 if (irq <= 0)
 611                         continue;
 612
 613                 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
 614                                        dev_name(hsp->dev), hsp);
 615                 if (err < 0) {
 616                         dev_err(hsp->dev, "failed to request interrupt: %d\n",
 617                                 err);
 618                         continue;
 619                 }
 620
 621                 hsp->shared_irq = i;
 622
 623                 /* disable all interrupts */
 624                 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
 625
 626                 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
 627
 628                 break;
 629         }
 630
 631         if (i == hsp->num_si) {
 632                 dev_err(hsp->dev, "failed to find available interrupt\n");
 633                 return -ENOENT;
 634         }
 635
 636         return 0;
 637 }
 638
 639 static int tegra_hsp_probe(struct platform_device *pdev)
 640 {
 641         struct tegra_hsp *hsp;
 642         struct resource *res;
 643         unsigned int i;
 644         u32 value;
 645         int err;
 646
 647         hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
 648         if (!hsp)
 649                 return -ENOMEM;
 650
 651         hsp->dev = &pdev->dev;
 652         hsp->soc = of_device_get_match_data(&pdev->dev);
 653         INIT_LIST_HEAD(&hsp->doorbells);
 654         spin_lock_init(&hsp->lock);
 655
 656         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 657         hsp->regs = devm_ioremap_resource(&pdev->dev, res);
 658         if (IS_ERR(hsp->regs))
 659                 return PTR_ERR(hsp->regs);
 660
 661         value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
 662         hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
 663         hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
 664         hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
 665         hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
 666         hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
 667
 668         err = platform_get_irq_byname(pdev, "doorbell");
 669         if (err >= 0)
 670                 hsp->doorbell_irq = err;
 671
 672         if (hsp->num_si > 0) {
 673                 unsigned int count = 0;
 674
 675                 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
 676                                                 sizeof(*hsp->shared_irqs),
 677                                                 GFP_KERNEL);
 678                 if (!hsp->shared_irqs)
 679                         return -ENOMEM;
 680
 681                 for (i = 0; i < hsp->num_si; i++) {
 682                         char *name;
 683
 684                         name = kasprintf(GFP_KERNEL, "shared%u", i);
 685                         if (!name)
 686                                 return -ENOMEM;
 687
 688                         err = platform_get_irq_byname(pdev, name);
 689                         if (err >= 0) {
 690                                 hsp->shared_irqs[i] = err;
 691                                 count++;
 692                         }
 693
 694                         kfree(name);
 695                 }
 696
 697                 if (count == 0) {
 698                         devm_kfree(&pdev->dev, hsp->shared_irqs);
 699                         hsp->shared_irqs = NULL;
 700                 }
 701         }
 702
 703         /* setup the doorbell controller */
 704         hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
 705         hsp->mbox_db.num_chans = 32;
 706         hsp->mbox_db.dev = &pdev->dev;
 707         hsp->mbox_db.ops = &tegra_hsp_db_ops;
 708
 709         hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
 710                                           sizeof(*hsp->mbox_db.chans),
 711                                           GFP_KERNEL);
 712         if (!hsp->mbox_db.chans)
 713                 return -ENOMEM;
 714
 715         if (hsp->doorbell_irq) {
 716                 err = tegra_hsp_add_doorbells(hsp);
 717                 if (err < 0) {
 718                         dev_err(&pdev->dev, "failed to add doorbells: %d\n",
 719                                 err);
 720                         return err;
 721                 }
 722         }
 723
 724         err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
 725         if (err < 0) {
 726                 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
 727                         err);
 728                 return err;
 729         }
 730
 731         /* setup the shared mailbox controller */
 732         hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
 733         hsp->mbox_sm.num_chans = hsp->num_sm;
 734         hsp->mbox_sm.dev = &pdev->dev;
 735         hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
 736
 737         hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
 738                                           sizeof(*hsp->mbox_sm.chans),
 739                                           GFP_KERNEL);
 740         if (!hsp->mbox_sm.chans)
 741                 return -ENOMEM;
 742
 743         if (hsp->shared_irqs) {
 744                 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
 745                 if (err < 0) {
 746                         dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
 747                                 err);
 748                         return err;
 749                 }
 750         }
 751
 752         err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
 753         if (err < 0) {
 754                 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
 755                         err);
 756                 return err;
 757         }
 758
 759         platform_set_drvdata(pdev, hsp);
 760
 761         if (hsp->doorbell_irq) {
 762                 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
 763                                        tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
 764                                        dev_name(&pdev->dev), hsp);
 765                 if (err < 0) {
 766                         dev_err(&pdev->dev,
 767                                 "failed to request doorbell IRQ#%u: %d\n",
 768                                 hsp->doorbell_irq, err);
 769                         return err;
 770                 }
 771         }
 772
 773         if (hsp->shared_irqs) {
 774                 err = tegra_hsp_request_shared_irq(hsp);
 775                 if (err < 0)
 776                         return err;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int tegra_hsp_resume(struct device *dev)
 783 {
 784         struct tegra_hsp *hsp = dev_get_drvdata(dev);
 785         unsigned int i;
 786
 787         for (i = 0; i < hsp->num_sm; i++) {
 788                 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
 789
 790                 if (mb->channel.chan->cl)
 791                         tegra_hsp_mailbox_startup(mb->channel.chan);
 792         }
 793
 794         return 0;
 795 }
 796
 797 static SIMPLE_DEV_PM_OPS(tegra_hsp_pm_ops, NULL, tegra_hsp_resume);
 798
 799 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
 800         { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
 801         { "bpmp",   TEGRA_HSP_DB_MASTER_BPMP,   HSP_DB_BPMP,   },
 802         { /* sentinel */ }
 803 };
 804
 805 static const struct tegra_hsp_soc tegra186_hsp_soc = {
 806         .map = tegra186_hsp_db_map,
 807         .has_per_mb_ie = false,
 808 };
 809
 810 static const struct tegra_hsp_soc tegra194_hsp_soc = {
 811         .map = tegra186_hsp_db_map,
 812         .has_per_mb_ie = true,
 813 };
 814
 815 static const struct of_device_id tegra_hsp_match[] = {
 816         { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
 817         { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
 818         { }
 819 };
 820
 821 static struct platform_driver tegra_hsp_driver = {
 822         .driver = {
 823                 .name = "tegra-hsp",
 824                 .of_match_table = tegra_hsp_match,
 825                 .pm = &tegra_hsp_pm_ops,
 826         },
 827         .probe = tegra_hsp_probe,
 828 };
 829
 830 static int __init tegra_hsp_init(void)
 831 {
 832         return platform_driver_register(&tegra_hsp_driver);
 833 }
 834 core_initcall(tegra_hsp_init);