arch/arc/kernel/time.c

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * vineetg: Jan 1011
   9  *  -sched_clock( ) no longer jiffies based. Uses the same clocksource
  10  *   as gtod
  11  *
  12  * Rajeshwarr/Vineetg: Mar 2008
  13  *  -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
  14  *   for arch independent gettimeofday()
  15  *  -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
  16  *
  17  * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
  18  */
  19
  20 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
  21  * Each can programmed to go from @count to @limit and optionally
  22  * interrupt when that happens.
  23  * A write to Control Register clears the Interrupt
  24  *
  25  * We've designated TIMER0 for events (clockevents)
  26  * while TIMER1 for free running (clocksource)
  27  *
  28  * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
  29  * which however is currently broken
  30  */
  31
  32 #include <linux/spinlock.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/module.h>
  35 #include <linux/sched.h>
  36 #include <linux/kernel.h>
  37 #include <linux/time.h>
  38 #include <linux/init.h>
  39 #include <linux/timex.h>
  40 #include <linux/profile.h>
  41 #include <linux/clocksource.h>
  42 #include <linux/clockchips.h>
  43 #include <asm/irq.h>
  44 #include <asm/arcregs.h>
  45 #include <asm/clk.h>
  46 #include <asm/mach_desc.h>
  47
  48 #include <asm/mcip.h>
  49
  50 /* Timer related Aux registers */
  51 #define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
  52 #define ARC_REG_TIMER0_CTRL     0x22    /* timer 0 control */
  53 #define ARC_REG_TIMER0_CNT      0x21    /* timer 0 count */
  54 #define ARC_REG_TIMER1_LIMIT    0x102   /* timer 1 limit */
  55 #define ARC_REG_TIMER1_CTRL     0x101   /* timer 1 control */
  56 #define ARC_REG_TIMER1_CNT      0x100   /* timer 1 count */
  57
  58 #define TIMER_CTRL_IE           (1 << 0) /* Interupt when Count reachs limit */
  59 #define TIMER_CTRL_NH           (1 << 1) /* Count only when CPU NOT halted */
  60
  61 #define ARC_TIMER_MAX   0xFFFFFFFF
  62
  63 /********** Clock Source Device *********/
  64
  65 #ifdef CONFIG_ARC_HAS_GRTC
  66
  67 static int arc_counter_setup(void)
  68 {
  69         return 1;
  70 }
  71
  72 static cycle_t arc_counter_read(struct clocksource *cs)
  73 {
  74         unsigned long flags;
  75         union {
  76 #ifdef CONFIG_CPU_BIG_ENDIAN
  77                 struct { u32 h, l; };
  78 #else
  79                 struct { u32 l, h; };
  80 #endif
  81                 cycle_t  full;
  82         } stamp;
  83
  84         local_irq_save(flags);
  85
  86         __mcip_cmd(CMD_GRTC_READ_LO, 0);
  87         stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
  88
  89         __mcip_cmd(CMD_GRTC_READ_HI, 0);
  90         stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
  91
  92         local_irq_restore(flags);
  93
  94         return stamp.full;
  95 }
  96
  97 static struct clocksource arc_counter = {
  98         .name   = "ARConnect GRTC",
  99         .rating = 400,
 100         .read   = arc_counter_read,
 101         .mask   = CLOCKSOURCE_MASK(64),
 102         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 103 };
 104
 105 #else
 106
 107 #ifdef CONFIG_ARC_HAS_RTC
 108
 109 #define AUX_RTC_CTRL    0x103
 110 #define AUX_RTC_LOW     0x104
 111 #define AUX_RTC_HIGH    0x105
 112
 113 int arc_counter_setup(void)
 114 {
 115         write_aux_reg(AUX_RTC_CTRL, 1);
 116
 117         /* Not usable in SMP */
 118         return !IS_ENABLED(CONFIG_SMP);
 119 }
 120
 121 static cycle_t arc_counter_read(struct clocksource *cs)
 122 {
 123         unsigned long status;
 124         union {
 125 #ifdef CONFIG_CPU_BIG_ENDIAN
 126                 struct { u32 high, low; };
 127 #else
 128                 struct { u32 low, high; };
 129 #endif
 130                 cycle_t  full;
 131         } stamp;
 132
 133         /*
 134          * hardware has an internal state machine which tracks readout of
 135          * low/high and updates the CTRL.status if
 136          *  - interrupt/exception taken between the two reads
 137          *  - high increments after low has been read
 138          */
 139         do {
 140                 stamp.low = read_aux_reg(AUX_RTC_LOW);
 141                 stamp.high = read_aux_reg(AUX_RTC_HIGH);
 142                 status = read_aux_reg(AUX_RTC_CTRL);
 143         } while (!(status & _BITUL(31)));
 144
 145         return stamp.full;
 146 }
 147
 148 static struct clocksource arc_counter = {
 149         .name   = "ARCv2 RTC",
 150         .rating = 350,
 151         .read   = arc_counter_read,
 152         .mask   = CLOCKSOURCE_MASK(64),
 153         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 154 };
 155
 156 #else /* !CONFIG_ARC_HAS_RTC */
 157
 158 /*
 159  * set 32bit TIMER1 to keep counting monotonically and wraparound
 160  */
 161 int arc_counter_setup(void)
 162 {
 163         write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
 164         write_aux_reg(ARC_REG_TIMER1_CNT, 0);
 165         write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
 166
 167         /* Not usable in SMP */
 168         return !IS_ENABLED(CONFIG_SMP);
 169 }
 170
 171 static cycle_t arc_counter_read(struct clocksource *cs)
 172 {
 173         return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
 174 }
 175
 176 static struct clocksource arc_counter = {
 177         .name   = "ARC Timer1",
 178         .rating = 300,
 179         .read   = arc_counter_read,
 180         .mask   = CLOCKSOURCE_MASK(32),
 181         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 182 };
 183
 184 #endif
 185 #endif
 186
 187 /********** Clock Event Device *********/
 188
 189 /*
 190  * Arm the timer to interrupt after @cycles
 191  * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
 192  */
 193 static void arc_timer_event_setup(unsigned int cycles)
 194 {
 195         write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
 196         write_aux_reg(ARC_REG_TIMER0_CNT, 0);   /* start from 0 */
 197
 198         write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
 199 }
 200
 201
 202 static int arc_clkevent_set_next_event(unsigned long delta,
 203                                        struct clock_event_device *dev)
 204 {
 205         arc_timer_event_setup(delta);
 206         return 0;
 207 }
 208
 209 static int arc_clkevent_set_periodic(struct clock_event_device *dev)
 210 {
 211         /*
 212          * At X Hz, 1 sec = 1000ms -> X cycles;
 213          *                    10ms -> X / 100 cycles
 214          */
 215         arc_timer_event_setup(arc_get_core_freq() / HZ);
 216         return 0;
 217 }
 218
 219 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
 220         .name                   = "ARC Timer0",
 221         .features               = CLOCK_EVT_FEAT_ONESHOT |
 222                                   CLOCK_EVT_FEAT_PERIODIC,
 223         .rating                 = 300,
 224         .irq                    = TIMER0_IRQ,   /* hardwired, no need for resources */
 225         .set_next_event         = arc_clkevent_set_next_event,
 226         .set_state_periodic     = arc_clkevent_set_periodic,
 227 };
 228
 229 static irqreturn_t timer_irq_handler(int irq, void *dev_id)
 230 {
 231         /*
 232          * Note that generic IRQ core could have passed @evt for @dev_id if
 233          * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
 234          */
 235         struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
 236         int irq_reenable = clockevent_state_periodic(evt);
 237
 238         /*
 239          * Any write to CTRL reg ACks the interrupt, we rewrite the
 240          * Count when [N]ot [H]alted bit.
 241          * And re-arm it if perioid by [I]nterrupt [E]nable bit
 242          */
 243         write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
 244
 245         evt->event_handler(evt);
 246
 247         return IRQ_HANDLED;
 248 }
 249
 250 /*
 251  * Setup the local event timer for @cpu
 252  */
 253 void arc_local_timer_setup()
 254 {
 255         struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
 256         int cpu = smp_processor_id();
 257
 258         evt->cpumask = cpumask_of(cpu);
 259         clockevents_config_and_register(evt, arc_get_core_freq(),
 260                                         0, ARC_TIMER_MAX);
 261
 262         /* setup the per-cpu timer IRQ handler - for all cpus */
 263         arc_request_percpu_irq(TIMER0_IRQ, cpu, timer_irq_handler,
 264                                "Timer0 (per-cpu-tick)", evt);
 265 }
 266
 267 /*
 268  * Called from start_kernel() - boot CPU only
 269  *
 270  * -Sets up h/w timers as applicable on boot cpu
 271  * -Also sets up any global state needed for timer subsystem:
 272  *    - for "counting" timer, registers a clocksource, usable across CPUs
 273  *      (provided that underlying counter h/w is synchronized across cores)
 274  *    - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
 275  */
 276 void __init time_init(void)
 277 {
 278         /*
 279          * sets up the timekeeping free-flowing counter which also returns
 280          * whether the counter is usable as clocksource
 281          */
 282         if (arc_counter_setup())
 283                 /*
 284                  * CLK upto 4.29 GHz can be safely represented in 32 bits
 285                  * because Max 32 bit number is 4,294,967,295
 286                  */
 287                 clocksource_register_hz(&arc_counter, arc_get_core_freq());
 288
 289         /* sets up the periodic event timer */
 290         arc_local_timer_setup();
 291 }