?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
uapi/if_ether.h: move __UAPI_DEF_ETHHDR libc define
[linux/fpc-iii.git] / drivers / gpio / gpio-dwapb.c
blobc07ada9c7af6d6f8403f5412bd5d4bc85fd46055
1 /*
2 * Copyright (c) 2011 Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10 #include <linux/acpi.h>
11 #include <linux/gpio/driver.h>
12 /* FIXME: for gpio_get_value(), replace this with direct register read */
13 #include <linux/gpio.h>
14 #include <linux/err.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/ioport.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/platform_device.h>
27 #include <linux/property.h>
28 #include <linux/spinlock.h>
29 #include <linux/platform_data/gpio-dwapb.h>
30 #include <linux/slab.h>
31
32 #include "gpiolib.h"
33
34 #define GPIO_SWPORTA_DR 0x00
35 #define GPIO_SWPORTA_DDR 0x04
36 #define GPIO_SWPORTB_DR 0x0c
37 #define GPIO_SWPORTB_DDR 0x10
38 #define GPIO_SWPORTC_DR 0x18
39 #define GPIO_SWPORTC_DDR 0x1c
40 #define GPIO_SWPORTD_DR 0x24
41 #define GPIO_SWPORTD_DDR 0x28
42 #define GPIO_INTEN 0x30
43 #define GPIO_INTMASK 0x34
44 #define GPIO_INTTYPE_LEVEL 0x38
45 #define GPIO_INT_POLARITY 0x3c
46 #define GPIO_INTSTATUS 0x40
47 #define GPIO_PORTA_DEBOUNCE 0x48
48 #define GPIO_PORTA_EOI 0x4c
49 #define GPIO_EXT_PORTA 0x50
50 #define GPIO_EXT_PORTB 0x54
51 #define GPIO_EXT_PORTC 0x58
52 #define GPIO_EXT_PORTD 0x5c
53
54 #define DWAPB_MAX_PORTS 4
55 #define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
56 #define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
57 #define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
58
59 #define GPIO_REG_OFFSET_V2 1
60
61 #define GPIO_INTMASK_V2 0x44
62 #define GPIO_INTTYPE_LEVEL_V2 0x34
63 #define GPIO_INT_POLARITY_V2 0x38
64 #define GPIO_INTSTATUS_V2 0x3c
65 #define GPIO_PORTA_EOI_V2 0x40
66
67 struct dwapb_gpio;
68
69 #ifdef CONFIG_PM_SLEEP
70 /* Store GPIO context across system-wide suspend/resume transitions */
71 struct dwapb_context {
72 u32 data;
73 u32 dir;
74 u32 ext;
75 u32 int_en;
76 u32 int_mask;
77 u32 int_type;
78 u32 int_pol;
79 u32 int_deb;
80 };
81 #endif
82
83 struct dwapb_gpio_port {
84 struct gpio_chip gc;
85 bool is_registered;
86 struct dwapb_gpio *gpio;
87 #ifdef CONFIG_PM_SLEEP
88 struct dwapb_context *ctx;
89 #endif
90 unsigned int idx;
91 };
92
93 struct dwapb_gpio {
94 struct device *dev;
95 void __iomem *regs;
96 struct dwapb_gpio_port *ports;
97 unsigned int nr_ports;
98 struct irq_domain *domain;
99 unsigned int flags;
100 };
101
102 static inline u32 gpio_reg_v2_convert(unsigned int offset)
103 {
104 switch (offset) {
105 case GPIO_INTMASK:
106 return GPIO_INTMASK_V2;
107 case GPIO_INTTYPE_LEVEL:
108 return GPIO_INTTYPE_LEVEL_V2;
109 case GPIO_INT_POLARITY:
110 return GPIO_INT_POLARITY_V2;
111 case GPIO_INTSTATUS:
112 return GPIO_INTSTATUS_V2;
113 case GPIO_PORTA_EOI:
114 return GPIO_PORTA_EOI_V2;
115 }
116
117 return offset;
118 }
119
120 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
121 {
122 if (gpio->flags & GPIO_REG_OFFSET_V2)
123 return gpio_reg_v2_convert(offset);
124
125 return offset;
126 }
127
128 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
129 {
130 struct gpio_chip *gc = &gpio->ports[0].gc;
131 void __iomem *reg_base = gpio->regs;
132
133 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
134 }
135
136 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
137 u32 val)
138 {
139 struct gpio_chip *gc = &gpio->ports[0].gc;
140 void __iomem *reg_base = gpio->regs;
141
142 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
143 }
144
145 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
146 {
147 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
148 struct dwapb_gpio *gpio = port->gpio;
149
150 return irq_find_mapping(gpio->domain, offset);
151 }
152
153 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
154 {
155 u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
156
157 if (gpio_get_value(gpio->ports[0].gc.base + offs))
158 v &= ~BIT(offs);
159 else
160 v |= BIT(offs);
161
162 dwapb_write(gpio, GPIO_INT_POLARITY, v);
163 }
164
165 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
166 {
167 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
168 u32 ret = irq_status;
169
170 while (irq_status) {
171 int hwirq = fls(irq_status) - 1;
172 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
173
174 generic_handle_irq(gpio_irq);
175 irq_status &= ~BIT(hwirq);
176
177 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
178 == IRQ_TYPE_EDGE_BOTH)
179 dwapb_toggle_trigger(gpio, hwirq);
180 }
181
182 return ret;
183 }
184
185 static void dwapb_irq_handler(struct irq_desc *desc)
186 {
187 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
188 struct irq_chip *chip = irq_desc_get_chip(desc);
189
190 dwapb_do_irq(gpio);
191
192 if (chip->irq_eoi)
193 chip->irq_eoi(irq_desc_get_irq_data(desc));
194 }
195
196 static void dwapb_irq_enable(struct irq_data *d)
197 {
198 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
199 struct dwapb_gpio *gpio = igc->private;
200 struct gpio_chip *gc = &gpio->ports[0].gc;
201 unsigned long flags;
202 u32 val;
203
204 spin_lock_irqsave(&gc->bgpio_lock, flags);
205 val = dwapb_read(gpio, GPIO_INTEN);
206 val |= BIT(d->hwirq);
207 dwapb_write(gpio, GPIO_INTEN, val);
208 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
209 }
210
211 static void dwapb_irq_disable(struct irq_data *d)
212 {
213 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
214 struct dwapb_gpio *gpio = igc->private;
215 struct gpio_chip *gc = &gpio->ports[0].gc;
216 unsigned long flags;
217 u32 val;
218
219 spin_lock_irqsave(&gc->bgpio_lock, flags);
220 val = dwapb_read(gpio, GPIO_INTEN);
221 val &= ~BIT(d->hwirq);
222 dwapb_write(gpio, GPIO_INTEN, val);
223 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
224 }
225
226 static int dwapb_irq_reqres(struct irq_data *d)
227 {
228 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
229 struct dwapb_gpio *gpio = igc->private;
230 struct gpio_chip *gc = &gpio->ports[0].gc;
231
232 if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
233 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
234 irqd_to_hwirq(d));
235 return -EINVAL;
236 }
237 return 0;
238 }
239
240 static void dwapb_irq_relres(struct irq_data *d)
241 {
242 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
243 struct dwapb_gpio *gpio = igc->private;
244 struct gpio_chip *gc = &gpio->ports[0].gc;
245
246 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
247 }
248
249 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
250 {
251 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
252 struct dwapb_gpio *gpio = igc->private;
253 struct gpio_chip *gc = &gpio->ports[0].gc;
254 int bit = d->hwirq;
255 unsigned long level, polarity, flags;
256
257 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
258 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
259 return -EINVAL;
260
261 spin_lock_irqsave(&gc->bgpio_lock, flags);
262 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
263 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
264
265 switch (type) {
266 case IRQ_TYPE_EDGE_BOTH:
267 level |= BIT(bit);
268 dwapb_toggle_trigger(gpio, bit);
269 break;
270 case IRQ_TYPE_EDGE_RISING:
271 level |= BIT(bit);
272 polarity |= BIT(bit);
273 break;
274 case IRQ_TYPE_EDGE_FALLING:
275 level |= BIT(bit);
276 polarity &= ~BIT(bit);
277 break;
278 case IRQ_TYPE_LEVEL_HIGH:
279 level &= ~BIT(bit);
280 polarity |= BIT(bit);
281 break;
282 case IRQ_TYPE_LEVEL_LOW:
283 level &= ~BIT(bit);
284 polarity &= ~BIT(bit);
285 break;
286 }
287
288 irq_setup_alt_chip(d, type);
289
290 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
291 if (type != IRQ_TYPE_EDGE_BOTH)
292 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
293 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
294
295 return 0;
296 }
297
298 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
299 unsigned offset, unsigned debounce)
300 {
301 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
302 struct dwapb_gpio *gpio = port->gpio;
303 unsigned long flags, val_deb;
304 unsigned long mask = gc->pin2mask(gc, offset);
305
306 spin_lock_irqsave(&gc->bgpio_lock, flags);
307
308 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
309 if (debounce)
310 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
311 else
312 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
313
314 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
315
316 return 0;
317 }
318
319 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
320 unsigned long config)
321 {
322 u32 debounce;
323
324 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
325 return -ENOTSUPP;
326
327 debounce = pinconf_to_config_argument(config);
328 return dwapb_gpio_set_debounce(gc, offset, debounce);
329 }
330
331 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
332 {
333 u32 worked;
334 struct dwapb_gpio *gpio = dev_id;
335
336 worked = dwapb_do_irq(gpio);
337
338 return worked ? IRQ_HANDLED : IRQ_NONE;
339 }
340
341 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
342 struct dwapb_gpio_port *port,
343 struct dwapb_port_property *pp)
344 {
345 struct gpio_chip *gc = &port->gc;
346 struct fwnode_handle *fwnode = pp->fwnode;
347 struct irq_chip_generic *irq_gc = NULL;
348 unsigned int hwirq, ngpio = gc->ngpio;
349 struct irq_chip_type *ct;
350 int err, i;
351
352 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
353 &irq_generic_chip_ops, gpio);
354 if (!gpio->domain)
355 return;
356
357 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
358 "gpio-dwapb", handle_level_irq,
359 IRQ_NOREQUEST, 0,
360 IRQ_GC_INIT_NESTED_LOCK);
361 if (err) {
362 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
363 irq_domain_remove(gpio->domain);
364 gpio->domain = NULL;
365 return;
366 }
367
368 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
369 if (!irq_gc) {
370 irq_domain_remove(gpio->domain);
371 gpio->domain = NULL;
372 return;
373 }
374
375 irq_gc->reg_base = gpio->regs;
376 irq_gc->private = gpio;
377
378 for (i = 0; i < 2; i++) {
379 ct = &irq_gc->chip_types[i];
380 ct->chip.irq_ack = irq_gc_ack_set_bit;
381 ct->chip.irq_mask = irq_gc_mask_set_bit;
382 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
383 ct->chip.irq_set_type = dwapb_irq_set_type;
384 ct->chip.irq_enable = dwapb_irq_enable;
385 ct->chip.irq_disable = dwapb_irq_disable;
386 ct->chip.irq_request_resources = dwapb_irq_reqres;
387 ct->chip.irq_release_resources = dwapb_irq_relres;
388 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
389 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
390 ct->type = IRQ_TYPE_LEVEL_MASK;
391 }
392
393 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
394 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
395 irq_gc->chip_types[1].handler = handle_edge_irq;
396
397 if (!pp->irq_shared) {
398 irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
399 gpio);
400 } else {
401 /*
402 * Request a shared IRQ since where MFD would have devices
403 * using the same irq pin
404 */
405 err = devm_request_irq(gpio->dev, pp->irq,
406 dwapb_irq_handler_mfd,
407 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
408 if (err) {
409 dev_err(gpio->dev, "error requesting IRQ\n");
410 irq_domain_remove(gpio->domain);
411 gpio->domain = NULL;
412 return;
413 }
414 }
415
416 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
417 irq_create_mapping(gpio->domain, hwirq);
418
419 port->gc.to_irq = dwapb_gpio_to_irq;
420 }
421
422 static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
423 {
424 struct dwapb_gpio_port *port = &gpio->ports[0];
425 struct gpio_chip *gc = &port->gc;
426 unsigned int ngpio = gc->ngpio;
427 irq_hw_number_t hwirq;
428
429 if (!gpio->domain)
430 return;
431
432 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
433 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
434
435 irq_domain_remove(gpio->domain);
436 gpio->domain = NULL;
437 }
438
439 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
440 struct dwapb_port_property *pp,
441 unsigned int offs)
442 {
443 struct dwapb_gpio_port *port;
444 void __iomem *dat, *set, *dirout;
445 int err;
446
447 port = &gpio->ports[offs];
448 port->gpio = gpio;
449 port->idx = pp->idx;
450
451 #ifdef CONFIG_PM_SLEEP
452 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
453 if (!port->ctx)
454 return -ENOMEM;
455 #endif
456
457 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
458 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
459 dirout = gpio->regs + GPIO_SWPORTA_DDR +
460 (pp->idx * GPIO_SWPORT_DDR_SIZE);
461
462 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
463 NULL, false);
464 if (err) {
465 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
466 port->idx);
467 return err;
468 }
469
470 #ifdef CONFIG_OF_GPIO
471 port->gc.of_node = to_of_node(pp->fwnode);
472 #endif
473 port->gc.ngpio = pp->ngpio;
474 port->gc.base = pp->gpio_base;
475
476 /* Only port A support debounce */
477 if (pp->idx == 0)
478 port->gc.set_config = dwapb_gpio_set_config;
479
480 if (pp->irq)
481 dwapb_configure_irqs(gpio, port, pp);
482
483 err = gpiochip_add_data(&port->gc, port);
484 if (err)
485 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
486 port->idx);
487 else
488 port->is_registered = true;
489
490 /* Add GPIO-signaled ACPI event support */
491 if (pp->irq)
492 acpi_gpiochip_request_interrupts(&port->gc);
493
494 return err;
495 }
496
497 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
498 {
499 unsigned int m;
500
501 for (m = 0; m < gpio->nr_ports; ++m)
502 if (gpio->ports[m].is_registered)
503 gpiochip_remove(&gpio->ports[m].gc);
504 }
505
506 static struct dwapb_platform_data *
507 dwapb_gpio_get_pdata(struct device *dev)
508 {
509 struct fwnode_handle *fwnode;
510 struct dwapb_platform_data *pdata;
511 struct dwapb_port_property *pp;
512 int nports;
513 int i;
514
515 nports = device_get_child_node_count(dev);
516 if (nports == 0)
517 return ERR_PTR(-ENODEV);
518
519 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
520 if (!pdata)
521 return ERR_PTR(-ENOMEM);
522
523 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
524 if (!pdata->properties)
525 return ERR_PTR(-ENOMEM);
526
527 pdata->nports = nports;
528
529 i = 0;
530 device_for_each_child_node(dev, fwnode) {
531 pp = &pdata->properties[i++];
532 pp->fwnode = fwnode;
533
534 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
535 pp->idx >= DWAPB_MAX_PORTS) {
536 dev_err(dev,
537 "missing/invalid port index for port%d\n", i);
538 fwnode_handle_put(fwnode);
539 return ERR_PTR(-EINVAL);
540 }
541
542 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
543 &pp->ngpio)) {
544 dev_info(dev,
545 "failed to get number of gpios for port%d\n",
546 i);
547 pp->ngpio = 32;
548 }
549
550 /*
551 * Only port A can provide interrupts in all configurations of
552 * the IP.
553 */
554 if (dev->of_node && pp->idx == 0 &&
555 fwnode_property_read_bool(fwnode,
556 "interrupt-controller")) {
557 pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0);
558 if (!pp->irq)
559 dev_warn(dev, "no irq for port%d\n", pp->idx);
560 }
561
562 if (has_acpi_companion(dev) && pp->idx == 0)
563 pp->irq = platform_get_irq(to_platform_device(dev), 0);
564
565 pp->irq_shared = false;
566 pp->gpio_base = -1;
567 }
568
569 return pdata;
570 }
571
572 static const struct of_device_id dwapb_of_match[] = {
573 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
574 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
575 { /* Sentinel */ }
576 };
577 MODULE_DEVICE_TABLE(of, dwapb_of_match);
578
579 static const struct acpi_device_id dwapb_acpi_match[] = {
580 {"HISI0181", 0},
581 {"APMC0D07", 0},
582 {"APMC0D81", GPIO_REG_OFFSET_V2},
583 { }
584 };
585 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
586
587 static int dwapb_gpio_probe(struct platform_device *pdev)
588 {
589 unsigned int i;
590 struct resource *res;
591 struct dwapb_gpio *gpio;
592 int err;
593 struct device *dev = &pdev->dev;
594 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
595
596 if (!pdata) {
597 pdata = dwapb_gpio_get_pdata(dev);
598 if (IS_ERR(pdata))
599 return PTR_ERR(pdata);
600 }
601
602 if (!pdata->nports)
603 return -ENODEV;
604
605 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
606 if (!gpio)
607 return -ENOMEM;
608
609 gpio->dev = &pdev->dev;
610 gpio->nr_ports = pdata->nports;
611
612 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
613 sizeof(*gpio->ports), GFP_KERNEL);
614 if (!gpio->ports)
615 return -ENOMEM;
616
617 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
618 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
619 if (IS_ERR(gpio->regs))
620 return PTR_ERR(gpio->regs);
621
622 gpio->flags = 0;
623 if (dev->of_node) {
624 const struct of_device_id *of_devid;
625
626 of_devid = of_match_device(dwapb_of_match, dev);
627 if (of_devid) {
628 if (of_devid->data)
629 gpio->flags = (uintptr_t)of_devid->data;
630 }
631 } else if (has_acpi_companion(dev)) {
632 const struct acpi_device_id *acpi_id;
633
634 acpi_id = acpi_match_device(dwapb_acpi_match, dev);
635 if (acpi_id) {
636 if (acpi_id->driver_data)
637 gpio->flags = acpi_id->driver_data;
638 }
639 }
640
641 for (i = 0; i < gpio->nr_ports; i++) {
642 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
643 if (err)
644 goto out_unregister;
645 }
646 platform_set_drvdata(pdev, gpio);
647
648 return 0;
649
650 out_unregister:
651 dwapb_gpio_unregister(gpio);
652 dwapb_irq_teardown(gpio);
653
654 return err;
655 }
656
657 static int dwapb_gpio_remove(struct platform_device *pdev)
658 {
659 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
660
661 dwapb_gpio_unregister(gpio);
662 dwapb_irq_teardown(gpio);
663
664 return 0;
665 }
666
667 #ifdef CONFIG_PM_SLEEP
668 static int dwapb_gpio_suspend(struct device *dev)
669 {
670 struct platform_device *pdev = to_platform_device(dev);
671 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
672 struct gpio_chip *gc = &gpio->ports[0].gc;
673 unsigned long flags;
674 int i;
675
676 spin_lock_irqsave(&gc->bgpio_lock, flags);
677 for (i = 0; i < gpio->nr_ports; i++) {
678 unsigned int offset;
679 unsigned int idx = gpio->ports[i].idx;
680 struct dwapb_context *ctx = gpio->ports[i].ctx;
681
682 BUG_ON(!ctx);
683
684 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
685 ctx->dir = dwapb_read(gpio, offset);
686
687 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
688 ctx->data = dwapb_read(gpio, offset);
689
690 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
691 ctx->ext = dwapb_read(gpio, offset);
692
693 /* Only port A can provide interrupts */
694 if (idx == 0) {
695 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
696 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
697 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
698 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
699 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
700
701 /* Mask out interrupts */
702 dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
703 }
704 }
705 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
706
707 return 0;
708 }
709
710 static int dwapb_gpio_resume(struct device *dev)
711 {
712 struct platform_device *pdev = to_platform_device(dev);
713 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
714 struct gpio_chip *gc = &gpio->ports[0].gc;
715 unsigned long flags;
716 int i;
717
718 spin_lock_irqsave(&gc->bgpio_lock, flags);
719 for (i = 0; i < gpio->nr_ports; i++) {
720 unsigned int offset;
721 unsigned int idx = gpio->ports[i].idx;
722 struct dwapb_context *ctx = gpio->ports[i].ctx;
723
724 BUG_ON(!ctx);
725
726 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
727 dwapb_write(gpio, offset, ctx->data);
728
729 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
730 dwapb_write(gpio, offset, ctx->dir);
731
732 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
733 dwapb_write(gpio, offset, ctx->ext);
734
735 /* Only port A can provide interrupts */
736 if (idx == 0) {
737 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
738 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
739 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
740 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
741 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
742
743 /* Clear out spurious interrupts */
744 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
745 }
746 }
747 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
748
749 return 0;
750 }
751 #endif
752
753 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
754 dwapb_gpio_resume);
755
756 static struct platform_driver dwapb_gpio_driver = {
757 .driver = {
758 .name = "gpio-dwapb",
759 .pm = &dwapb_gpio_pm_ops,
760 .of_match_table = of_match_ptr(dwapb_of_match),
761 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
762 },
763 .probe = dwapb_gpio_probe,
764 .remove = dwapb_gpio_remove,
765 };
766
767 module_platform_driver(dwapb_gpio_driver);
768
769 MODULE_LICENSE("GPL");
770 MODULE_AUTHOR("Jamie Iles");
771 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
Linux with added FPC-III support