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uapi/if_ether.h: move __UAPI_DEF_ETHHDR libc define
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-rockchip.c
bloba9bc1e01f9828747b0d74417e1d2fba1f9f6b375
1 /*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26 #include <linux/init.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
43
44 #include "core.h"
45 #include "pinconf.h"
46
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
60
61 enum rockchip_pinctrl_type {
62 RV1108,
63 RK2928,
64 RK3066B,
65 RK3128,
66 RK3188,
67 RK3288,
68 RK3368,
69 RK3399,
70 };
71
72 /**
73 * Encode variants of iomux registers into a type variable
74 */
75 #define IOMUX_GPIO_ONLY BIT(0)
76 #define IOMUX_WIDTH_4BIT BIT(1)
77 #define IOMUX_SOURCE_PMU BIT(2)
78 #define IOMUX_UNROUTED BIT(3)
79 #define IOMUX_WIDTH_3BIT BIT(4)
80
81 /**
82 * @type: iomux variant using IOMUX_* constants
83 * @offset: if initialized to -1 it will be autocalculated, by specifying
84 * an initial offset value the relevant source offset can be reset
85 * to a new value for autocalculating the following iomux registers.
86 */
87 struct rockchip_iomux {
88 int type;
89 int offset;
90 };
91
92 /**
93 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
94 */
95 enum rockchip_pin_drv_type {
96 DRV_TYPE_IO_DEFAULT = 0,
97 DRV_TYPE_IO_1V8_OR_3V0,
98 DRV_TYPE_IO_1V8_ONLY,
99 DRV_TYPE_IO_1V8_3V0_AUTO,
100 DRV_TYPE_IO_3V3_ONLY,
101 DRV_TYPE_MAX
102 };
103
104 /**
105 * enum type index corresponding to rockchip_pull_list arrays index.
106 */
107 enum rockchip_pin_pull_type {
108 PULL_TYPE_IO_DEFAULT = 0,
109 PULL_TYPE_IO_1V8_ONLY,
110 PULL_TYPE_MAX
111 };
112
113 /**
114 * @drv_type: drive strength variant using rockchip_perpin_drv_type
115 * @offset: if initialized to -1 it will be autocalculated, by specifying
116 * an initial offset value the relevant source offset can be reset
117 * to a new value for autocalculating the following drive strength
118 * registers. if used chips own cal_drv func instead to calculate
119 * registers offset, the variant could be ignored.
120 */
121 struct rockchip_drv {
122 enum rockchip_pin_drv_type drv_type;
123 int offset;
124 };
125
126 /**
127 * @reg_base: register base of the gpio bank
128 * @reg_pull: optional separate register for additional pull settings
129 * @clk: clock of the gpio bank
130 * @irq: interrupt of the gpio bank
131 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
132 * @pin_base: first pin number
133 * @nr_pins: number of pins in this bank
134 * @name: name of the bank
135 * @bank_num: number of the bank, to account for holes
136 * @iomux: array describing the 4 iomux sources of the bank
137 * @drv: array describing the 4 drive strength sources of the bank
138 * @pull_type: array describing the 4 pull type sources of the bank
139 * @valid: are all necessary informations present
140 * @of_node: dt node of this bank
141 * @drvdata: common pinctrl basedata
142 * @domain: irqdomain of the gpio bank
143 * @gpio_chip: gpiolib chip
144 * @grange: gpio range
145 * @slock: spinlock for the gpio bank
146 * @route_mask: bits describing the routing pins of per bank
147 */
148 struct rockchip_pin_bank {
149 void __iomem *reg_base;
150 struct regmap *regmap_pull;
151 struct clk *clk;
152 int irq;
153 u32 saved_masks;
154 u32 pin_base;
155 u8 nr_pins;
156 char *name;
157 u8 bank_num;
158 struct rockchip_iomux iomux[4];
159 struct rockchip_drv drv[4];
160 enum rockchip_pin_pull_type pull_type[4];
161 bool valid;
162 struct device_node *of_node;
163 struct rockchip_pinctrl *drvdata;
164 struct irq_domain *domain;
165 struct gpio_chip gpio_chip;
166 struct pinctrl_gpio_range grange;
167 raw_spinlock_t slock;
168 u32 toggle_edge_mode;
169 u32 recalced_mask;
170 u32 route_mask;
171 };
172
173 #define PIN_BANK(id, pins, label) \
174 { \
175 .bank_num = id, \
176 .nr_pins = pins, \
177 .name = label, \
178 .iomux = { \
179 { .offset = -1 }, \
180 { .offset = -1 }, \
181 { .offset = -1 }, \
182 { .offset = -1 }, \
183 }, \
184 }
185
186 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
187 { \
188 .bank_num = id, \
189 .nr_pins = pins, \
190 .name = label, \
191 .iomux = { \
192 { .type = iom0, .offset = -1 }, \
193 { .type = iom1, .offset = -1 }, \
194 { .type = iom2, .offset = -1 }, \
195 { .type = iom3, .offset = -1 }, \
196 }, \
197 }
198
199 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
200 { \
201 .bank_num = id, \
202 .nr_pins = pins, \
203 .name = label, \
204 .iomux = { \
205 { .offset = -1 }, \
206 { .offset = -1 }, \
207 { .offset = -1 }, \
208 { .offset = -1 }, \
209 }, \
210 .drv = { \
211 { .drv_type = type0, .offset = -1 }, \
212 { .drv_type = type1, .offset = -1 }, \
213 { .drv_type = type2, .offset = -1 }, \
214 { .drv_type = type3, .offset = -1 }, \
215 }, \
216 }
217
218 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
219 drv2, drv3, pull0, pull1, \
220 pull2, pull3) \
221 { \
222 .bank_num = id, \
223 .nr_pins = pins, \
224 .name = label, \
225 .iomux = { \
226 { .offset = -1 }, \
227 { .offset = -1 }, \
228 { .offset = -1 }, \
229 { .offset = -1 }, \
230 }, \
231 .drv = { \
232 { .drv_type = drv0, .offset = -1 }, \
233 { .drv_type = drv1, .offset = -1 }, \
234 { .drv_type = drv2, .offset = -1 }, \
235 { .drv_type = drv3, .offset = -1 }, \
236 }, \
237 .pull_type[0] = pull0, \
238 .pull_type[1] = pull1, \
239 .pull_type[2] = pull2, \
240 .pull_type[3] = pull3, \
241 }
242
243 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
244 iom2, iom3, drv0, drv1, drv2, \
245 drv3, offset0, offset1, \
246 offset2, offset3) \
247 { \
248 .bank_num = id, \
249 .nr_pins = pins, \
250 .name = label, \
251 .iomux = { \
252 { .type = iom0, .offset = -1 }, \
253 { .type = iom1, .offset = -1 }, \
254 { .type = iom2, .offset = -1 }, \
255 { .type = iom3, .offset = -1 }, \
256 }, \
257 .drv = { \
258 { .drv_type = drv0, .offset = offset0 }, \
259 { .drv_type = drv1, .offset = offset1 }, \
260 { .drv_type = drv2, .offset = offset2 }, \
261 { .drv_type = drv3, .offset = offset3 }, \
262 }, \
263 }
264
265 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
266 label, iom0, iom1, iom2, \
267 iom3, drv0, drv1, drv2, \
268 drv3, offset0, offset1, \
269 offset2, offset3, pull0, \
270 pull1, pull2, pull3) \
271 { \
272 .bank_num = id, \
273 .nr_pins = pins, \
274 .name = label, \
275 .iomux = { \
276 { .type = iom0, .offset = -1 }, \
277 { .type = iom1, .offset = -1 }, \
278 { .type = iom2, .offset = -1 }, \
279 { .type = iom3, .offset = -1 }, \
280 }, \
281 .drv = { \
282 { .drv_type = drv0, .offset = offset0 }, \
283 { .drv_type = drv1, .offset = offset1 }, \
284 { .drv_type = drv2, .offset = offset2 }, \
285 { .drv_type = drv3, .offset = offset3 }, \
286 }, \
287 .pull_type[0] = pull0, \
288 .pull_type[1] = pull1, \
289 .pull_type[2] = pull2, \
290 .pull_type[3] = pull3, \
291 }
292
293 /**
294 * struct rockchip_mux_recalced_data: represent a pin iomux data.
295 * @num: bank number.
296 * @pin: pin number.
297 * @bit: index at register.
298 * @reg: register offset.
299 * @mask: mask bit
300 */
301 struct rockchip_mux_recalced_data {
302 u8 num;
303 u8 pin;
304 u32 reg;
305 u8 bit;
306 u8 mask;
307 };
308
309 /**
310 * struct rockchip_mux_recalced_data: represent a pin iomux data.
311 * @bank_num: bank number.
312 * @pin: index at register or used to calc index.
313 * @func: the min pin.
314 * @route_offset: the max pin.
315 * @route_val: the register offset.
316 */
317 struct rockchip_mux_route_data {
318 u8 bank_num;
319 u8 pin;
320 u8 func;
321 u32 route_offset;
322 u32 route_val;
323 };
324
325 /**
326 */
327 struct rockchip_pin_ctrl {
328 struct rockchip_pin_bank *pin_banks;
329 u32 nr_banks;
330 u32 nr_pins;
331 char *label;
332 enum rockchip_pinctrl_type type;
333 int grf_mux_offset;
334 int pmu_mux_offset;
335 int grf_drv_offset;
336 int pmu_drv_offset;
337 struct rockchip_mux_recalced_data *iomux_recalced;
338 u32 niomux_recalced;
339 struct rockchip_mux_route_data *iomux_routes;
340 u32 niomux_routes;
341
342 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
343 int pin_num, struct regmap **regmap,
344 int *reg, u8 *bit);
345 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
346 int pin_num, struct regmap **regmap,
347 int *reg, u8 *bit);
348 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
349 int pin_num, struct regmap **regmap,
350 int *reg, u8 *bit);
351 };
352
353 struct rockchip_pin_config {
354 unsigned int func;
355 unsigned long *configs;
356 unsigned int nconfigs;
357 };
358
359 /**
360 * struct rockchip_pin_group: represent group of pins of a pinmux function.
361 * @name: name of the pin group, used to lookup the group.
362 * @pins: the pins included in this group.
363 * @npins: number of pins included in this group.
364 * @func: the mux function number to be programmed when selected.
365 * @configs: the config values to be set for each pin
366 * @nconfigs: number of configs for each pin
367 */
368 struct rockchip_pin_group {
369 const char *name;
370 unsigned int npins;
371 unsigned int *pins;
372 struct rockchip_pin_config *data;
373 };
374
375 /**
376 * struct rockchip_pmx_func: represent a pin function.
377 * @name: name of the pin function, used to lookup the function.
378 * @groups: one or more names of pin groups that provide this function.
379 * @num_groups: number of groups included in @groups.
380 */
381 struct rockchip_pmx_func {
382 const char *name;
383 const char **groups;
384 u8 ngroups;
385 };
386
387 struct rockchip_pinctrl {
388 struct regmap *regmap_base;
389 int reg_size;
390 struct regmap *regmap_pull;
391 struct regmap *regmap_pmu;
392 struct device *dev;
393 struct rockchip_pin_ctrl *ctrl;
394 struct pinctrl_desc pctl;
395 struct pinctrl_dev *pctl_dev;
396 struct rockchip_pin_group *groups;
397 unsigned int ngroups;
398 struct rockchip_pmx_func *functions;
399 unsigned int nfunctions;
400 };
401
402 static struct regmap_config rockchip_regmap_config = {
403 .reg_bits = 32,
404 .val_bits = 32,
405 .reg_stride = 4,
406 };
407
408 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
409 const struct rockchip_pinctrl *info,
410 const char *name)
411 {
412 int i;
413
414 for (i = 0; i < info->ngroups; i++) {
415 if (!strcmp(info->groups[i].name, name))
416 return &info->groups[i];
417 }
418
419 return NULL;
420 }
421
422 /*
423 * given a pin number that is local to a pin controller, find out the pin bank
424 * and the register base of the pin bank.
425 */
426 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
427 unsigned pin)
428 {
429 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
430
431 while (pin >= (b->pin_base + b->nr_pins))
432 b++;
433
434 return b;
435 }
436
437 static struct rockchip_pin_bank *bank_num_to_bank(
438 struct rockchip_pinctrl *info,
439 unsigned num)
440 {
441 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
442 int i;
443
444 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
445 if (b->bank_num == num)
446 return b;
447 }
448
449 return ERR_PTR(-EINVAL);
450 }
451
452 /*
453 * Pinctrl_ops handling
454 */
455
456 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
457 {
458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
459
460 return info->ngroups;
461 }
462
463 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
464 unsigned selector)
465 {
466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
467
468 return info->groups[selector].name;
469 }
470
471 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
472 unsigned selector, const unsigned **pins,
473 unsigned *npins)
474 {
475 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
476
477 if (selector >= info->ngroups)
478 return -EINVAL;
479
480 *pins = info->groups[selector].pins;
481 *npins = info->groups[selector].npins;
482
483 return 0;
484 }
485
486 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *np,
488 struct pinctrl_map **map, unsigned *num_maps)
489 {
490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
491 const struct rockchip_pin_group *grp;
492 struct pinctrl_map *new_map;
493 struct device_node *parent;
494 int map_num = 1;
495 int i;
496
497 /*
498 * first find the group of this node and check if we need to create
499 * config maps for pins
500 */
501 grp = pinctrl_name_to_group(info, np->name);
502 if (!grp) {
503 dev_err(info->dev, "unable to find group for node %s\n",
504 np->name);
505 return -EINVAL;
506 }
507
508 map_num += grp->npins;
509 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
510 GFP_KERNEL);
511 if (!new_map)
512 return -ENOMEM;
513
514 *map = new_map;
515 *num_maps = map_num;
516
517 /* create mux map */
518 parent = of_get_parent(np);
519 if (!parent) {
520 devm_kfree(pctldev->dev, new_map);
521 return -EINVAL;
522 }
523 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
524 new_map[0].data.mux.function = parent->name;
525 new_map[0].data.mux.group = np->name;
526 of_node_put(parent);
527
528 /* create config map */
529 new_map++;
530 for (i = 0; i < grp->npins; i++) {
531 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
532 new_map[i].data.configs.group_or_pin =
533 pin_get_name(pctldev, grp->pins[i]);
534 new_map[i].data.configs.configs = grp->data[i].configs;
535 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
536 }
537
538 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
539 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
540
541 return 0;
542 }
543
544 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
545 struct pinctrl_map *map, unsigned num_maps)
546 {
547 }
548
549 static const struct pinctrl_ops rockchip_pctrl_ops = {
550 .get_groups_count = rockchip_get_groups_count,
551 .get_group_name = rockchip_get_group_name,
552 .get_group_pins = rockchip_get_group_pins,
553 .dt_node_to_map = rockchip_dt_node_to_map,
554 .dt_free_map = rockchip_dt_free_map,
555 };
556
557 /*
558 * Hardware access
559 */
560
561 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
562 {
563 .num = 1,
564 .pin = 0,
565 .reg = 0x418,
566 .bit = 0,
567 .mask = 0x3
568 }, {
569 .num = 1,
570 .pin = 1,
571 .reg = 0x418,
572 .bit = 2,
573 .mask = 0x3
574 }, {
575 .num = 1,
576 .pin = 2,
577 .reg = 0x418,
578 .bit = 4,
579 .mask = 0x3
580 }, {
581 .num = 1,
582 .pin = 3,
583 .reg = 0x418,
584 .bit = 6,
585 .mask = 0x3
586 }, {
587 .num = 1,
588 .pin = 4,
589 .reg = 0x418,
590 .bit = 8,
591 .mask = 0x3
592 }, {
593 .num = 1,
594 .pin = 5,
595 .reg = 0x418,
596 .bit = 10,
597 .mask = 0x3
598 }, {
599 .num = 1,
600 .pin = 6,
601 .reg = 0x418,
602 .bit = 12,
603 .mask = 0x3
604 }, {
605 .num = 1,
606 .pin = 7,
607 .reg = 0x418,
608 .bit = 14,
609 .mask = 0x3
610 }, {
611 .num = 1,
612 .pin = 8,
613 .reg = 0x41c,
614 .bit = 0,
615 .mask = 0x3
616 }, {
617 .num = 1,
618 .pin = 9,
619 .reg = 0x41c,
620 .bit = 2,
621 .mask = 0x3
622 },
623 };
624
625 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
626 {
627 .num = 2,
628 .pin = 20,
629 .reg = 0xe8,
630 .bit = 0,
631 .mask = 0x7
632 }, {
633 .num = 2,
634 .pin = 21,
635 .reg = 0xe8,
636 .bit = 4,
637 .mask = 0x7
638 }, {
639 .num = 2,
640 .pin = 22,
641 .reg = 0xe8,
642 .bit = 8,
643 .mask = 0x7
644 }, {
645 .num = 2,
646 .pin = 23,
647 .reg = 0xe8,
648 .bit = 12,
649 .mask = 0x7
650 }, {
651 .num = 2,
652 .pin = 24,
653 .reg = 0xd4,
654 .bit = 12,
655 .mask = 0x7
656 },
657 };
658
659 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
660 {
661 .num = 2,
662 .pin = 12,
663 .reg = 0x24,
664 .bit = 8,
665 .mask = 0x3
666 }, {
667 .num = 2,
668 .pin = 15,
669 .reg = 0x28,
670 .bit = 0,
671 .mask = 0x7
672 }, {
673 .num = 2,
674 .pin = 23,
675 .reg = 0x30,
676 .bit = 14,
677 .mask = 0x3
678 },
679 };
680
681 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
682 int *reg, u8 *bit, int *mask)
683 {
684 struct rockchip_pinctrl *info = bank->drvdata;
685 struct rockchip_pin_ctrl *ctrl = info->ctrl;
686 struct rockchip_mux_recalced_data *data;
687 int i;
688
689 for (i = 0; i < ctrl->niomux_recalced; i++) {
690 data = &ctrl->iomux_recalced[i];
691 if (data->num == bank->bank_num &&
692 data->pin == pin)
693 break;
694 }
695
696 if (i >= ctrl->niomux_recalced)
697 return;
698
699 *reg = data->reg;
700 *mask = data->mask;
701 *bit = data->bit;
702 }
703
704 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
705 {
706 /* spi-0 */
707 .bank_num = 1,
708 .pin = 10,
709 .func = 1,
710 .route_offset = 0x144,
711 .route_val = BIT(16 + 3) | BIT(16 + 4),
712 }, {
713 /* spi-1 */
714 .bank_num = 1,
715 .pin = 27,
716 .func = 3,
717 .route_offset = 0x144,
718 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
719 }, {
720 /* spi-2 */
721 .bank_num = 0,
722 .pin = 13,
723 .func = 2,
724 .route_offset = 0x144,
725 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
726 }, {
727 /* i2s-0 */
728 .bank_num = 1,
729 .pin = 5,
730 .func = 1,
731 .route_offset = 0x144,
732 .route_val = BIT(16 + 5),
733 }, {
734 /* i2s-1 */
735 .bank_num = 0,
736 .pin = 14,
737 .func = 1,
738 .route_offset = 0x144,
739 .route_val = BIT(16 + 5) | BIT(5),
740 }, {
741 /* emmc-0 */
742 .bank_num = 1,
743 .pin = 22,
744 .func = 2,
745 .route_offset = 0x144,
746 .route_val = BIT(16 + 6),
747 }, {
748 /* emmc-1 */
749 .bank_num = 2,
750 .pin = 4,
751 .func = 2,
752 .route_offset = 0x144,
753 .route_val = BIT(16 + 6) | BIT(6),
754 },
755 };
756
757 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
758 {
759 /* pwm0-0 */
760 .bank_num = 0,
761 .pin = 26,
762 .func = 1,
763 .route_offset = 0x50,
764 .route_val = BIT(16),
765 }, {
766 /* pwm0-1 */
767 .bank_num = 3,
768 .pin = 21,
769 .func = 1,
770 .route_offset = 0x50,
771 .route_val = BIT(16) | BIT(0),
772 }, {
773 /* pwm1-0 */
774 .bank_num = 0,
775 .pin = 27,
776 .func = 1,
777 .route_offset = 0x50,
778 .route_val = BIT(16 + 1),
779 }, {
780 /* pwm1-1 */
781 .bank_num = 0,
782 .pin = 30,
783 .func = 2,
784 .route_offset = 0x50,
785 .route_val = BIT(16 + 1) | BIT(1),
786 }, {
787 /* pwm2-0 */
788 .bank_num = 0,
789 .pin = 28,
790 .func = 1,
791 .route_offset = 0x50,
792 .route_val = BIT(16 + 2),
793 }, {
794 /* pwm2-1 */
795 .bank_num = 1,
796 .pin = 12,
797 .func = 2,
798 .route_offset = 0x50,
799 .route_val = BIT(16 + 2) | BIT(2),
800 }, {
801 /* pwm3-0 */
802 .bank_num = 3,
803 .pin = 26,
804 .func = 1,
805 .route_offset = 0x50,
806 .route_val = BIT(16 + 3),
807 }, {
808 /* pwm3-1 */
809 .bank_num = 1,
810 .pin = 11,
811 .func = 2,
812 .route_offset = 0x50,
813 .route_val = BIT(16 + 3) | BIT(3),
814 }, {
815 /* sdio-0_d0 */
816 .bank_num = 1,
817 .pin = 1,
818 .func = 1,
819 .route_offset = 0x50,
820 .route_val = BIT(16 + 4),
821 }, {
822 /* sdio-1_d0 */
823 .bank_num = 3,
824 .pin = 2,
825 .func = 1,
826 .route_offset = 0x50,
827 .route_val = BIT(16 + 4) | BIT(4),
828 }, {
829 /* spi-0_rx */
830 .bank_num = 0,
831 .pin = 13,
832 .func = 2,
833 .route_offset = 0x50,
834 .route_val = BIT(16 + 5),
835 }, {
836 /* spi-1_rx */
837 .bank_num = 2,
838 .pin = 0,
839 .func = 2,
840 .route_offset = 0x50,
841 .route_val = BIT(16 + 5) | BIT(5),
842 }, {
843 /* emmc-0_cmd */
844 .bank_num = 1,
845 .pin = 22,
846 .func = 2,
847 .route_offset = 0x50,
848 .route_val = BIT(16 + 7),
849 }, {
850 /* emmc-1_cmd */
851 .bank_num = 2,
852 .pin = 4,
853 .func = 2,
854 .route_offset = 0x50,
855 .route_val = BIT(16 + 7) | BIT(7),
856 }, {
857 /* uart2-0_rx */
858 .bank_num = 1,
859 .pin = 19,
860 .func = 2,
861 .route_offset = 0x50,
862 .route_val = BIT(16 + 8),
863 }, {
864 /* uart2-1_rx */
865 .bank_num = 1,
866 .pin = 10,
867 .func = 2,
868 .route_offset = 0x50,
869 .route_val = BIT(16 + 8) | BIT(8),
870 }, {
871 /* uart1-0_rx */
872 .bank_num = 1,
873 .pin = 10,
874 .func = 1,
875 .route_offset = 0x50,
876 .route_val = BIT(16 + 11),
877 }, {
878 /* uart1-1_rx */
879 .bank_num = 3,
880 .pin = 13,
881 .func = 1,
882 .route_offset = 0x50,
883 .route_val = BIT(16 + 11) | BIT(11),
884 },
885 };
886
887 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
888 {
889 /* uart2dbg_rxm0 */
890 .bank_num = 1,
891 .pin = 1,
892 .func = 2,
893 .route_offset = 0x50,
894 .route_val = BIT(16) | BIT(16 + 1),
895 }, {
896 /* uart2dbg_rxm1 */
897 .bank_num = 2,
898 .pin = 1,
899 .func = 1,
900 .route_offset = 0x50,
901 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
902 }, {
903 /* gmac-m1-optimized_rxd0 */
904 .bank_num = 1,
905 .pin = 11,
906 .func = 2,
907 .route_offset = 0x50,
908 .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10),
909 }, {
910 /* pdm_sdi0m0 */
911 .bank_num = 2,
912 .pin = 19,
913 .func = 2,
914 .route_offset = 0x50,
915 .route_val = BIT(16 + 3),
916 }, {
917 /* pdm_sdi0m1 */
918 .bank_num = 1,
919 .pin = 23,
920 .func = 3,
921 .route_offset = 0x50,
922 .route_val = BIT(16 + 3) | BIT(3),
923 }, {
924 /* spi_rxdm2 */
925 .bank_num = 3,
926 .pin = 2,
927 .func = 4,
928 .route_offset = 0x50,
929 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
930 }, {
931 /* i2s2_sdim0 */
932 .bank_num = 1,
933 .pin = 24,
934 .func = 1,
935 .route_offset = 0x50,
936 .route_val = BIT(16 + 6),
937 }, {
938 /* i2s2_sdim1 */
939 .bank_num = 3,
940 .pin = 2,
941 .func = 6,
942 .route_offset = 0x50,
943 .route_val = BIT(16 + 6) | BIT(6),
944 }, {
945 /* card_iom1 */
946 .bank_num = 2,
947 .pin = 22,
948 .func = 3,
949 .route_offset = 0x50,
950 .route_val = BIT(16 + 7) | BIT(7),
951 }, {
952 /* tsp_d5m1 */
953 .bank_num = 2,
954 .pin = 16,
955 .func = 3,
956 .route_offset = 0x50,
957 .route_val = BIT(16 + 8) | BIT(8),
958 }, {
959 /* cif_data5m1 */
960 .bank_num = 2,
961 .pin = 16,
962 .func = 4,
963 .route_offset = 0x50,
964 .route_val = BIT(16 + 9) | BIT(9),
965 },
966 };
967
968 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
969 {
970 /* uart2dbga_rx */
971 .bank_num = 4,
972 .pin = 8,
973 .func = 2,
974 .route_offset = 0xe21c,
975 .route_val = BIT(16 + 10) | BIT(16 + 11),
976 }, {
977 /* uart2dbgb_rx */
978 .bank_num = 4,
979 .pin = 16,
980 .func = 2,
981 .route_offset = 0xe21c,
982 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
983 }, {
984 /* uart2dbgc_rx */
985 .bank_num = 4,
986 .pin = 19,
987 .func = 1,
988 .route_offset = 0xe21c,
989 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
990 }, {
991 /* pcie_clkreqn */
992 .bank_num = 2,
993 .pin = 26,
994 .func = 2,
995 .route_offset = 0xe21c,
996 .route_val = BIT(16 + 14),
997 }, {
998 /* pcie_clkreqnb */
999 .bank_num = 4,
1000 .pin = 24,
1001 .func = 1,
1002 .route_offset = 0xe21c,
1003 .route_val = BIT(16 + 14) | BIT(14),
1004 },
1005 };
1006
1007 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1008 int mux, u32 *reg, u32 *value)
1009 {
1010 struct rockchip_pinctrl *info = bank->drvdata;
1011 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1012 struct rockchip_mux_route_data *data;
1013 int i;
1014
1015 for (i = 0; i < ctrl->niomux_routes; i++) {
1016 data = &ctrl->iomux_routes[i];
1017 if ((data->bank_num == bank->bank_num) &&
1018 (data->pin == pin) && (data->func == mux))
1019 break;
1020 }
1021
1022 if (i >= ctrl->niomux_routes)
1023 return false;
1024
1025 *reg = data->route_offset;
1026 *value = data->route_val;
1027
1028 return true;
1029 }
1030
1031 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1032 {
1033 struct rockchip_pinctrl *info = bank->drvdata;
1034 int iomux_num = (pin / 8);
1035 struct regmap *regmap;
1036 unsigned int val;
1037 int reg, ret, mask, mux_type;
1038 u8 bit;
1039
1040 if (iomux_num > 3)
1041 return -EINVAL;
1042
1043 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1044 dev_err(info->dev, "pin %d is unrouted\n", pin);
1045 return -EINVAL;
1046 }
1047
1048 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1049 return RK_FUNC_GPIO;
1050
1051 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1052 ? info->regmap_pmu : info->regmap_base;
1053
1054 /* get basic quadrupel of mux registers and the correct reg inside */
1055 mux_type = bank->iomux[iomux_num].type;
1056 reg = bank->iomux[iomux_num].offset;
1057 if (mux_type & IOMUX_WIDTH_4BIT) {
1058 if ((pin % 8) >= 4)
1059 reg += 0x4;
1060 bit = (pin % 4) * 4;
1061 mask = 0xf;
1062 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1063 if ((pin % 8) >= 5)
1064 reg += 0x4;
1065 bit = (pin % 8 % 5) * 3;
1066 mask = 0x7;
1067 } else {
1068 bit = (pin % 8) * 2;
1069 mask = 0x3;
1070 }
1071
1072 if (bank->recalced_mask & BIT(pin))
1073 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1074
1075 ret = regmap_read(regmap, reg, &val);
1076 if (ret)
1077 return ret;
1078
1079 return ((val >> bit) & mask);
1080 }
1081
1082 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1083 int pin, int mux)
1084 {
1085 struct rockchip_pinctrl *info = bank->drvdata;
1086 int iomux_num = (pin / 8);
1087
1088 if (iomux_num > 3)
1089 return -EINVAL;
1090
1091 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1092 dev_err(info->dev, "pin %d is unrouted\n", pin);
1093 return -EINVAL;
1094 }
1095
1096 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1097 if (mux != RK_FUNC_GPIO) {
1098 dev_err(info->dev,
1099 "pin %d only supports a gpio mux\n", pin);
1100 return -ENOTSUPP;
1101 }
1102 }
1103
1104 return 0;
1105 }
1106
1107 /*
1108 * Set a new mux function for a pin.
1109 *
1110 * The register is divided into the upper and lower 16 bit. When changing
1111 * a value, the previous register value is not read and changed. Instead
1112 * it seems the changed bits are marked in the upper 16 bit, while the
1113 * changed value gets set in the same offset in the lower 16 bit.
1114 * All pin settings seem to be 2 bit wide in both the upper and lower
1115 * parts.
1116 * @bank: pin bank to change
1117 * @pin: pin to change
1118 * @mux: new mux function to set
1119 */
1120 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1121 {
1122 struct rockchip_pinctrl *info = bank->drvdata;
1123 int iomux_num = (pin / 8);
1124 struct regmap *regmap;
1125 int reg, ret, mask, mux_type;
1126 u8 bit;
1127 u32 data, rmask, route_reg, route_val;
1128
1129 ret = rockchip_verify_mux(bank, pin, mux);
1130 if (ret < 0)
1131 return ret;
1132
1133 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1134 return 0;
1135
1136 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1137 bank->bank_num, pin, mux);
1138
1139 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1140 ? info->regmap_pmu : info->regmap_base;
1141
1142 /* get basic quadrupel of mux registers and the correct reg inside */
1143 mux_type = bank->iomux[iomux_num].type;
1144 reg = bank->iomux[iomux_num].offset;
1145 if (mux_type & IOMUX_WIDTH_4BIT) {
1146 if ((pin % 8) >= 4)
1147 reg += 0x4;
1148 bit = (pin % 4) * 4;
1149 mask = 0xf;
1150 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1151 if ((pin % 8) >= 5)
1152 reg += 0x4;
1153 bit = (pin % 8 % 5) * 3;
1154 mask = 0x7;
1155 } else {
1156 bit = (pin % 8) * 2;
1157 mask = 0x3;
1158 }
1159
1160 if (bank->recalced_mask & BIT(pin))
1161 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1162
1163 if (bank->route_mask & BIT(pin)) {
1164 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1165 &route_val)) {
1166 ret = regmap_write(regmap, route_reg, route_val);
1167 if (ret)
1168 return ret;
1169 }
1170 }
1171
1172 data = (mask << (bit + 16));
1173 rmask = data | (data >> 16);
1174 data |= (mux & mask) << bit;
1175 ret = regmap_update_bits(regmap, reg, rmask, data);
1176
1177 return ret;
1178 }
1179
1180 #define RV1108_PULL_PMU_OFFSET 0x10
1181 #define RV1108_PULL_OFFSET 0x110
1182 #define RV1108_PULL_PINS_PER_REG 8
1183 #define RV1108_PULL_BITS_PER_PIN 2
1184 #define RV1108_PULL_BANK_STRIDE 16
1185
1186 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1187 int pin_num, struct regmap **regmap,
1188 int *reg, u8 *bit)
1189 {
1190 struct rockchip_pinctrl *info = bank->drvdata;
1191
1192 /* The first 24 pins of the first bank are located in PMU */
1193 if (bank->bank_num == 0) {
1194 *regmap = info->regmap_pmu;
1195 *reg = RV1108_PULL_PMU_OFFSET;
1196 } else {
1197 *reg = RV1108_PULL_OFFSET;
1198 *regmap = info->regmap_base;
1199 /* correct the offset, as we're starting with the 2nd bank */
1200 *reg -= 0x10;
1201 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1202 }
1203
1204 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1205 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1206 *bit *= RV1108_PULL_BITS_PER_PIN;
1207 }
1208
1209 #define RV1108_DRV_PMU_OFFSET 0x20
1210 #define RV1108_DRV_GRF_OFFSET 0x210
1211 #define RV1108_DRV_BITS_PER_PIN 2
1212 #define RV1108_DRV_PINS_PER_REG 8
1213 #define RV1108_DRV_BANK_STRIDE 16
1214
1215 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1216 int pin_num, struct regmap **regmap,
1217 int *reg, u8 *bit)
1218 {
1219 struct rockchip_pinctrl *info = bank->drvdata;
1220
1221 /* The first 24 pins of the first bank are located in PMU */
1222 if (bank->bank_num == 0) {
1223 *regmap = info->regmap_pmu;
1224 *reg = RV1108_DRV_PMU_OFFSET;
1225 } else {
1226 *regmap = info->regmap_base;
1227 *reg = RV1108_DRV_GRF_OFFSET;
1228
1229 /* correct the offset, as we're starting with the 2nd bank */
1230 *reg -= 0x10;
1231 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1232 }
1233
1234 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1235 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1236 *bit *= RV1108_DRV_BITS_PER_PIN;
1237 }
1238
1239 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1240 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1241 #define RV1108_SCHMITT_BANK_STRIDE 8
1242 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1243 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1244
1245 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1246 int pin_num,
1247 struct regmap **regmap,
1248 int *reg, u8 *bit)
1249 {
1250 struct rockchip_pinctrl *info = bank->drvdata;
1251 int pins_per_reg;
1252
1253 if (bank->bank_num == 0) {
1254 *regmap = info->regmap_pmu;
1255 *reg = RV1108_SCHMITT_PMU_OFFSET;
1256 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1257 } else {
1258 *regmap = info->regmap_base;
1259 *reg = RV1108_SCHMITT_GRF_OFFSET;
1260 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1261 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1262 }
1263 *reg += ((pin_num / pins_per_reg) * 4);
1264 *bit = pin_num % pins_per_reg;
1265
1266 return 0;
1267 }
1268
1269 #define RK2928_PULL_OFFSET 0x118
1270 #define RK2928_PULL_PINS_PER_REG 16
1271 #define RK2928_PULL_BANK_STRIDE 8
1272
1273 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1274 int pin_num, struct regmap **regmap,
1275 int *reg, u8 *bit)
1276 {
1277 struct rockchip_pinctrl *info = bank->drvdata;
1278
1279 *regmap = info->regmap_base;
1280 *reg = RK2928_PULL_OFFSET;
1281 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1282 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1283
1284 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1285 };
1286
1287 #define RK3128_PULL_OFFSET 0x118
1288
1289 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1290 int pin_num, struct regmap **regmap,
1291 int *reg, u8 *bit)
1292 {
1293 struct rockchip_pinctrl *info = bank->drvdata;
1294
1295 *regmap = info->regmap_base;
1296 *reg = RK3128_PULL_OFFSET;
1297 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1298 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1299
1300 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1301 }
1302
1303 #define RK3188_PULL_OFFSET 0x164
1304 #define RK3188_PULL_BITS_PER_PIN 2
1305 #define RK3188_PULL_PINS_PER_REG 8
1306 #define RK3188_PULL_BANK_STRIDE 16
1307 #define RK3188_PULL_PMU_OFFSET 0x64
1308
1309 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1310 int pin_num, struct regmap **regmap,
1311 int *reg, u8 *bit)
1312 {
1313 struct rockchip_pinctrl *info = bank->drvdata;
1314
1315 /* The first 12 pins of the first bank are located elsewhere */
1316 if (bank->bank_num == 0 && pin_num < 12) {
1317 *regmap = info->regmap_pmu ? info->regmap_pmu
1318 : bank->regmap_pull;
1319 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1320 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1321 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1322 *bit *= RK3188_PULL_BITS_PER_PIN;
1323 } else {
1324 *regmap = info->regmap_pull ? info->regmap_pull
1325 : info->regmap_base;
1326 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1327
1328 /* correct the offset, as it is the 2nd pull register */
1329 *reg -= 4;
1330 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1331 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1332
1333 /*
1334 * The bits in these registers have an inverse ordering
1335 * with the lowest pin being in bits 15:14 and the highest
1336 * pin in bits 1:0
1337 */
1338 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1339 *bit *= RK3188_PULL_BITS_PER_PIN;
1340 }
1341 }
1342
1343 #define RK3288_PULL_OFFSET 0x140
1344 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1345 int pin_num, struct regmap **regmap,
1346 int *reg, u8 *bit)
1347 {
1348 struct rockchip_pinctrl *info = bank->drvdata;
1349
1350 /* The first 24 pins of the first bank are located in PMU */
1351 if (bank->bank_num == 0) {
1352 *regmap = info->regmap_pmu;
1353 *reg = RK3188_PULL_PMU_OFFSET;
1354
1355 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1356 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1357 *bit *= RK3188_PULL_BITS_PER_PIN;
1358 } else {
1359 *regmap = info->regmap_base;
1360 *reg = RK3288_PULL_OFFSET;
1361
1362 /* correct the offset, as we're starting with the 2nd bank */
1363 *reg -= 0x10;
1364 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1365 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1366
1367 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1368 *bit *= RK3188_PULL_BITS_PER_PIN;
1369 }
1370 }
1371
1372 #define RK3288_DRV_PMU_OFFSET 0x70
1373 #define RK3288_DRV_GRF_OFFSET 0x1c0
1374 #define RK3288_DRV_BITS_PER_PIN 2
1375 #define RK3288_DRV_PINS_PER_REG 8
1376 #define RK3288_DRV_BANK_STRIDE 16
1377
1378 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1379 int pin_num, struct regmap **regmap,
1380 int *reg, u8 *bit)
1381 {
1382 struct rockchip_pinctrl *info = bank->drvdata;
1383
1384 /* The first 24 pins of the first bank are located in PMU */
1385 if (bank->bank_num == 0) {
1386 *regmap = info->regmap_pmu;
1387 *reg = RK3288_DRV_PMU_OFFSET;
1388
1389 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1390 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1391 *bit *= RK3288_DRV_BITS_PER_PIN;
1392 } else {
1393 *regmap = info->regmap_base;
1394 *reg = RK3288_DRV_GRF_OFFSET;
1395
1396 /* correct the offset, as we're starting with the 2nd bank */
1397 *reg -= 0x10;
1398 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1399 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1400
1401 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1402 *bit *= RK3288_DRV_BITS_PER_PIN;
1403 }
1404 }
1405
1406 #define RK3228_PULL_OFFSET 0x100
1407
1408 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1409 int pin_num, struct regmap **regmap,
1410 int *reg, u8 *bit)
1411 {
1412 struct rockchip_pinctrl *info = bank->drvdata;
1413
1414 *regmap = info->regmap_base;
1415 *reg = RK3228_PULL_OFFSET;
1416 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1417 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1418
1419 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1420 *bit *= RK3188_PULL_BITS_PER_PIN;
1421 }
1422
1423 #define RK3228_DRV_GRF_OFFSET 0x200
1424
1425 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1426 int pin_num, struct regmap **regmap,
1427 int *reg, u8 *bit)
1428 {
1429 struct rockchip_pinctrl *info = bank->drvdata;
1430
1431 *regmap = info->regmap_base;
1432 *reg = RK3228_DRV_GRF_OFFSET;
1433 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1434 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1435
1436 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1437 *bit *= RK3288_DRV_BITS_PER_PIN;
1438 }
1439
1440 #define RK3368_PULL_GRF_OFFSET 0x100
1441 #define RK3368_PULL_PMU_OFFSET 0x10
1442
1443 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1444 int pin_num, struct regmap **regmap,
1445 int *reg, u8 *bit)
1446 {
1447 struct rockchip_pinctrl *info = bank->drvdata;
1448
1449 /* The first 32 pins of the first bank are located in PMU */
1450 if (bank->bank_num == 0) {
1451 *regmap = info->regmap_pmu;
1452 *reg = RK3368_PULL_PMU_OFFSET;
1453
1454 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1455 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1456 *bit *= RK3188_PULL_BITS_PER_PIN;
1457 } else {
1458 *regmap = info->regmap_base;
1459 *reg = RK3368_PULL_GRF_OFFSET;
1460
1461 /* correct the offset, as we're starting with the 2nd bank */
1462 *reg -= 0x10;
1463 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1464 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1465
1466 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1467 *bit *= RK3188_PULL_BITS_PER_PIN;
1468 }
1469 }
1470
1471 #define RK3368_DRV_PMU_OFFSET 0x20
1472 #define RK3368_DRV_GRF_OFFSET 0x200
1473
1474 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1475 int pin_num, struct regmap **regmap,
1476 int *reg, u8 *bit)
1477 {
1478 struct rockchip_pinctrl *info = bank->drvdata;
1479
1480 /* The first 32 pins of the first bank are located in PMU */
1481 if (bank->bank_num == 0) {
1482 *regmap = info->regmap_pmu;
1483 *reg = RK3368_DRV_PMU_OFFSET;
1484
1485 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1486 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1487 *bit *= RK3288_DRV_BITS_PER_PIN;
1488 } else {
1489 *regmap = info->regmap_base;
1490 *reg = RK3368_DRV_GRF_OFFSET;
1491
1492 /* correct the offset, as we're starting with the 2nd bank */
1493 *reg -= 0x10;
1494 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1495 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1496
1497 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1498 *bit *= RK3288_DRV_BITS_PER_PIN;
1499 }
1500 }
1501
1502 #define RK3399_PULL_GRF_OFFSET 0xe040
1503 #define RK3399_PULL_PMU_OFFSET 0x40
1504 #define RK3399_DRV_3BITS_PER_PIN 3
1505
1506 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1507 int pin_num, struct regmap **regmap,
1508 int *reg, u8 *bit)
1509 {
1510 struct rockchip_pinctrl *info = bank->drvdata;
1511
1512 /* The bank0:16 and bank1:32 pins are located in PMU */
1513 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1514 *regmap = info->regmap_pmu;
1515 *reg = RK3399_PULL_PMU_OFFSET;
1516
1517 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1518
1519 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1520 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1521 *bit *= RK3188_PULL_BITS_PER_PIN;
1522 } else {
1523 *regmap = info->regmap_base;
1524 *reg = RK3399_PULL_GRF_OFFSET;
1525
1526 /* correct the offset, as we're starting with the 3rd bank */
1527 *reg -= 0x20;
1528 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1529 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1530
1531 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1532 *bit *= RK3188_PULL_BITS_PER_PIN;
1533 }
1534 }
1535
1536 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1537 int pin_num, struct regmap **regmap,
1538 int *reg, u8 *bit)
1539 {
1540 struct rockchip_pinctrl *info = bank->drvdata;
1541 int drv_num = (pin_num / 8);
1542
1543 /* The bank0:16 and bank1:32 pins are located in PMU */
1544 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1545 *regmap = info->regmap_pmu;
1546 else
1547 *regmap = info->regmap_base;
1548
1549 *reg = bank->drv[drv_num].offset;
1550 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1551 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1552 *bit = (pin_num % 8) * 3;
1553 else
1554 *bit = (pin_num % 8) * 2;
1555 }
1556
1557 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1558 { 2, 4, 8, 12, -1, -1, -1, -1 },
1559 { 3, 6, 9, 12, -1, -1, -1, -1 },
1560 { 5, 10, 15, 20, -1, -1, -1, -1 },
1561 { 4, 6, 8, 10, 12, 14, 16, 18 },
1562 { 4, 7, 10, 13, 16, 19, 22, 26 }
1563 };
1564
1565 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1566 int pin_num)
1567 {
1568 struct rockchip_pinctrl *info = bank->drvdata;
1569 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1570 struct regmap *regmap;
1571 int reg, ret;
1572 u32 data, temp, rmask_bits;
1573 u8 bit;
1574 int drv_type = bank->drv[pin_num / 8].drv_type;
1575
1576 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1577
1578 switch (drv_type) {
1579 case DRV_TYPE_IO_1V8_3V0_AUTO:
1580 case DRV_TYPE_IO_3V3_ONLY:
1581 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1582 switch (bit) {
1583 case 0 ... 12:
1584 /* regular case, nothing to do */
1585 break;
1586 case 15:
1587 /*
1588 * drive-strength offset is special, as it is
1589 * spread over 2 registers
1590 */
1591 ret = regmap_read(regmap, reg, &data);
1592 if (ret)
1593 return ret;
1594
1595 ret = regmap_read(regmap, reg + 0x4, &temp);
1596 if (ret)
1597 return ret;
1598
1599 /*
1600 * the bit data[15] contains bit 0 of the value
1601 * while temp[1:0] contains bits 2 and 1
1602 */
1603 data >>= 15;
1604 temp &= 0x3;
1605 temp <<= 1;
1606 data |= temp;
1607
1608 return rockchip_perpin_drv_list[drv_type][data];
1609 case 18 ... 21:
1610 /* setting fully enclosed in the second register */
1611 reg += 4;
1612 bit -= 16;
1613 break;
1614 default:
1615 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1616 bit, drv_type);
1617 return -EINVAL;
1618 }
1619
1620 break;
1621 case DRV_TYPE_IO_DEFAULT:
1622 case DRV_TYPE_IO_1V8_OR_3V0:
1623 case DRV_TYPE_IO_1V8_ONLY:
1624 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1625 break;
1626 default:
1627 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1628 drv_type);
1629 return -EINVAL;
1630 }
1631
1632 ret = regmap_read(regmap, reg, &data);
1633 if (ret)
1634 return ret;
1635
1636 data >>= bit;
1637 data &= (1 << rmask_bits) - 1;
1638
1639 return rockchip_perpin_drv_list[drv_type][data];
1640 }
1641
1642 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1643 int pin_num, int strength)
1644 {
1645 struct rockchip_pinctrl *info = bank->drvdata;
1646 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1647 struct regmap *regmap;
1648 int reg, ret, i;
1649 u32 data, rmask, rmask_bits, temp;
1650 u8 bit;
1651 int drv_type = bank->drv[pin_num / 8].drv_type;
1652
1653 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1654 bank->bank_num, pin_num, strength);
1655
1656 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1657
1658 ret = -EINVAL;
1659 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1660 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1661 ret = i;
1662 break;
1663 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1664 ret = rockchip_perpin_drv_list[drv_type][i];
1665 break;
1666 }
1667 }
1668
1669 if (ret < 0) {
1670 dev_err(info->dev, "unsupported driver strength %d\n",
1671 strength);
1672 return ret;
1673 }
1674
1675 switch (drv_type) {
1676 case DRV_TYPE_IO_1V8_3V0_AUTO:
1677 case DRV_TYPE_IO_3V3_ONLY:
1678 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1679 switch (bit) {
1680 case 0 ... 12:
1681 /* regular case, nothing to do */
1682 break;
1683 case 15:
1684 /*
1685 * drive-strength offset is special, as it is spread
1686 * over 2 registers, the bit data[15] contains bit 0
1687 * of the value while temp[1:0] contains bits 2 and 1
1688 */
1689 data = (ret & 0x1) << 15;
1690 temp = (ret >> 0x1) & 0x3;
1691
1692 rmask = BIT(15) | BIT(31);
1693 data |= BIT(31);
1694 ret = regmap_update_bits(regmap, reg, rmask, data);
1695 if (ret)
1696 return ret;
1697
1698 rmask = 0x3 | (0x3 << 16);
1699 temp |= (0x3 << 16);
1700 reg += 0x4;
1701 ret = regmap_update_bits(regmap, reg, rmask, temp);
1702
1703 return ret;
1704 case 18 ... 21:
1705 /* setting fully enclosed in the second register */
1706 reg += 4;
1707 bit -= 16;
1708 break;
1709 default:
1710 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1711 bit, drv_type);
1712 return -EINVAL;
1713 }
1714 break;
1715 case DRV_TYPE_IO_DEFAULT:
1716 case DRV_TYPE_IO_1V8_OR_3V0:
1717 case DRV_TYPE_IO_1V8_ONLY:
1718 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1719 break;
1720 default:
1721 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1722 drv_type);
1723 return -EINVAL;
1724 }
1725
1726 /* enable the write to the equivalent lower bits */
1727 data = ((1 << rmask_bits) - 1) << (bit + 16);
1728 rmask = data | (data >> 16);
1729 data |= (ret << bit);
1730
1731 ret = regmap_update_bits(regmap, reg, rmask, data);
1732
1733 return ret;
1734 }
1735
1736 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1737 {
1738 PIN_CONFIG_BIAS_DISABLE,
1739 PIN_CONFIG_BIAS_PULL_UP,
1740 PIN_CONFIG_BIAS_PULL_DOWN,
1741 PIN_CONFIG_BIAS_BUS_HOLD
1742 },
1743 {
1744 PIN_CONFIG_BIAS_DISABLE,
1745 PIN_CONFIG_BIAS_PULL_DOWN,
1746 PIN_CONFIG_BIAS_DISABLE,
1747 PIN_CONFIG_BIAS_PULL_UP
1748 },
1749 };
1750
1751 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1752 {
1753 struct rockchip_pinctrl *info = bank->drvdata;
1754 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1755 struct regmap *regmap;
1756 int reg, ret, pull_type;
1757 u8 bit;
1758 u32 data;
1759
1760 /* rk3066b does support any pulls */
1761 if (ctrl->type == RK3066B)
1762 return PIN_CONFIG_BIAS_DISABLE;
1763
1764 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1765
1766 ret = regmap_read(regmap, reg, &data);
1767 if (ret)
1768 return ret;
1769
1770 switch (ctrl->type) {
1771 case RK2928:
1772 case RK3128:
1773 return !(data & BIT(bit))
1774 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1775 : PIN_CONFIG_BIAS_DISABLE;
1776 case RV1108:
1777 case RK3188:
1778 case RK3288:
1779 case RK3368:
1780 case RK3399:
1781 pull_type = bank->pull_type[pin_num / 8];
1782 data >>= bit;
1783 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1784
1785 return rockchip_pull_list[pull_type][data];
1786 default:
1787 dev_err(info->dev, "unsupported pinctrl type\n");
1788 return -EINVAL;
1789 };
1790 }
1791
1792 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1793 int pin_num, int pull)
1794 {
1795 struct rockchip_pinctrl *info = bank->drvdata;
1796 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1797 struct regmap *regmap;
1798 int reg, ret, i, pull_type;
1799 u8 bit;
1800 u32 data, rmask;
1801
1802 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1803 bank->bank_num, pin_num, pull);
1804
1805 /* rk3066b does support any pulls */
1806 if (ctrl->type == RK3066B)
1807 return pull ? -EINVAL : 0;
1808
1809 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1810
1811 switch (ctrl->type) {
1812 case RK2928:
1813 case RK3128:
1814 data = BIT(bit + 16);
1815 if (pull == PIN_CONFIG_BIAS_DISABLE)
1816 data |= BIT(bit);
1817 ret = regmap_write(regmap, reg, data);
1818 break;
1819 case RV1108:
1820 case RK3188:
1821 case RK3288:
1822 case RK3368:
1823 case RK3399:
1824 pull_type = bank->pull_type[pin_num / 8];
1825 ret = -EINVAL;
1826 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1827 i++) {
1828 if (rockchip_pull_list[pull_type][i] == pull) {
1829 ret = i;
1830 break;
1831 }
1832 }
1833
1834 if (ret < 0) {
1835 dev_err(info->dev, "unsupported pull setting %d\n",
1836 pull);
1837 return ret;
1838 }
1839
1840 /* enable the write to the equivalent lower bits */
1841 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1842 rmask = data | (data >> 16);
1843 data |= (ret << bit);
1844
1845 ret = regmap_update_bits(regmap, reg, rmask, data);
1846 break;
1847 default:
1848 dev_err(info->dev, "unsupported pinctrl type\n");
1849 return -EINVAL;
1850 }
1851
1852 return ret;
1853 }
1854
1855 #define RK3328_SCHMITT_BITS_PER_PIN 1
1856 #define RK3328_SCHMITT_PINS_PER_REG 16
1857 #define RK3328_SCHMITT_BANK_STRIDE 8
1858 #define RK3328_SCHMITT_GRF_OFFSET 0x380
1859
1860 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1861 int pin_num,
1862 struct regmap **regmap,
1863 int *reg, u8 *bit)
1864 {
1865 struct rockchip_pinctrl *info = bank->drvdata;
1866
1867 *regmap = info->regmap_base;
1868 *reg = RK3328_SCHMITT_GRF_OFFSET;
1869
1870 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1871 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1872 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1873
1874 return 0;
1875 }
1876
1877 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1878 {
1879 struct rockchip_pinctrl *info = bank->drvdata;
1880 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1881 struct regmap *regmap;
1882 int reg, ret;
1883 u8 bit;
1884 u32 data;
1885
1886 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1887 if (ret)
1888 return ret;
1889
1890 ret = regmap_read(regmap, reg, &data);
1891 if (ret)
1892 return ret;
1893
1894 data >>= bit;
1895 return data & 0x1;
1896 }
1897
1898 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1899 int pin_num, int enable)
1900 {
1901 struct rockchip_pinctrl *info = bank->drvdata;
1902 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1903 struct regmap *regmap;
1904 int reg, ret;
1905 u8 bit;
1906 u32 data, rmask;
1907
1908 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1909 bank->bank_num, pin_num, enable);
1910
1911 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1912 if (ret)
1913 return ret;
1914
1915 /* enable the write to the equivalent lower bits */
1916 data = BIT(bit + 16) | (enable << bit);
1917 rmask = BIT(bit + 16) | BIT(bit);
1918
1919 return regmap_update_bits(regmap, reg, rmask, data);
1920 }
1921
1922 /*
1923 * Pinmux_ops handling
1924 */
1925
1926 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1927 {
1928 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1929
1930 return info->nfunctions;
1931 }
1932
1933 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1934 unsigned selector)
1935 {
1936 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1937
1938 return info->functions[selector].name;
1939 }
1940
1941 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1942 unsigned selector, const char * const **groups,
1943 unsigned * const num_groups)
1944 {
1945 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1946
1947 *groups = info->functions[selector].groups;
1948 *num_groups = info->functions[selector].ngroups;
1949
1950 return 0;
1951 }
1952
1953 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1954 unsigned group)
1955 {
1956 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1957 const unsigned int *pins = info->groups[group].pins;
1958 const struct rockchip_pin_config *data = info->groups[group].data;
1959 struct rockchip_pin_bank *bank;
1960 int cnt, ret = 0;
1961
1962 dev_dbg(info->dev, "enable function %s group %s\n",
1963 info->functions[selector].name, info->groups[group].name);
1964
1965 /*
1966 * for each pin in the pin group selected, program the correspoding pin
1967 * pin function number in the config register.
1968 */
1969 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1970 bank = pin_to_bank(info, pins[cnt]);
1971 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1972 data[cnt].func);
1973 if (ret)
1974 break;
1975 }
1976
1977 if (ret) {
1978 /* revert the already done pin settings */
1979 for (cnt--; cnt >= 0; cnt--)
1980 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1981
1982 return ret;
1983 }
1984
1985 return 0;
1986 }
1987
1988 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1989 {
1990 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1991 u32 data;
1992 int ret;
1993
1994 ret = clk_enable(bank->clk);
1995 if (ret < 0) {
1996 dev_err(bank->drvdata->dev,
1997 "failed to enable clock for bank %s\n", bank->name);
1998 return ret;
1999 }
2000 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2001 clk_disable(bank->clk);
2002
2003 return !(data & BIT(offset));
2004 }
2005
2006 /*
2007 * The calls to gpio_direction_output() and gpio_direction_input()
2008 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2009 * function called from the gpiolib interface).
2010 */
2011 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2012 int pin, bool input)
2013 {
2014 struct rockchip_pin_bank *bank;
2015 int ret;
2016 unsigned long flags;
2017 u32 data;
2018
2019 bank = gpiochip_get_data(chip);
2020
2021 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2022 if (ret < 0)
2023 return ret;
2024
2025 clk_enable(bank->clk);
2026 raw_spin_lock_irqsave(&bank->slock, flags);
2027
2028 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2029 /* set bit to 1 for output, 0 for input */
2030 if (!input)
2031 data |= BIT(pin);
2032 else
2033 data &= ~BIT(pin);
2034 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2035
2036 raw_spin_unlock_irqrestore(&bank->slock, flags);
2037 clk_disable(bank->clk);
2038
2039 return 0;
2040 }
2041
2042 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2043 struct pinctrl_gpio_range *range,
2044 unsigned offset, bool input)
2045 {
2046 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2047 struct gpio_chip *chip;
2048 int pin;
2049
2050 chip = range->gc;
2051 pin = offset - chip->base;
2052 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2053 offset, range->name, pin, input ? "input" : "output");
2054
2055 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2056 input);
2057 }
2058
2059 static const struct pinmux_ops rockchip_pmx_ops = {
2060 .get_functions_count = rockchip_pmx_get_funcs_count,
2061 .get_function_name = rockchip_pmx_get_func_name,
2062 .get_function_groups = rockchip_pmx_get_groups,
2063 .set_mux = rockchip_pmx_set,
2064 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2065 };
2066
2067 /*
2068 * Pinconf_ops handling
2069 */
2070
2071 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2072 enum pin_config_param pull)
2073 {
2074 switch (ctrl->type) {
2075 case RK2928:
2076 case RK3128:
2077 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2078 pull == PIN_CONFIG_BIAS_DISABLE);
2079 case RK3066B:
2080 return pull ? false : true;
2081 case RV1108:
2082 case RK3188:
2083 case RK3288:
2084 case RK3368:
2085 case RK3399:
2086 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2087 }
2088
2089 return false;
2090 }
2091
2092 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2093 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2094
2095 /* set the pin config settings for a specified pin */
2096 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2097 unsigned long *configs, unsigned num_configs)
2098 {
2099 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2100 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2101 enum pin_config_param param;
2102 u32 arg;
2103 int i;
2104 int rc;
2105
2106 for (i = 0; i < num_configs; i++) {
2107 param = pinconf_to_config_param(configs[i]);
2108 arg = pinconf_to_config_argument(configs[i]);
2109
2110 switch (param) {
2111 case PIN_CONFIG_BIAS_DISABLE:
2112 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2113 param);
2114 if (rc)
2115 return rc;
2116 break;
2117 case PIN_CONFIG_BIAS_PULL_UP:
2118 case PIN_CONFIG_BIAS_PULL_DOWN:
2119 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2120 case PIN_CONFIG_BIAS_BUS_HOLD:
2121 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2122 return -ENOTSUPP;
2123
2124 if (!arg)
2125 return -EINVAL;
2126
2127 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2128 param);
2129 if (rc)
2130 return rc;
2131 break;
2132 case PIN_CONFIG_OUTPUT:
2133 rockchip_gpio_set(&bank->gpio_chip,
2134 pin - bank->pin_base, arg);
2135 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2136 pin - bank->pin_base, false);
2137 if (rc)
2138 return rc;
2139 break;
2140 case PIN_CONFIG_DRIVE_STRENGTH:
2141 /* rk3288 is the first with per-pin drive-strength */
2142 if (!info->ctrl->drv_calc_reg)
2143 return -ENOTSUPP;
2144
2145 rc = rockchip_set_drive_perpin(bank,
2146 pin - bank->pin_base, arg);
2147 if (rc < 0)
2148 return rc;
2149 break;
2150 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2151 if (!info->ctrl->schmitt_calc_reg)
2152 return -ENOTSUPP;
2153
2154 rc = rockchip_set_schmitt(bank,
2155 pin - bank->pin_base, arg);
2156 if (rc < 0)
2157 return rc;
2158 break;
2159 default:
2160 return -ENOTSUPP;
2161 break;
2162 }
2163 } /* for each config */
2164
2165 return 0;
2166 }
2167
2168 /* get the pin config settings for a specified pin */
2169 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2170 unsigned long *config)
2171 {
2172 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2173 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2174 enum pin_config_param param = pinconf_to_config_param(*config);
2175 u16 arg;
2176 int rc;
2177
2178 switch (param) {
2179 case PIN_CONFIG_BIAS_DISABLE:
2180 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2181 return -EINVAL;
2182
2183 arg = 0;
2184 break;
2185 case PIN_CONFIG_BIAS_PULL_UP:
2186 case PIN_CONFIG_BIAS_PULL_DOWN:
2187 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2188 case PIN_CONFIG_BIAS_BUS_HOLD:
2189 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2190 return -ENOTSUPP;
2191
2192 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2193 return -EINVAL;
2194
2195 arg = 1;
2196 break;
2197 case PIN_CONFIG_OUTPUT:
2198 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2199 if (rc != RK_FUNC_GPIO)
2200 return -EINVAL;
2201
2202 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2203 if (rc < 0)
2204 return rc;
2205
2206 arg = rc ? 1 : 0;
2207 break;
2208 case PIN_CONFIG_DRIVE_STRENGTH:
2209 /* rk3288 is the first with per-pin drive-strength */
2210 if (!info->ctrl->drv_calc_reg)
2211 return -ENOTSUPP;
2212
2213 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2214 if (rc < 0)
2215 return rc;
2216
2217 arg = rc;
2218 break;
2219 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2220 if (!info->ctrl->schmitt_calc_reg)
2221 return -ENOTSUPP;
2222
2223 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2224 if (rc < 0)
2225 return rc;
2226
2227 arg = rc;
2228 break;
2229 default:
2230 return -ENOTSUPP;
2231 break;
2232 }
2233
2234 *config = pinconf_to_config_packed(param, arg);
2235
2236 return 0;
2237 }
2238
2239 static const struct pinconf_ops rockchip_pinconf_ops = {
2240 .pin_config_get = rockchip_pinconf_get,
2241 .pin_config_set = rockchip_pinconf_set,
2242 .is_generic = true,
2243 };
2244
2245 static const struct of_device_id rockchip_bank_match[] = {
2246 { .compatible = "rockchip,gpio-bank" },
2247 { .compatible = "rockchip,rk3188-gpio-bank0" },
2248 {},
2249 };
2250
2251 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2252 struct device_node *np)
2253 {
2254 struct device_node *child;
2255
2256 for_each_child_of_node(np, child) {
2257 if (of_match_node(rockchip_bank_match, child))
2258 continue;
2259
2260 info->nfunctions++;
2261 info->ngroups += of_get_child_count(child);
2262 }
2263 }
2264
2265 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2266 struct rockchip_pin_group *grp,
2267 struct rockchip_pinctrl *info,
2268 u32 index)
2269 {
2270 struct rockchip_pin_bank *bank;
2271 int size;
2272 const __be32 *list;
2273 int num;
2274 int i, j;
2275 int ret;
2276
2277 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
2278
2279 /* Initialise group */
2280 grp->name = np->name;
2281
2282 /*
2283 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2284 * do sanity check and calculate pins number
2285 */
2286 list = of_get_property(np, "rockchip,pins", &size);
2287 /* we do not check return since it's safe node passed down */
2288 size /= sizeof(*list);
2289 if (!size || size % 4) {
2290 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2291 return -EINVAL;
2292 }
2293
2294 grp->npins = size / 4;
2295
2296 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2297 GFP_KERNEL);
2298 grp->data = devm_kzalloc(info->dev, grp->npins *
2299 sizeof(struct rockchip_pin_config),
2300 GFP_KERNEL);
2301 if (!grp->pins || !grp->data)
2302 return -ENOMEM;
2303
2304 for (i = 0, j = 0; i < size; i += 4, j++) {
2305 const __be32 *phandle;
2306 struct device_node *np_config;
2307
2308 num = be32_to_cpu(*list++);
2309 bank = bank_num_to_bank(info, num);
2310 if (IS_ERR(bank))
2311 return PTR_ERR(bank);
2312
2313 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2314 grp->data[j].func = be32_to_cpu(*list++);
2315
2316 phandle = list++;
2317 if (!phandle)
2318 return -EINVAL;
2319
2320 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2321 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2322 &grp->data[j].configs, &grp->data[j].nconfigs);
2323 if (ret)
2324 return ret;
2325 }
2326
2327 return 0;
2328 }
2329
2330 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2331 struct rockchip_pinctrl *info,
2332 u32 index)
2333 {
2334 struct device_node *child;
2335 struct rockchip_pmx_func *func;
2336 struct rockchip_pin_group *grp;
2337 int ret;
2338 static u32 grp_index;
2339 u32 i = 0;
2340
2341 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2342
2343 func = &info->functions[index];
2344
2345 /* Initialise function */
2346 func->name = np->name;
2347 func->ngroups = of_get_child_count(np);
2348 if (func->ngroups <= 0)
2349 return 0;
2350
2351 func->groups = devm_kzalloc(info->dev,
2352 func->ngroups * sizeof(char *), GFP_KERNEL);
2353 if (!func->groups)
2354 return -ENOMEM;
2355
2356 for_each_child_of_node(np, child) {
2357 func->groups[i] = child->name;
2358 grp = &info->groups[grp_index++];
2359 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2360 if (ret) {
2361 of_node_put(child);
2362 return ret;
2363 }
2364 }
2365
2366 return 0;
2367 }
2368
2369 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2370 struct rockchip_pinctrl *info)
2371 {
2372 struct device *dev = &pdev->dev;
2373 struct device_node *np = dev->of_node;
2374 struct device_node *child;
2375 int ret;
2376 int i;
2377
2378 rockchip_pinctrl_child_count(info, np);
2379
2380 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2381 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2382
2383 info->functions = devm_kzalloc(dev, info->nfunctions *
2384 sizeof(struct rockchip_pmx_func),
2385 GFP_KERNEL);
2386 if (!info->functions) {
2387 dev_err(dev, "failed to allocate memory for function list\n");
2388 return -EINVAL;
2389 }
2390
2391 info->groups = devm_kzalloc(dev, info->ngroups *
2392 sizeof(struct rockchip_pin_group),
2393 GFP_KERNEL);
2394 if (!info->groups) {
2395 dev_err(dev, "failed allocate memory for ping group list\n");
2396 return -EINVAL;
2397 }
2398
2399 i = 0;
2400
2401 for_each_child_of_node(np, child) {
2402 if (of_match_node(rockchip_bank_match, child))
2403 continue;
2404
2405 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2406 if (ret) {
2407 dev_err(&pdev->dev, "failed to parse function\n");
2408 of_node_put(child);
2409 return ret;
2410 }
2411 }
2412
2413 return 0;
2414 }
2415
2416 static int rockchip_pinctrl_register(struct platform_device *pdev,
2417 struct rockchip_pinctrl *info)
2418 {
2419 struct pinctrl_desc *ctrldesc = &info->pctl;
2420 struct pinctrl_pin_desc *pindesc, *pdesc;
2421 struct rockchip_pin_bank *pin_bank;
2422 int pin, bank, ret;
2423 int k;
2424
2425 ctrldesc->name = "rockchip-pinctrl";
2426 ctrldesc->owner = THIS_MODULE;
2427 ctrldesc->pctlops = &rockchip_pctrl_ops;
2428 ctrldesc->pmxops = &rockchip_pmx_ops;
2429 ctrldesc->confops = &rockchip_pinconf_ops;
2430
2431 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2432 info->ctrl->nr_pins, GFP_KERNEL);
2433 if (!pindesc) {
2434 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2435 return -ENOMEM;
2436 }
2437 ctrldesc->pins = pindesc;
2438 ctrldesc->npins = info->ctrl->nr_pins;
2439
2440 pdesc = pindesc;
2441 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2442 pin_bank = &info->ctrl->pin_banks[bank];
2443 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2444 pdesc->number = k;
2445 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2446 pin_bank->name, pin);
2447 pdesc++;
2448 }
2449 }
2450
2451 ret = rockchip_pinctrl_parse_dt(pdev, info);
2452 if (ret)
2453 return ret;
2454
2455 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2456 if (IS_ERR(info->pctl_dev)) {
2457 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2458 return PTR_ERR(info->pctl_dev);
2459 }
2460
2461 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2462 pin_bank = &info->ctrl->pin_banks[bank];
2463 pin_bank->grange.name = pin_bank->name;
2464 pin_bank->grange.id = bank;
2465 pin_bank->grange.pin_base = pin_bank->pin_base;
2466 pin_bank->grange.base = pin_bank->gpio_chip.base;
2467 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2468 pin_bank->grange.gc = &pin_bank->gpio_chip;
2469 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2470 }
2471
2472 return 0;
2473 }
2474
2475 /*
2476 * GPIO handling
2477 */
2478
2479 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2480 {
2481 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2482 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2483 unsigned long flags;
2484 u32 data;
2485
2486 clk_enable(bank->clk);
2487 raw_spin_lock_irqsave(&bank->slock, flags);
2488
2489 data = readl(reg);
2490 data &= ~BIT(offset);
2491 if (value)
2492 data |= BIT(offset);
2493 writel(data, reg);
2494
2495 raw_spin_unlock_irqrestore(&bank->slock, flags);
2496 clk_disable(bank->clk);
2497 }
2498
2499 /*
2500 * Returns the level of the pin for input direction and setting of the DR
2501 * register for output gpios.
2502 */
2503 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2504 {
2505 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2506 u32 data;
2507
2508 clk_enable(bank->clk);
2509 data = readl(bank->reg_base + GPIO_EXT_PORT);
2510 clk_disable(bank->clk);
2511 data >>= offset;
2512 data &= 1;
2513 return data;
2514 }
2515
2516 /*
2517 * gpiolib gpio_direction_input callback function. The setting of the pin
2518 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2519 * interface.
2520 */
2521 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2522 {
2523 return pinctrl_gpio_direction_input(gc->base + offset);
2524 }
2525
2526 /*
2527 * gpiolib gpio_direction_output callback function. The setting of the pin
2528 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2529 * interface.
2530 */
2531 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2532 unsigned offset, int value)
2533 {
2534 rockchip_gpio_set(gc, offset, value);
2535 return pinctrl_gpio_direction_output(gc->base + offset);
2536 }
2537
2538 /*
2539 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2540 * and a virtual IRQ, if not already present.
2541 */
2542 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2543 {
2544 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2545 unsigned int virq;
2546
2547 if (!bank->domain)
2548 return -ENXIO;
2549
2550 virq = irq_create_mapping(bank->domain, offset);
2551
2552 return (virq) ? : -ENXIO;
2553 }
2554
2555 static const struct gpio_chip rockchip_gpiolib_chip = {
2556 .request = gpiochip_generic_request,
2557 .free = gpiochip_generic_free,
2558 .set = rockchip_gpio_set,
2559 .get = rockchip_gpio_get,
2560 .get_direction = rockchip_gpio_get_direction,
2561 .direction_input = rockchip_gpio_direction_input,
2562 .direction_output = rockchip_gpio_direction_output,
2563 .to_irq = rockchip_gpio_to_irq,
2564 .owner = THIS_MODULE,
2565 };
2566
2567 /*
2568 * Interrupt handling
2569 */
2570
2571 static void rockchip_irq_demux(struct irq_desc *desc)
2572 {
2573 struct irq_chip *chip = irq_desc_get_chip(desc);
2574 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2575 u32 pend;
2576
2577 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2578
2579 chained_irq_enter(chip, desc);
2580
2581 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2582
2583 while (pend) {
2584 unsigned int irq, virq;
2585
2586 irq = __ffs(pend);
2587 pend &= ~BIT(irq);
2588 virq = irq_linear_revmap(bank->domain, irq);
2589
2590 if (!virq) {
2591 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2592 continue;
2593 }
2594
2595 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2596
2597 /*
2598 * Triggering IRQ on both rising and falling edge
2599 * needs manual intervention.
2600 */
2601 if (bank->toggle_edge_mode & BIT(irq)) {
2602 u32 data, data_old, polarity;
2603 unsigned long flags;
2604
2605 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2606 do {
2607 raw_spin_lock_irqsave(&bank->slock, flags);
2608
2609 polarity = readl_relaxed(bank->reg_base +
2610 GPIO_INT_POLARITY);
2611 if (data & BIT(irq))
2612 polarity &= ~BIT(irq);
2613 else
2614 polarity |= BIT(irq);
2615 writel(polarity,
2616 bank->reg_base + GPIO_INT_POLARITY);
2617
2618 raw_spin_unlock_irqrestore(&bank->slock, flags);
2619
2620 data_old = data;
2621 data = readl_relaxed(bank->reg_base +
2622 GPIO_EXT_PORT);
2623 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2624 }
2625
2626 generic_handle_irq(virq);
2627 }
2628
2629 chained_irq_exit(chip, desc);
2630 }
2631
2632 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2633 {
2634 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2635 struct rockchip_pin_bank *bank = gc->private;
2636 u32 mask = BIT(d->hwirq);
2637 u32 polarity;
2638 u32 level;
2639 u32 data;
2640 unsigned long flags;
2641 int ret;
2642
2643 /* make sure the pin is configured as gpio input */
2644 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2645 if (ret < 0)
2646 return ret;
2647
2648 clk_enable(bank->clk);
2649 raw_spin_lock_irqsave(&bank->slock, flags);
2650
2651 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2652 data &= ~mask;
2653 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2654
2655 raw_spin_unlock_irqrestore(&bank->slock, flags);
2656
2657 if (type & IRQ_TYPE_EDGE_BOTH)
2658 irq_set_handler_locked(d, handle_edge_irq);
2659 else
2660 irq_set_handler_locked(d, handle_level_irq);
2661
2662 raw_spin_lock_irqsave(&bank->slock, flags);
2663 irq_gc_lock(gc);
2664
2665 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2666 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2667
2668 switch (type) {
2669 case IRQ_TYPE_EDGE_BOTH:
2670 bank->toggle_edge_mode |= mask;
2671 level |= mask;
2672
2673 /*
2674 * Determine gpio state. If 1 next interrupt should be falling
2675 * otherwise rising.
2676 */
2677 data = readl(bank->reg_base + GPIO_EXT_PORT);
2678 if (data & mask)
2679 polarity &= ~mask;
2680 else
2681 polarity |= mask;
2682 break;
2683 case IRQ_TYPE_EDGE_RISING:
2684 bank->toggle_edge_mode &= ~mask;
2685 level |= mask;
2686 polarity |= mask;
2687 break;
2688 case IRQ_TYPE_EDGE_FALLING:
2689 bank->toggle_edge_mode &= ~mask;
2690 level |= mask;
2691 polarity &= ~mask;
2692 break;
2693 case IRQ_TYPE_LEVEL_HIGH:
2694 bank->toggle_edge_mode &= ~mask;
2695 level &= ~mask;
2696 polarity |= mask;
2697 break;
2698 case IRQ_TYPE_LEVEL_LOW:
2699 bank->toggle_edge_mode &= ~mask;
2700 level &= ~mask;
2701 polarity &= ~mask;
2702 break;
2703 default:
2704 irq_gc_unlock(gc);
2705 raw_spin_unlock_irqrestore(&bank->slock, flags);
2706 clk_disable(bank->clk);
2707 return -EINVAL;
2708 }
2709
2710 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2711 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2712
2713 irq_gc_unlock(gc);
2714 raw_spin_unlock_irqrestore(&bank->slock, flags);
2715 clk_disable(bank->clk);
2716
2717 return 0;
2718 }
2719
2720 static void rockchip_irq_suspend(struct irq_data *d)
2721 {
2722 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2723 struct rockchip_pin_bank *bank = gc->private;
2724
2725 clk_enable(bank->clk);
2726 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2727 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2728 clk_disable(bank->clk);
2729 }
2730
2731 static void rockchip_irq_resume(struct irq_data *d)
2732 {
2733 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2734 struct rockchip_pin_bank *bank = gc->private;
2735
2736 clk_enable(bank->clk);
2737 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2738 clk_disable(bank->clk);
2739 }
2740
2741 static void rockchip_irq_enable(struct irq_data *d)
2742 {
2743 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2744 struct rockchip_pin_bank *bank = gc->private;
2745
2746 clk_enable(bank->clk);
2747 irq_gc_mask_clr_bit(d);
2748 }
2749
2750 static void rockchip_irq_disable(struct irq_data *d)
2751 {
2752 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2753 struct rockchip_pin_bank *bank = gc->private;
2754
2755 irq_gc_mask_set_bit(d);
2756 clk_disable(bank->clk);
2757 }
2758
2759 static int rockchip_interrupts_register(struct platform_device *pdev,
2760 struct rockchip_pinctrl *info)
2761 {
2762 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2763 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2764 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2765 struct irq_chip_generic *gc;
2766 int ret;
2767 int i, j;
2768
2769 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2770 if (!bank->valid) {
2771 dev_warn(&pdev->dev, "bank %s is not valid\n",
2772 bank->name);
2773 continue;
2774 }
2775
2776 ret = clk_enable(bank->clk);
2777 if (ret) {
2778 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2779 bank->name);
2780 continue;
2781 }
2782
2783 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2784 &irq_generic_chip_ops, NULL);
2785 if (!bank->domain) {
2786 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2787 bank->name);
2788 clk_disable(bank->clk);
2789 continue;
2790 }
2791
2792 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2793 "rockchip_gpio_irq", handle_level_irq,
2794 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2795 if (ret) {
2796 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2797 bank->name);
2798 irq_domain_remove(bank->domain);
2799 clk_disable(bank->clk);
2800 continue;
2801 }
2802
2803 /*
2804 * Linux assumes that all interrupts start out disabled/masked.
2805 * Our driver only uses the concept of masked and always keeps
2806 * things enabled, so for us that's all masked and all enabled.
2807 */
2808 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2809 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2810
2811 gc = irq_get_domain_generic_chip(bank->domain, 0);
2812 gc->reg_base = bank->reg_base;
2813 gc->private = bank;
2814 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2815 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2816 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2817 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
2818 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
2819 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
2820 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
2821 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2822 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2823 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2824 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2825 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2826
2827 irq_set_chained_handler_and_data(bank->irq,
2828 rockchip_irq_demux, bank);
2829
2830 /* map the gpio irqs here, when the clock is still running */
2831 for (j = 0 ; j < 32 ; j++)
2832 irq_create_mapping(bank->domain, j);
2833
2834 clk_disable(bank->clk);
2835 }
2836
2837 return 0;
2838 }
2839
2840 static int rockchip_gpiolib_register(struct platform_device *pdev,
2841 struct rockchip_pinctrl *info)
2842 {
2843 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2844 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2845 struct gpio_chip *gc;
2846 int ret;
2847 int i;
2848
2849 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2850 if (!bank->valid) {
2851 dev_warn(&pdev->dev, "bank %s is not valid\n",
2852 bank->name);
2853 continue;
2854 }
2855
2856 bank->gpio_chip = rockchip_gpiolib_chip;
2857
2858 gc = &bank->gpio_chip;
2859 gc->base = bank->pin_base;
2860 gc->ngpio = bank->nr_pins;
2861 gc->parent = &pdev->dev;
2862 gc->of_node = bank->of_node;
2863 gc->label = bank->name;
2864
2865 ret = gpiochip_add_data(gc, bank);
2866 if (ret) {
2867 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2868 gc->label, ret);
2869 goto fail;
2870 }
2871 }
2872
2873 rockchip_interrupts_register(pdev, info);
2874
2875 return 0;
2876
2877 fail:
2878 for (--i, --bank; i >= 0; --i, --bank) {
2879 if (!bank->valid)
2880 continue;
2881 gpiochip_remove(&bank->gpio_chip);
2882 }
2883 return ret;
2884 }
2885
2886 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2887 struct rockchip_pinctrl *info)
2888 {
2889 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2890 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2891 int i;
2892
2893 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2894 if (!bank->valid)
2895 continue;
2896 gpiochip_remove(&bank->gpio_chip);
2897 }
2898
2899 return 0;
2900 }
2901
2902 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2903 struct rockchip_pinctrl *info)
2904 {
2905 struct resource res;
2906 void __iomem *base;
2907
2908 if (of_address_to_resource(bank->of_node, 0, &res)) {
2909 dev_err(info->dev, "cannot find IO resource for bank\n");
2910 return -ENOENT;
2911 }
2912
2913 bank->reg_base = devm_ioremap_resource(info->dev, &res);
2914 if (IS_ERR(bank->reg_base))
2915 return PTR_ERR(bank->reg_base);
2916
2917 /*
2918 * special case, where parts of the pull setting-registers are
2919 * part of the PMU register space
2920 */
2921 if (of_device_is_compatible(bank->of_node,
2922 "rockchip,rk3188-gpio-bank0")) {
2923 struct device_node *node;
2924
2925 node = of_parse_phandle(bank->of_node->parent,
2926 "rockchip,pmu", 0);
2927 if (!node) {
2928 if (of_address_to_resource(bank->of_node, 1, &res)) {
2929 dev_err(info->dev, "cannot find IO resource for bank\n");
2930 return -ENOENT;
2931 }
2932
2933 base = devm_ioremap_resource(info->dev, &res);
2934 if (IS_ERR(base))
2935 return PTR_ERR(base);
2936 rockchip_regmap_config.max_register =
2937 resource_size(&res) - 4;
2938 rockchip_regmap_config.name =
2939 "rockchip,rk3188-gpio-bank0-pull";
2940 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2941 base,
2942 &rockchip_regmap_config);
2943 }
2944 }
2945
2946 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2947
2948 bank->clk = of_clk_get(bank->of_node, 0);
2949 if (IS_ERR(bank->clk))
2950 return PTR_ERR(bank->clk);
2951
2952 return clk_prepare(bank->clk);
2953 }
2954
2955 static const struct of_device_id rockchip_pinctrl_dt_match[];
2956
2957 /* retrieve the soc specific data */
2958 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2959 struct rockchip_pinctrl *d,
2960 struct platform_device *pdev)
2961 {
2962 const struct of_device_id *match;
2963 struct device_node *node = pdev->dev.of_node;
2964 struct device_node *np;
2965 struct rockchip_pin_ctrl *ctrl;
2966 struct rockchip_pin_bank *bank;
2967 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2968
2969 match = of_match_node(rockchip_pinctrl_dt_match, node);
2970 ctrl = (struct rockchip_pin_ctrl *)match->data;
2971
2972 for_each_child_of_node(node, np) {
2973 if (!of_find_property(np, "gpio-controller", NULL))
2974 continue;
2975
2976 bank = ctrl->pin_banks;
2977 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2978 if (!strcmp(bank->name, np->name)) {
2979 bank->of_node = np;
2980
2981 if (!rockchip_get_bank_data(bank, d))
2982 bank->valid = true;
2983
2984 break;
2985 }
2986 }
2987 }
2988
2989 grf_offs = ctrl->grf_mux_offset;
2990 pmu_offs = ctrl->pmu_mux_offset;
2991 drv_pmu_offs = ctrl->pmu_drv_offset;
2992 drv_grf_offs = ctrl->grf_drv_offset;
2993 bank = ctrl->pin_banks;
2994 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2995 int bank_pins = 0;
2996
2997 raw_spin_lock_init(&bank->slock);
2998 bank->drvdata = d;
2999 bank->pin_base = ctrl->nr_pins;
3000 ctrl->nr_pins += bank->nr_pins;
3001
3002 /* calculate iomux and drv offsets */
3003 for (j = 0; j < 4; j++) {
3004 struct rockchip_iomux *iom = &bank->iomux[j];
3005 struct rockchip_drv *drv = &bank->drv[j];
3006 int inc;
3007
3008 if (bank_pins >= bank->nr_pins)
3009 break;
3010
3011 /* preset iomux offset value, set new start value */
3012 if (iom->offset >= 0) {
3013 if (iom->type & IOMUX_SOURCE_PMU)
3014 pmu_offs = iom->offset;
3015 else
3016 grf_offs = iom->offset;
3017 } else { /* set current iomux offset */
3018 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3019 pmu_offs : grf_offs;
3020 }
3021
3022 /* preset drv offset value, set new start value */
3023 if (drv->offset >= 0) {
3024 if (iom->type & IOMUX_SOURCE_PMU)
3025 drv_pmu_offs = drv->offset;
3026 else
3027 drv_grf_offs = drv->offset;
3028 } else { /* set current drv offset */
3029 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3030 drv_pmu_offs : drv_grf_offs;
3031 }
3032
3033 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3034 i, j, iom->offset, drv->offset);
3035
3036 /*
3037 * Increase offset according to iomux width.
3038 * 4bit iomux'es are spread over two registers.
3039 */
3040 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3041 IOMUX_WIDTH_3BIT)) ? 8 : 4;
3042 if (iom->type & IOMUX_SOURCE_PMU)
3043 pmu_offs += inc;
3044 else
3045 grf_offs += inc;
3046
3047 /*
3048 * Increase offset according to drv width.
3049 * 3bit drive-strenth'es are spread over two registers.
3050 */
3051 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3052 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3053 inc = 8;
3054 else
3055 inc = 4;
3056
3057 if (iom->type & IOMUX_SOURCE_PMU)
3058 drv_pmu_offs += inc;
3059 else
3060 drv_grf_offs += inc;
3061
3062 bank_pins += 8;
3063 }
3064
3065 /* calculate the per-bank recalced_mask */
3066 for (j = 0; j < ctrl->niomux_recalced; j++) {
3067 int pin = 0;
3068
3069 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3070 pin = ctrl->iomux_recalced[j].pin;
3071 bank->recalced_mask |= BIT(pin);
3072 }
3073 }
3074
3075 /* calculate the per-bank route_mask */
3076 for (j = 0; j < ctrl->niomux_routes; j++) {
3077 int pin = 0;
3078
3079 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3080 pin = ctrl->iomux_routes[j].pin;
3081 bank->route_mask |= BIT(pin);
3082 }
3083 }
3084 }
3085
3086 return ctrl;
3087 }
3088
3089 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3090 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3091
3092 static u32 rk3288_grf_gpio6c_iomux;
3093
3094 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3095 {
3096 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3097 int ret = pinctrl_force_sleep(info->pctl_dev);
3098
3099 if (ret)
3100 return ret;
3101
3102 /*
3103 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3104 * the setting here, and restore it at resume.
3105 */
3106 if (info->ctrl->type == RK3288) {
3107 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3108 &rk3288_grf_gpio6c_iomux);
3109 if (ret) {
3110 pinctrl_force_default(info->pctl_dev);
3111 return ret;
3112 }
3113 }
3114
3115 return 0;
3116 }
3117
3118 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3119 {
3120 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3121 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3122 rk3288_grf_gpio6c_iomux |
3123 GPIO6C6_SEL_WRITE_ENABLE);
3124
3125 if (ret)
3126 return ret;
3127
3128 return pinctrl_force_default(info->pctl_dev);
3129 }
3130
3131 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3132 rockchip_pinctrl_resume);
3133
3134 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3135 {
3136 struct rockchip_pinctrl *info;
3137 struct device *dev = &pdev->dev;
3138 struct rockchip_pin_ctrl *ctrl;
3139 struct device_node *np = pdev->dev.of_node, *node;
3140 struct resource *res;
3141 void __iomem *base;
3142 int ret;
3143
3144 if (!dev->of_node) {
3145 dev_err(dev, "device tree node not found\n");
3146 return -ENODEV;
3147 }
3148
3149 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
3150 if (!info)
3151 return -ENOMEM;
3152
3153 info->dev = dev;
3154
3155 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3156 if (!ctrl) {
3157 dev_err(dev, "driver data not available\n");
3158 return -EINVAL;
3159 }
3160 info->ctrl = ctrl;
3161
3162 node = of_parse_phandle(np, "rockchip,grf", 0);
3163 if (node) {
3164 info->regmap_base = syscon_node_to_regmap(node);
3165 if (IS_ERR(info->regmap_base))
3166 return PTR_ERR(info->regmap_base);
3167 } else {
3168 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3169 base = devm_ioremap_resource(&pdev->dev, res);
3170 if (IS_ERR(base))
3171 return PTR_ERR(base);
3172
3173 rockchip_regmap_config.max_register = resource_size(res) - 4;
3174 rockchip_regmap_config.name = "rockchip,pinctrl";
3175 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3176 &rockchip_regmap_config);
3177
3178 /* to check for the old dt-bindings */
3179 info->reg_size = resource_size(res);
3180
3181 /* Honor the old binding, with pull registers as 2nd resource */
3182 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3183 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3184 base = devm_ioremap_resource(&pdev->dev, res);
3185 if (IS_ERR(base))
3186 return PTR_ERR(base);
3187
3188 rockchip_regmap_config.max_register =
3189 resource_size(res) - 4;
3190 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3191 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3192 base,
3193 &rockchip_regmap_config);
3194 }
3195 }
3196
3197 /* try to find the optional reference to the pmu syscon */
3198 node = of_parse_phandle(np, "rockchip,pmu", 0);
3199 if (node) {
3200 info->regmap_pmu = syscon_node_to_regmap(node);
3201 if (IS_ERR(info->regmap_pmu))
3202 return PTR_ERR(info->regmap_pmu);
3203 }
3204
3205 ret = rockchip_gpiolib_register(pdev, info);
3206 if (ret)
3207 return ret;
3208
3209 ret = rockchip_pinctrl_register(pdev, info);
3210 if (ret) {
3211 rockchip_gpiolib_unregister(pdev, info);
3212 return ret;
3213 }
3214
3215 platform_set_drvdata(pdev, info);
3216
3217 return 0;
3218 }
3219
3220 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3221 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3222 IOMUX_SOURCE_PMU,
3223 IOMUX_SOURCE_PMU,
3224 IOMUX_SOURCE_PMU),
3225 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3226 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3227 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3228 };
3229
3230 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3231 .pin_banks = rv1108_pin_banks,
3232 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3233 .label = "RV1108-GPIO",
3234 .type = RV1108,
3235 .grf_mux_offset = 0x10,
3236 .pmu_mux_offset = 0x0,
3237 .iomux_recalced = rv1108_mux_recalced_data,
3238 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3239 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3240 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3241 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3242 };
3243
3244 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3245 PIN_BANK(0, 32, "gpio0"),
3246 PIN_BANK(1, 32, "gpio1"),
3247 PIN_BANK(2, 32, "gpio2"),
3248 PIN_BANK(3, 32, "gpio3"),
3249 };
3250
3251 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3252 .pin_banks = rk2928_pin_banks,
3253 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3254 .label = "RK2928-GPIO",
3255 .type = RK2928,
3256 .grf_mux_offset = 0xa8,
3257 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3258 };
3259
3260 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3261 PIN_BANK(0, 32, "gpio0"),
3262 PIN_BANK(1, 32, "gpio1"),
3263 PIN_BANK(2, 32, "gpio2"),
3264 };
3265
3266 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3267 .pin_banks = rk3036_pin_banks,
3268 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3269 .label = "RK3036-GPIO",
3270 .type = RK2928,
3271 .grf_mux_offset = 0xa8,
3272 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3273 };
3274
3275 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3276 PIN_BANK(0, 32, "gpio0"),
3277 PIN_BANK(1, 32, "gpio1"),
3278 PIN_BANK(2, 32, "gpio2"),
3279 PIN_BANK(3, 32, "gpio3"),
3280 PIN_BANK(4, 32, "gpio4"),
3281 PIN_BANK(6, 16, "gpio6"),
3282 };
3283
3284 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3285 .pin_banks = rk3066a_pin_banks,
3286 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3287 .label = "RK3066a-GPIO",
3288 .type = RK2928,
3289 .grf_mux_offset = 0xa8,
3290 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3291 };
3292
3293 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3294 PIN_BANK(0, 32, "gpio0"),
3295 PIN_BANK(1, 32, "gpio1"),
3296 PIN_BANK(2, 32, "gpio2"),
3297 PIN_BANK(3, 32, "gpio3"),
3298 };
3299
3300 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3301 .pin_banks = rk3066b_pin_banks,
3302 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3303 .label = "RK3066b-GPIO",
3304 .type = RK3066B,
3305 .grf_mux_offset = 0x60,
3306 };
3307
3308 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3309 PIN_BANK(0, 32, "gpio0"),
3310 PIN_BANK(1, 32, "gpio1"),
3311 PIN_BANK(2, 32, "gpio2"),
3312 PIN_BANK(3, 32, "gpio3"),
3313 };
3314
3315 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3316 .pin_banks = rk3128_pin_banks,
3317 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3318 .label = "RK3128-GPIO",
3319 .type = RK3128,
3320 .grf_mux_offset = 0xa8,
3321 .iomux_recalced = rk3128_mux_recalced_data,
3322 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3323 .iomux_routes = rk3128_mux_route_data,
3324 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3325 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3326 };
3327
3328 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3329 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3330 PIN_BANK(1, 32, "gpio1"),
3331 PIN_BANK(2, 32, "gpio2"),
3332 PIN_BANK(3, 32, "gpio3"),
3333 };
3334
3335 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3336 .pin_banks = rk3188_pin_banks,
3337 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3338 .label = "RK3188-GPIO",
3339 .type = RK3188,
3340 .grf_mux_offset = 0x60,
3341 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3342 };
3343
3344 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3345 PIN_BANK(0, 32, "gpio0"),
3346 PIN_BANK(1, 32, "gpio1"),
3347 PIN_BANK(2, 32, "gpio2"),
3348 PIN_BANK(3, 32, "gpio3"),
3349 };
3350
3351 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3352 .pin_banks = rk3228_pin_banks,
3353 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3354 .label = "RK3228-GPIO",
3355 .type = RK3288,
3356 .grf_mux_offset = 0x0,
3357 .iomux_routes = rk3228_mux_route_data,
3358 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3359 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3360 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3361 };
3362
3363 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3364 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3365 IOMUX_SOURCE_PMU,
3366 IOMUX_SOURCE_PMU,
3367 IOMUX_UNROUTED
3368 ),
3369 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3370 IOMUX_UNROUTED,
3371 IOMUX_UNROUTED,
3372 0
3373 ),
3374 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3375 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3376 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3377 IOMUX_WIDTH_4BIT,
3378 0,
3379 0
3380 ),
3381 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3382 0,
3383 0,
3384 IOMUX_UNROUTED
3385 ),
3386 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3387 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3388 0,
3389 IOMUX_WIDTH_4BIT,
3390 IOMUX_UNROUTED
3391 ),
3392 PIN_BANK(8, 16, "gpio8"),
3393 };
3394
3395 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3396 .pin_banks = rk3288_pin_banks,
3397 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3398 .label = "RK3288-GPIO",
3399 .type = RK3288,
3400 .grf_mux_offset = 0x0,
3401 .pmu_mux_offset = 0x84,
3402 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3403 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3404 };
3405
3406 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3407 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3408 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3409 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3410 IOMUX_WIDTH_3BIT,
3411 IOMUX_WIDTH_3BIT,
3412 0),
3413 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3414 IOMUX_WIDTH_3BIT,
3415 IOMUX_WIDTH_3BIT,
3416 0,
3417 0),
3418 };
3419
3420 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3421 .pin_banks = rk3328_pin_banks,
3422 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3423 .label = "RK3328-GPIO",
3424 .type = RK3288,
3425 .grf_mux_offset = 0x0,
3426 .iomux_recalced = rk3328_mux_recalced_data,
3427 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3428 .iomux_routes = rk3328_mux_route_data,
3429 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3430 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3431 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3432 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3433 };
3434
3435 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3436 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3437 IOMUX_SOURCE_PMU,
3438 IOMUX_SOURCE_PMU,
3439 IOMUX_SOURCE_PMU
3440 ),
3441 PIN_BANK(1, 32, "gpio1"),
3442 PIN_BANK(2, 32, "gpio2"),
3443 PIN_BANK(3, 32, "gpio3"),
3444 };
3445
3446 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3447 .pin_banks = rk3368_pin_banks,
3448 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3449 .label = "RK3368-GPIO",
3450 .type = RK3368,
3451 .grf_mux_offset = 0x0,
3452 .pmu_mux_offset = 0x0,
3453 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3454 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3455 };
3456
3457 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3458 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3459 IOMUX_SOURCE_PMU,
3460 IOMUX_SOURCE_PMU,
3461 IOMUX_SOURCE_PMU,
3462 IOMUX_SOURCE_PMU,
3463 DRV_TYPE_IO_1V8_ONLY,
3464 DRV_TYPE_IO_1V8_ONLY,
3465 DRV_TYPE_IO_DEFAULT,
3466 DRV_TYPE_IO_DEFAULT,
3467 0x0,
3468 0x8,
3469 -1,
3470 -1,
3471 PULL_TYPE_IO_1V8_ONLY,
3472 PULL_TYPE_IO_1V8_ONLY,
3473 PULL_TYPE_IO_DEFAULT,
3474 PULL_TYPE_IO_DEFAULT
3475 ),
3476 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3477 IOMUX_SOURCE_PMU,
3478 IOMUX_SOURCE_PMU,
3479 IOMUX_SOURCE_PMU,
3480 DRV_TYPE_IO_1V8_OR_3V0,
3481 DRV_TYPE_IO_1V8_OR_3V0,
3482 DRV_TYPE_IO_1V8_OR_3V0,
3483 DRV_TYPE_IO_1V8_OR_3V0,
3484 0x20,
3485 0x28,
3486 0x30,
3487 0x38
3488 ),
3489 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3490 DRV_TYPE_IO_1V8_OR_3V0,
3491 DRV_TYPE_IO_1V8_ONLY,
3492 DRV_TYPE_IO_1V8_ONLY,
3493 PULL_TYPE_IO_DEFAULT,
3494 PULL_TYPE_IO_DEFAULT,
3495 PULL_TYPE_IO_1V8_ONLY,
3496 PULL_TYPE_IO_1V8_ONLY
3497 ),
3498 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3499 DRV_TYPE_IO_3V3_ONLY,
3500 DRV_TYPE_IO_3V3_ONLY,
3501 DRV_TYPE_IO_1V8_OR_3V0
3502 ),
3503 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3504 DRV_TYPE_IO_1V8_3V0_AUTO,
3505 DRV_TYPE_IO_1V8_OR_3V0,
3506 DRV_TYPE_IO_1V8_OR_3V0
3507 ),
3508 };
3509
3510 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3511 .pin_banks = rk3399_pin_banks,
3512 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3513 .label = "RK3399-GPIO",
3514 .type = RK3399,
3515 .grf_mux_offset = 0xe000,
3516 .pmu_mux_offset = 0x0,
3517 .grf_drv_offset = 0xe100,
3518 .pmu_drv_offset = 0x80,
3519 .iomux_routes = rk3399_mux_route_data,
3520 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3521 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3522 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3523 };
3524
3525 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3526 { .compatible = "rockchip,rv1108-pinctrl",
3527 .data = &rv1108_pin_ctrl },
3528 { .compatible = "rockchip,rk2928-pinctrl",
3529 .data = &rk2928_pin_ctrl },
3530 { .compatible = "rockchip,rk3036-pinctrl",
3531 .data = &rk3036_pin_ctrl },
3532 { .compatible = "rockchip,rk3066a-pinctrl",
3533 .data = &rk3066a_pin_ctrl },
3534 { .compatible = "rockchip,rk3066b-pinctrl",
3535 .data = &rk3066b_pin_ctrl },
3536 { .compatible = "rockchip,rk3128-pinctrl",
3537 .data = (void *)&rk3128_pin_ctrl },
3538 { .compatible = "rockchip,rk3188-pinctrl",
3539 .data = &rk3188_pin_ctrl },
3540 { .compatible = "rockchip,rk3228-pinctrl",
3541 .data = &rk3228_pin_ctrl },
3542 { .compatible = "rockchip,rk3288-pinctrl",
3543 .data = &rk3288_pin_ctrl },
3544 { .compatible = "rockchip,rk3328-pinctrl",
3545 .data = &rk3328_pin_ctrl },
3546 { .compatible = "rockchip,rk3368-pinctrl",
3547 .data = &rk3368_pin_ctrl },
3548 { .compatible = "rockchip,rk3399-pinctrl",
3549 .data = &rk3399_pin_ctrl },
3550 {},
3551 };
3552
3553 static struct platform_driver rockchip_pinctrl_driver = {
3554 .probe = rockchip_pinctrl_probe,
3555 .driver = {
3556 .name = "rockchip-pinctrl",
3557 .pm = &rockchip_pinctrl_dev_pm_ops,
3558 .of_match_table = rockchip_pinctrl_dt_match,
3559 },
3560 };
3561
3562 static int __init rockchip_pinctrl_drv_register(void)
3563 {
3564 return platform_driver_register(&rockchip_pinctrl_driver);
3565 }
3566 postcore_initcall(rockchip_pinctrl_drv_register);
Linux with added FPC-III support