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uapi/if_ether.h: move __UAPI_DEF_ETHHDR libc define
[linux/fpc-iii.git] / drivers / pinctrl / sunxi / pinctrl-sun50i-h5.c
blob97b48336f84a3fdd6a30e98a19e954d625d3cfee
1 /*
2 * Allwinner H5 SoC pinctrl driver.
3 *
4 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
5 *
6 * Based on pinctrl-sun8i-h3.c, which is:
7 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
8 *
9 * Based on pinctrl-sun8i-a23.c, which is:
10 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
11 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/pinctrl.h>
24
25 #include "pinctrl-sunxi.h"
26
27 static const struct sunxi_desc_pin sun50i_h5_pins[] = {
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
32 SUNXI_FUNCTION(0x3, "jtag"), /* MS */
33 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
38 SUNXI_FUNCTION(0x3, "jtag"), /* CK */
39 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
44 SUNXI_FUNCTION(0x3, "jtag"), /* DO */
45 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
50 SUNXI_FUNCTION(0x3, "jtag"), /* DI */
51 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
56 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
57 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
58 SUNXI_FUNCTION(0x0, "gpio_in"),
59 SUNXI_FUNCTION(0x1, "gpio_out"),
60 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
61 SUNXI_FUNCTION(0x3, "pwm0"),
62 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "sim"), /* PWREN */
67 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "sim"), /* CLK */
72 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "sim"), /* DATA */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "sim"), /* RST */
82 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "sim"), /* DET */
87 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
88 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
89 SUNXI_FUNCTION(0x0, "gpio_in"),
90 SUNXI_FUNCTION(0x1, "gpio_out"),
91 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
92 SUNXI_FUNCTION(0x3, "di"), /* TX */
93 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
94 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
95 SUNXI_FUNCTION(0x0, "gpio_in"),
96 SUNXI_FUNCTION(0x1, "gpio_out"),
97 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
98 SUNXI_FUNCTION(0x3, "di"), /* RX */
99 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
100 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
101 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out"),
103 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
104 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
105 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
110 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
111 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
112 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
113 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out"),
115 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
116 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
117 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
118 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
119 SUNXI_FUNCTION(0x0, "gpio_in"),
120 SUNXI_FUNCTION(0x1, "gpio_out"),
121 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
122 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
123 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
128 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
129 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
133 SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
134 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
135 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
136 SUNXI_FUNCTION(0x0, "gpio_in"),
137 SUNXI_FUNCTION(0x1, "gpio_out"),
138 SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
139 SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
140 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
141 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
142 SUNXI_FUNCTION(0x0, "gpio_in"),
143 SUNXI_FUNCTION(0x1, "gpio_out"),
144 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
145 SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */
146 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
147 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
148 SUNXI_FUNCTION(0x0, "gpio_in"),
149 SUNXI_FUNCTION(0x1, "gpio_out"),
150 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
151 SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */
152 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
153 /* Hole */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
158 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
163 SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
164 SUNXI_FUNCTION(0x4, "mmc2")), /* DS */
165 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
166 SUNXI_FUNCTION(0x0, "gpio_in"),
167 SUNXI_FUNCTION(0x1, "gpio_out"),
168 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
169 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
170 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
171 SUNXI_FUNCTION(0x0, "gpio_in"),
172 SUNXI_FUNCTION(0x1, "gpio_out"),
173 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
174 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
179 SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
184 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
189 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
194 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
195 SUNXI_FUNCTION(0x0, "gpio_in"),
196 SUNXI_FUNCTION(0x1, "gpio_out"),
197 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
198 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
203 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
208 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
213 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
214 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
215 SUNXI_FUNCTION(0x0, "gpio_in"),
216 SUNXI_FUNCTION(0x1, "gpio_out"),
217 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
218 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
219 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
220 SUNXI_FUNCTION(0x0, "gpio_in"),
221 SUNXI_FUNCTION(0x1, "gpio_out"),
222 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
223 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
224 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
225 SUNXI_FUNCTION(0x0, "gpio_in"),
226 SUNXI_FUNCTION(0x1, "gpio_out"),
227 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
228 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
233 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
238 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
239 /* Hole */
240 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
241 SUNXI_FUNCTION(0x0, "gpio_in"),
242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */
244 SUNXI_FUNCTION(0x3, "di"), /* TX */
245 SUNXI_FUNCTION(0x4, "ts2")), /* CLK */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x1, "gpio_out"),
249 SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */
250 SUNXI_FUNCTION(0x3, "di"), /* RX */
251 SUNXI_FUNCTION(0x4, "ts2")), /* ERR */
252 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
253 SUNXI_FUNCTION(0x0, "gpio_in"),
254 SUNXI_FUNCTION(0x1, "gpio_out"),
255 SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */
256 SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */
261 SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "emac"), /* RXCK */
266 SUNXI_FUNCTION(0x4, "ts2")), /* D0 */
267 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */
271 SUNXI_FUNCTION(0x4, "ts2")), /* D1 */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "emac"), /* RXERR */
276 SUNXI_FUNCTION(0x4, "ts2")), /* D2 */
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */
281 SUNXI_FUNCTION(0x4, "ts2"), /* D3 */
282 SUNXI_FUNCTION(0x5, "ts3")), /* CLK */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */
287 SUNXI_FUNCTION(0x4, "ts2"), /* D4 */
288 SUNXI_FUNCTION(0x5, "ts3")), /* ERR */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */
293 SUNXI_FUNCTION(0x4, "ts2"), /* D5 */
294 SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */
295 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
296 SUNXI_FUNCTION(0x0, "gpio_in"),
297 SUNXI_FUNCTION(0x1, "gpio_out"),
298 SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */
299 SUNXI_FUNCTION(0x4, "ts2"), /* D6 */
300 SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "emac"), /* CRS */
305 SUNXI_FUNCTION(0x4, "ts2"), /* D7 */
306 SUNXI_FUNCTION(0x5, "ts3")), /* D0 */
307 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
308 SUNXI_FUNCTION(0x0, "gpio_in"),
309 SUNXI_FUNCTION(0x1, "gpio_out"),
310 SUNXI_FUNCTION(0x2, "emac"), /* TXCK */
311 SUNXI_FUNCTION(0x4, "sim")), /* PWREN */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */
316 SUNXI_FUNCTION(0x4, "sim")), /* CLK */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "emac"), /* TXERR */
321 SUNXI_FUNCTION(0x4, "sim")), /* DATA */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */
326 SUNXI_FUNCTION(0x4, "sim")), /* RST */
327 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
328 SUNXI_FUNCTION(0x0, "gpio_in"),
329 SUNXI_FUNCTION(0x1, "gpio_out"),
330 SUNXI_FUNCTION(0x2, "emac"), /* MDC */
331 SUNXI_FUNCTION(0x4, "sim")), /* DET */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "emac")), /* MDIO */
336 /* Hole */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
341 SUNXI_FUNCTION(0x3, "ts0")), /* CLK */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
346 SUNXI_FUNCTION(0x3, "ts0")), /* ERR */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
351 SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
356 SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
361 SUNXI_FUNCTION(0x3, "ts0")), /* D0 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
366 SUNXI_FUNCTION(0x3, "ts0")), /* D1 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
371 SUNXI_FUNCTION(0x3, "ts0")), /* D2 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
376 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
377 SUNXI_FUNCTION(0x4, "ts1")), /* CLK */
378 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
379 SUNXI_FUNCTION(0x0, "gpio_in"),
380 SUNXI_FUNCTION(0x1, "gpio_out"),
381 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
382 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
383 SUNXI_FUNCTION(0x4, "ts1")), /* ERR */
384 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
385 SUNXI_FUNCTION(0x0, "gpio_in"),
386 SUNXI_FUNCTION(0x1, "gpio_out"),
387 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
388 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
389 SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */
390 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
394 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
395 SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */
396 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
397 SUNXI_FUNCTION(0x0, "gpio_in"),
398 SUNXI_FUNCTION(0x1, "gpio_out"),
399 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
400 SUNXI_FUNCTION(0x3, "ts"), /* D7 */
401 SUNXI_FUNCTION(0x4, "ts1")), /* D0 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
406 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
411 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
416 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
417 SUNXI_FUNCTION(0x0, "gpio_in"),
418 SUNXI_FUNCTION(0x1, "gpio_out"),
419 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
420 /* Hole */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out"),
424 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
425 SUNXI_FUNCTION(0x3, "jtag"), /* MS */
426 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
431 SUNXI_FUNCTION(0x3, "jtag"), /* DI */
432 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */
433 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
434 SUNXI_FUNCTION(0x0, "gpio_in"),
435 SUNXI_FUNCTION(0x1, "gpio_out"),
436 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
437 SUNXI_FUNCTION(0x3, "uart0"), /* TX */
438 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */
439 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
440 SUNXI_FUNCTION(0x0, "gpio_in"),
441 SUNXI_FUNCTION(0x1, "gpio_out"),
442 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
443 SUNXI_FUNCTION(0x3, "jtag"), /* DO */
444 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
449 SUNXI_FUNCTION(0x3, "uart0"), /* RX */
450 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */
451 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
452 SUNXI_FUNCTION(0x0, "gpio_in"),
453 SUNXI_FUNCTION(0x1, "gpio_out"),
454 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
455 SUNXI_FUNCTION(0x3, "jtag"), /* CK */
456 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */
461 /* Hole */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
466 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
471 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
476 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
481 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x1, "gpio_out"),
485 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
486 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */
487 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
488 SUNXI_FUNCTION(0x0, "gpio_in"),
489 SUNXI_FUNCTION(0x1, "gpio_out"),
490 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
491 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */
492 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
493 SUNXI_FUNCTION(0x0, "gpio_in"),
494 SUNXI_FUNCTION(0x1, "gpio_out"),
495 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
496 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */
497 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
498 SUNXI_FUNCTION(0x0, "gpio_in"),
499 SUNXI_FUNCTION(0x1, "gpio_out"),
500 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
501 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */
502 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
503 SUNXI_FUNCTION(0x0, "gpio_in"),
504 SUNXI_FUNCTION(0x1, "gpio_out"),
505 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
506 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */
507 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
508 SUNXI_FUNCTION(0x0, "gpio_in"),
509 SUNXI_FUNCTION(0x1, "gpio_out"),
510 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
511 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */
512 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
513 SUNXI_FUNCTION(0x0, "gpio_in"),
514 SUNXI_FUNCTION(0x1, "gpio_out"),
515 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
516 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
517 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
518 SUNXI_FUNCTION(0x0, "gpio_in"),
519 SUNXI_FUNCTION(0x1, "gpio_out"),
520 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
521 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
522 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
523 SUNXI_FUNCTION(0x0, "gpio_in"),
524 SUNXI_FUNCTION(0x1, "gpio_out"),
525 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
526 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
527 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x1, "gpio_out"),
530 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
531 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
532 };
533
534 static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
535 .pins = sun50i_h5_pins,
536 .npins = ARRAY_SIZE(sun50i_h5_pins),
537 .irq_banks = 2,
538 .irq_read_needs_mux = true
539 };
540
541 static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
542 .pins = sun50i_h5_pins,
543 .npins = ARRAY_SIZE(sun50i_h5_pins),
544 .irq_banks = 3,
545 .irq_read_needs_mux = true
546 };
547
548 static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
549 {
550 switch (of_irq_count(pdev->dev.of_node)) {
551 case 2:
552 dev_warn(&pdev->dev,
553 "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
554 dev_warn(&pdev->dev,
555 "Please update the device tree, otherwise PG bank IRQ won't work.\n");
556 return sunxi_pinctrl_init(pdev,
557 &sun50i_h5_pinctrl_data_broken);
558 case 3:
559 return sunxi_pinctrl_init(pdev,
560 &sun50i_h5_pinctrl_data);
561 default:
562 return -EINVAL;
563 }
564 }
565
566 static const struct of_device_id sun50i_h5_pinctrl_match[] = {
567 { .compatible = "allwinner,sun50i-h5-pinctrl", },
568 {}
569 };
570
571 static struct platform_driver sun50i_h5_pinctrl_driver = {
572 .probe = sun50i_h5_pinctrl_probe,
573 .driver = {
574 .name = "sun50i-h5-pinctrl",
575 .of_match_table = sun50i_h5_pinctrl_match,
576 },
577 };
578 builtin_platform_driver(sun50i_h5_pinctrl_driver);
Linux with added FPC-III support