drivers/watchdog/renesas_wdt.c

   1 /*
   2  * Watchdog driver for Renesas WDT watchdog
   3  *
   4  * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   5  * Copyright (C) 2015-17 Renesas Electronics Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  */
  11 #include <linux/bitops.h>
  12 #include <linux/clk.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/watchdog.h>
  20
  21 #define RWTCNT          0
  22 #define RWTCSRA         4
  23 #define RWTCSRA_WOVF    BIT(4)
  24 #define RWTCSRA_WRFLG   BIT(5)
  25 #define RWTCSRA_TME     BIT(7)
  26 #define RWTCSRB         8
  27
  28 #define RWDT_DEFAULT_TIMEOUT 60U
  29
  30 /*
  31  * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
  32  * divider (12 bits). d is only a factor to fully utilize the WDT counter and
  33  * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
  34  */
  35 #define MUL_BY_CLKS_PER_SEC(p, d) \
  36         DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
  37
  38 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
  39 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
  40
  41 static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
  42
  43 static bool nowayout = WATCHDOG_NOWAYOUT;
  44 module_param(nowayout, bool, 0);
  45 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  46                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  47
  48 struct rwdt_priv {
  49         void __iomem *base;
  50         struct watchdog_device wdev;
  51         unsigned long clk_rate;
  52         u8 cks;
  53 };
  54
  55 static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
  56 {
  57         if (reg == RWTCNT)
  58                 val |= 0x5a5a0000;
  59         else
  60                 val |= 0xa5a5a500;
  61
  62         writel_relaxed(val, priv->base + reg);
  63 }
  64
  65 static int rwdt_init_timeout(struct watchdog_device *wdev)
  66 {
  67         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  68
  69         rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
  70
  71         return 0;
  72 }
  73
  74 static int rwdt_start(struct watchdog_device *wdev)
  75 {
  76         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  77         u8 val;
  78
  79         pm_runtime_get_sync(wdev->parent);
  80
  81         /* Stop the timer before we modify any register */
  82         val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
  83         rwdt_write(priv, val, RWTCSRA);
  84
  85         rwdt_init_timeout(wdev);
  86         rwdt_write(priv, priv->cks, RWTCSRA);
  87         rwdt_write(priv, 0, RWTCSRB);
  88
  89         while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
  90                 cpu_relax();
  91
  92         rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
  93
  94         return 0;
  95 }
  96
  97 static int rwdt_stop(struct watchdog_device *wdev)
  98 {
  99         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 100
 101         rwdt_write(priv, priv->cks, RWTCSRA);
 102         pm_runtime_put(wdev->parent);
 103
 104         return 0;
 105 }
 106
 107 static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
 108 {
 109         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 110         u16 val = readw_relaxed(priv->base + RWTCNT);
 111
 112         return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
 113 }
 114
 115 static const struct watchdog_info rwdt_ident = {
 116         .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
 117         .identity = "Renesas WDT Watchdog",
 118 };
 119
 120 static const struct watchdog_ops rwdt_ops = {
 121         .owner = THIS_MODULE,
 122         .start = rwdt_start,
 123         .stop = rwdt_stop,
 124         .ping = rwdt_init_timeout,
 125         .get_timeleft = rwdt_get_timeleft,
 126 };
 127
 128 static int rwdt_probe(struct platform_device *pdev)
 129 {
 130         struct rwdt_priv *priv;
 131         struct resource *res;
 132         struct clk *clk;
 133         unsigned long clks_per_sec;
 134         int ret, i;
 135
 136         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 137         if (!priv)
 138                 return -ENOMEM;
 139
 140         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 141         priv->base = devm_ioremap_resource(&pdev->dev, res);
 142         if (IS_ERR(priv->base))
 143                 return PTR_ERR(priv->base);
 144
 145         clk = devm_clk_get(&pdev->dev, NULL);
 146         if (IS_ERR(clk))
 147                 return PTR_ERR(clk);
 148
 149         pm_runtime_enable(&pdev->dev);
 150
 151         pm_runtime_get_sync(&pdev->dev);
 152         priv->clk_rate = clk_get_rate(clk);
 153         pm_runtime_put(&pdev->dev);
 154
 155         if (!priv->clk_rate) {
 156                 ret = -ENOENT;
 157                 goto out_pm_disable;
 158         }
 159
 160         for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
 161                 clks_per_sec = priv->clk_rate / clk_divs[i];
 162                 if (clks_per_sec && clks_per_sec < 65536) {
 163                         priv->cks = i;
 164                         break;
 165                 }
 166         }
 167
 168         if (i < 0) {
 169                 dev_err(&pdev->dev, "Can't find suitable clock divider\n");
 170                 ret = -ERANGE;
 171                 goto out_pm_disable;
 172         }
 173
 174         priv->wdev.info = &rwdt_ident,
 175         priv->wdev.ops = &rwdt_ops,
 176         priv->wdev.parent = &pdev->dev;
 177         priv->wdev.min_timeout = 1;
 178         priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
 179         priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
 180
 181         platform_set_drvdata(pdev, priv);
 182         watchdog_set_drvdata(&priv->wdev, priv);
 183         watchdog_set_nowayout(&priv->wdev, nowayout);
 184
 185         /* This overrides the default timeout only if DT configuration was found */
 186         ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
 187         if (ret)
 188                 dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");
 189
 190         ret = watchdog_register_device(&priv->wdev);
 191         if (ret < 0)
 192                 goto out_pm_disable;
 193
 194         return 0;
 195
 196  out_pm_disable:
 197         pm_runtime_disable(&pdev->dev);
 198         return ret;
 199 }
 200
 201 static int rwdt_remove(struct platform_device *pdev)
 202 {
 203         struct rwdt_priv *priv = platform_get_drvdata(pdev);
 204
 205         watchdog_unregister_device(&priv->wdev);
 206         pm_runtime_disable(&pdev->dev);
 207
 208         return 0;
 209 }
 210
 211 /*
 212  * This driver does also fit for R-Car Gen2 (r8a779[0-4]) WDT. However, for SMP
 213  * to work there, one also needs a RESET (RST) driver which does not exist yet
 214  * due to HW issues. This needs to be solved before adding compatibles here.
 215  */
 216 static const struct of_device_id rwdt_ids[] = {
 217         { .compatible = "renesas,rcar-gen3-wdt", },
 218         { /* sentinel */ }
 219 };
 220 MODULE_DEVICE_TABLE(of, rwdt_ids);
 221
 222 static struct platform_driver rwdt_driver = {
 223         .driver = {
 224                 .name = "renesas_wdt",
 225                 .of_match_table = rwdt_ids,
 226         },
 227         .probe = rwdt_probe,
 228         .remove = rwdt_remove,
 229 };
 230 module_platform_driver(rwdt_driver);
 231
 232 MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
 233 MODULE_LICENSE("GPL v2");
 234 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");