1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #ifndef _IXGBE_COMMON_H_
29 #define _IXGBE_COMMON_H_
31 #include "ixgbe_type.h"
33 u32
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
);
34 s32
ixgbe_init_ops_generic(struct ixgbe_hw
*hw
);
35 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
);
36 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
);
37 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
);
38 s32
ixgbe_read_pba_num_generic(struct ixgbe_hw
*hw
, u32
*pba_num
);
39 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
);
40 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
);
41 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
);
42 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
);
44 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
);
45 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
);
47 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
);
48 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
);
49 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
);
50 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
52 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
54 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
);
55 s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
);
57 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
59 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
);
60 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
);
61 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
62 struct net_device
*netdev
);
63 s32
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw
*hw
,
64 struct net_device
*netdev
);
65 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
);
66 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
);
67 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
);
68 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
, s32 packtetbuf_num
);
69 s32
ixgbe_fc_autoneg(struct ixgbe_hw
*hw
);
71 s32
ixgbe_validate_mac_addr(u8
*mac_addr
);
72 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
);
73 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
);
74 s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
);
75 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
);
76 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
);
77 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
);
78 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
);
79 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
,
80 u32 vind
, bool vlan_on
);
81 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
);
82 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
,
83 ixgbe_link_speed
*speed
,
84 bool *link_up
, bool link_up_wait_to_complete
);
86 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
);
87 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
);
89 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
92 #define writeq(val, addr) writel((u32) (val), addr); \
93 writel((u32) (val >> 32), (addr + 4));
96 #define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
98 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
100 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
101 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
103 #define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
104 readl((a)->hw_addr + (reg) + ((offset) << 2)))
106 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
108 extern struct net_device
*ixgbe_get_hw_dev(struct ixgbe_hw
*hw
);
109 #define hw_dbg(hw, format, arg...) \
110 netdev_dbg(ixgbe_get_hw_dev(hw), format, ##arg)
111 #define e_dev_info(format, arg...) \
112 dev_info(&adapter->pdev->dev, format, ## arg)
113 #define e_dev_warn(format, arg...) \
114 dev_warn(&adapter->pdev->dev, format, ## arg)
115 #define e_dev_err(format, arg...) \
116 dev_err(&adapter->pdev->dev, format, ## arg)
117 #define e_dev_notice(format, arg...) \
118 dev_notice(&adapter->pdev->dev, format, ## arg)
119 #define e_info(msglvl, format, arg...) \
120 netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
121 #define e_err(msglvl, format, arg...) \
122 netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
123 #define e_warn(msglvl, format, arg...) \
124 netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
125 #define e_crit(msglvl, format, arg...) \
126 netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
127 #endif /* IXGBE_COMMON */