drivers/spi/spi-pxa2xx.h

   1 /*
   2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3  * Copyright (C) 2013, Intel Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifndef SPI_PXA2XX_H
  11 #define SPI_PXA2XX_H
  12
  13 #include <linux/atomic.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/errno.h>
  16 #include <linux/io.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pxa2xx_ssp.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/sizes.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/pxa2xx_spi.h>
  24
  25 struct driver_data {
  26         /* Driver model hookup */
  27         struct platform_device *pdev;
  28
  29         /* SSP Info */
  30         struct ssp_device *ssp;
  31
  32         /* SPI framework hookup */
  33         enum pxa_ssp_type ssp_type;
  34         struct spi_master *master;
  35
  36         /* PXA hookup */
  37         struct pxa2xx_spi_master *master_info;
  38
  39         /* PXA private DMA setup stuff */
  40         int rx_channel;
  41         int tx_channel;
  42         u32 *null_dma_buf;
  43
  44         /* SSP register addresses */
  45         void __iomem *ioaddr;
  46         u32 ssdr_physical;
  47
  48         /* SSP masks*/
  49         u32 dma_cr1;
  50         u32 int_cr1;
  51         u32 clear_sr;
  52         u32 mask_sr;
  53
  54         /* Maximun clock rate */
  55         unsigned long max_clk_rate;
  56
  57         /* Message Transfer pump */
  58         struct tasklet_struct pump_transfers;
  59
  60         /* DMA engine support */
  61         struct dma_chan *rx_chan;
  62         struct dma_chan *tx_chan;
  63         struct sg_table rx_sgt;
  64         struct sg_table tx_sgt;
  65         int rx_nents;
  66         int tx_nents;
  67         void *dummy;
  68         atomic_t dma_running;
  69
  70         /* Current message transfer state info */
  71         struct spi_message *cur_msg;
  72         struct spi_transfer *cur_transfer;
  73         struct chip_data *cur_chip;
  74         size_t len;
  75         void *tx;
  76         void *tx_end;
  77         void *rx;
  78         void *rx_end;
  79         int dma_mapped;
  80         dma_addr_t rx_dma;
  81         dma_addr_t tx_dma;
  82         size_t rx_map_len;
  83         size_t tx_map_len;
  84         u8 n_bytes;
  85         int (*write)(struct driver_data *drv_data);
  86         int (*read)(struct driver_data *drv_data);
  87         irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
  88         void (*cs_control)(u32 command);
  89
  90         void __iomem *lpss_base;
  91 };
  92
  93 struct chip_data {
  94         u32 cr0;
  95         u32 cr1;
  96         u32 dds_rate;
  97         u32 psp;
  98         u32 timeout;
  99         u8 n_bytes;
 100         u32 dma_burst_size;
 101         u32 threshold;
 102         u32 dma_threshold;
 103         u16 lpss_rx_threshold;
 104         u16 lpss_tx_threshold;
 105         u8 enable_dma;
 106         u8 bits_per_word;
 107         u32 speed_hz;
 108         union {
 109                 int gpio_cs;
 110                 unsigned int frm;
 111         };
 112         int gpio_cs_inverted;
 113         int (*write)(struct driver_data *drv_data);
 114         int (*read)(struct driver_data *drv_data);
 115         void (*cs_control)(u32 command);
 116 };
 117
 118 #define DEFINE_SSP_REG(reg, off) \
 119 static inline u32 read_##reg(void const __iomem *p) \
 120 { return __raw_readl(p + (off)); } \
 121 \
 122 static inline void write_##reg(u32 v, void __iomem *p) \
 123 { __raw_writel(v, p + (off)); }
 124
 125 DEFINE_SSP_REG(SSCR0, 0x00)
 126 DEFINE_SSP_REG(SSCR1, 0x04)
 127 DEFINE_SSP_REG(SSSR, 0x08)
 128 DEFINE_SSP_REG(SSITR, 0x0c)
 129 DEFINE_SSP_REG(SSDR, 0x10)
 130 DEFINE_SSP_REG(DDS_RATE, 0x28)  /* DDS Clock Rate */
 131 DEFINE_SSP_REG(SSTO, 0x28)
 132 DEFINE_SSP_REG(SSPSP, 0x2c)
 133 DEFINE_SSP_REG(SSITF, SSITF)
 134 DEFINE_SSP_REG(SSIRF, SSIRF)
 135
 136 #define START_STATE ((void *)0)
 137 #define RUNNING_STATE ((void *)1)
 138 #define DONE_STATE ((void *)2)
 139 #define ERROR_STATE ((void *)-1)
 140
 141 #define IS_DMA_ALIGNED(x)       IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
 142 #define DMA_ALIGNMENT           8
 143
 144 static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
 145 {
 146         switch (drv_data->ssp_type) {
 147         case PXA25x_SSP:
 148         case CE4100_SSP:
 149         case QUARK_X1000_SSP:
 150                 return 1;
 151         default:
 152                 return 0;
 153         }
 154 }
 155
 156 static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
 157 {
 158         void __iomem *reg = drv_data->ioaddr;
 159
 160         if (drv_data->ssp_type == CE4100_SSP ||
 161             drv_data->ssp_type == QUARK_X1000_SSP)
 162                 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
 163
 164         write_SSSR(val, reg);
 165 }
 166
 167 extern int pxa2xx_spi_flush(struct driver_data *drv_data);
 168 extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
 169
 170 /*
 171  * Select the right DMA implementation.
 172  */
 173 #if defined(CONFIG_SPI_PXA2XX_PXADMA)
 174 #define SPI_PXA2XX_USE_DMA      1
 175 #define MAX_DMA_LEN             8191
 176 #define DEFAULT_DMA_CR1         (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE)
 177 #elif defined(CONFIG_SPI_PXA2XX_DMA)
 178 #define SPI_PXA2XX_USE_DMA      1
 179 #define MAX_DMA_LEN             SZ_64K
 180 #define DEFAULT_DMA_CR1         (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
 181 #else
 182 #undef SPI_PXA2XX_USE_DMA
 183 #define MAX_DMA_LEN             0
 184 #define DEFAULT_DMA_CR1         0
 185 #endif
 186
 187 #ifdef SPI_PXA2XX_USE_DMA
 188 extern bool pxa2xx_spi_dma_is_possible(size_t len);
 189 extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data);
 190 extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
 191 extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
 192 extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
 193 extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
 194 extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
 195 extern void pxa2xx_spi_dma_resume(struct driver_data *drv_data);
 196 extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
 197                                                   struct spi_device *spi,
 198                                                   u8 bits_per_word,
 199                                                   u32 *burst_code,
 200                                                   u32 *threshold);
 201 #else
 202 static inline bool pxa2xx_spi_dma_is_possible(size_t len) { return false; }
 203 static inline int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
 204 {
 205         return 0;
 206 }
 207 #define pxa2xx_spi_dma_transfer NULL
 208 static inline void pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
 209                                           u32 dma_burst) {}
 210 static inline void pxa2xx_spi_dma_start(struct driver_data *drv_data) {}
 211 static inline int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
 212 {
 213         return 0;
 214 }
 215 static inline void pxa2xx_spi_dma_release(struct driver_data *drv_data) {}
 216 static inline void pxa2xx_spi_dma_resume(struct driver_data *drv_data) {}
 217 static inline int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
 218                                                          struct spi_device *spi,
 219                                                          u8 bits_per_word,
 220                                                          u32 *burst_code,
 221                                                          u32 *threshold)
 222 {
 223         return -ENODEV;
 224 }
 225 #endif
 226
 227 #endif /* SPI_PXA2XX_H */