drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9485_initvals.h"
  21 #include "ar9340_initvals.h"
  22 #include "ar9330_1p1_initvals.h"
  23 #include "ar9330_1p2_initvals.h"
  24 #include "ar955x_1p0_initvals.h"
  25 #include "ar9580_1p0_initvals.h"
  26 #include "ar9462_2p0_initvals.h"
  27
  28 /* General hardware code for the AR9003 hadware family */
  29
  30 /*
  31  * The AR9003 family uses a new INI format (pre, core, post
  32  * arrays per subsystem). This provides support for the
  33  * AR9003 2.2 chipsets.
  34  */
  35 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  36 {
  37 #define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
  38                 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
  39
  40 #define AR9462_BB_CTX_COEFJ(x)  \
  41                 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
  42
  43 #define AR9462_BBC_TXIFR_COEFFJ \
  44                 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
  45         if (AR_SREV_9330_11(ah)) {
  46                 /* mac */
  47                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
  48                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  49                                 ar9331_1p1_mac_core,
  50                                 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
  51                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  52                                 ar9331_1p1_mac_postamble,
  53                                 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
  54
  55                 /* bb */
  56                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
  57                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  58                                 ar9331_1p1_baseband_core,
  59                                 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
  60                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  61                                 ar9331_1p1_baseband_postamble,
  62                                 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
  63
  64                 /* radio */
  65                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
  66                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  67                                 ar9331_1p1_radio_core,
  68                                 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
  69                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
  70
  71                 /* soc */
  72                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  73                                 ar9331_1p1_soc_preamble,
  74                                 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
  75                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
  76                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  77                                 ar9331_1p1_soc_postamble,
  78                                 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
  79
  80                 /* rx/tx gain */
  81                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  82                                 ar9331_common_rx_gain_1p1,
  83                                 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
  84                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  85                         ar9331_modes_lowest_ob_db_tx_gain_1p1,
  86                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
  87                         5);
  88
  89                 /* additional clock settings */
  90                 if (ah->is_clk_25mhz)
  91                         INIT_INI_ARRAY(&ah->iniAdditional,
  92                                         ar9331_1p1_xtal_25M,
  93                                         ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
  94                 else
  95                         INIT_INI_ARRAY(&ah->iniAdditional,
  96                                         ar9331_1p1_xtal_40M,
  97                                         ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
  98         } else if (AR_SREV_9330_12(ah)) {
  99                 /* mac */
 100                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 101                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 102                                 ar9331_1p2_mac_core,
 103                                 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
 104                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 105                                 ar9331_1p2_mac_postamble,
 106                                 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
 107
 108                 /* bb */
 109                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 110                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 111                                 ar9331_1p2_baseband_core,
 112                                 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
 113                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 114                                 ar9331_1p2_baseband_postamble,
 115                                 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
 116
 117                 /* radio */
 118                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 119                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 120                                 ar9331_1p2_radio_core,
 121                                 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
 122                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
 123
 124                 /* soc */
 125                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 126                                 ar9331_1p2_soc_preamble,
 127                                 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
 128                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 129                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 130                                 ar9331_1p2_soc_postamble,
 131                                 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
 132
 133                 /* rx/tx gain */
 134                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 135                                 ar9331_common_rx_gain_1p2,
 136                                 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
 137                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 138                         ar9331_modes_lowest_ob_db_tx_gain_1p2,
 139                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 140                         5);
 141
 142                 /* additional clock settings */
 143                 if (ah->is_clk_25mhz)
 144                         INIT_INI_ARRAY(&ah->iniAdditional,
 145                                         ar9331_1p2_xtal_25M,
 146                                         ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
 147                 else
 148                         INIT_INI_ARRAY(&ah->iniAdditional,
 149                                         ar9331_1p2_xtal_40M,
 150                                         ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
 151         } else if (AR_SREV_9340(ah)) {
 152                 /* mac */
 153                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 154                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 155                                 ar9340_1p0_mac_core,
 156                                 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
 157                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 158                                 ar9340_1p0_mac_postamble,
 159                                 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
 160
 161                 /* bb */
 162                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 163                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 164                                 ar9340_1p0_baseband_core,
 165                                 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
 166                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 167                                 ar9340_1p0_baseband_postamble,
 168                                 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
 169
 170                 /* radio */
 171                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 172                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 173                                 ar9340_1p0_radio_core,
 174                                 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
 175                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 176                                 ar9340_1p0_radio_postamble,
 177                                 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
 178
 179                 /* soc */
 180                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 181                                 ar9340_1p0_soc_preamble,
 182                                 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
 183                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 184                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 185                                 ar9340_1p0_soc_postamble,
 186                                 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
 187
 188                 /* rx/tx gain */
 189                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 190                                 ar9340Common_wo_xlna_rx_gain_table_1p0,
 191                                 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 192                                 5);
 193                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 194                                 ar9340Modes_high_ob_db_tx_gain_table_1p0,
 195                                 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
 196                                 5);
 197
 198                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 199                                 ar9340Modes_fast_clock_1p0,
 200                                 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
 201                                 3);
 202
 203                 if (!ah->is_clk_25mhz)
 204                         INIT_INI_ARRAY(&ah->iniAdditional,
 205                                        ar9340_1p0_radio_core_40M,
 206                                        ARRAY_SIZE(ar9340_1p0_radio_core_40M),
 207                                        2);
 208         } else if (AR_SREV_9485_11(ah)) {
 209                 /* mac */
 210                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 211                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 212                                 ar9485_1_1_mac_core,
 213                                 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
 214                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 215                                 ar9485_1_1_mac_postamble,
 216                                 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
 217
 218                 /* bb */
 219                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
 220                                 ARRAY_SIZE(ar9485_1_1), 2);
 221                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 222                                 ar9485_1_1_baseband_core,
 223                                 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
 224                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 225                                 ar9485_1_1_baseband_postamble,
 226                                 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
 227
 228                 /* radio */
 229                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 230                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 231                                 ar9485_1_1_radio_core,
 232                                 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
 233                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 234                                 ar9485_1_1_radio_postamble,
 235                                 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
 236
 237                 /* soc */
 238                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 239                                 ar9485_1_1_soc_preamble,
 240                                 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
 241                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 242                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
 243
 244                 /* rx/tx gain */
 245                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 246                                 ar9485Common_wo_xlna_rx_gain_1_1,
 247                                 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
 248                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 249                                 ar9485_modes_lowest_ob_db_tx_gain_1_1,
 250                                 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 251                                 5);
 252
 253                 /* Load PCIE SERDES settings from INI */
 254
 255                 /* Awake Setting */
 256
 257                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 258                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 259                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 260                                 2);
 261
 262                 /* Sleep Setting */
 263
 264                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 265                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 266                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 267                                 2);
 268         } else if (AR_SREV_9462_20(ah)) {
 269
 270                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 271                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
 272                                 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
 273                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 274                                 ar9462_2p0_mac_postamble,
 275                                 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
 276
 277                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 278                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 279                                 ar9462_2p0_baseband_core,
 280                                 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
 281                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 282                                 ar9462_2p0_baseband_postamble,
 283                                 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
 284
 285                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 286                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 287                                 ar9462_2p0_radio_core,
 288                                 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
 289                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 290                                 ar9462_2p0_radio_postamble,
 291                                 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
 292                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 293                                 ar9462_2p0_radio_postamble_sys2ant,
 294                                 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
 295                                 5);
 296
 297                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 298                                 ar9462_2p0_soc_preamble,
 299                                 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
 300                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 301                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 302                                 ar9462_2p0_soc_postamble,
 303                                 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
 304
 305                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 306                                 ar9462_common_rx_gain_table_2p0,
 307                                 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
 308
 309                 /* Awake -> Sleep Setting */
 310                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 311                                 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 312                                 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 313                                 2);
 314                 /* Sleep -> Awake Setting */
 315                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 316                                 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 317                                 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 318                                 2);
 319
 320                 /* Fast clock modal settings */
 321                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 322                                 ar9462_modes_fast_clock_2p0,
 323                                 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
 324
 325                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 326                                 AR9462_BB_CTX_COEFJ(2p0),
 327                                 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
 328
 329                 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
 330                                 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
 331         } else if (AR_SREV_9550(ah)) {
 332                 /* mac */
 333                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 334                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 335                                 ar955x_1p0_mac_core,
 336                                 ARRAY_SIZE(ar955x_1p0_mac_core), 2);
 337                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 338                                 ar955x_1p0_mac_postamble,
 339                                 ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
 340
 341                 /* bb */
 342                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 343                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 344                                 ar955x_1p0_baseband_core,
 345                                 ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
 346                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 347                                 ar955x_1p0_baseband_postamble,
 348                                 ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
 349
 350                 /* radio */
 351                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 352                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 353                                 ar955x_1p0_radio_core,
 354                                 ARRAY_SIZE(ar955x_1p0_radio_core), 2);
 355                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 356                                 ar955x_1p0_radio_postamble,
 357                                 ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
 358
 359                 /* soc */
 360                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 361                                 ar955x_1p0_soc_preamble,
 362                                 ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
 363                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 364                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 365                                 ar955x_1p0_soc_postamble,
 366                                 ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
 367
 368                 /* rx/tx gain */
 369                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 370                         ar955x_1p0_common_wo_xlna_rx_gain_table,
 371                         ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
 372                         2);
 373                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 374                         ar955x_1p0_common_wo_xlna_rx_gain_bounds,
 375                         ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
 376                         5);
 377                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 378                                 ar955x_1p0_modes_xpa_tx_gain_table,
 379                                 ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
 380                                 9);
 381
 382                 /* Fast clock modal settings */
 383                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 384                                 ar955x_1p0_modes_fast_clock,
 385                                 ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
 386         } else if (AR_SREV_9580(ah)) {
 387                 /* mac */
 388                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 389                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 390                                 ar9580_1p0_mac_core,
 391                                 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
 392                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 393                                 ar9580_1p0_mac_postamble,
 394                                 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
 395
 396                 /* bb */
 397                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 398                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 399                                 ar9580_1p0_baseband_core,
 400                                 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
 401                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 402                                 ar9580_1p0_baseband_postamble,
 403                                 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
 404
 405                 /* radio */
 406                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 407                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 408                                 ar9580_1p0_radio_core,
 409                                 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
 410                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 411                                 ar9580_1p0_radio_postamble,
 412                                 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
 413
 414                 /* soc */
 415                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 416                                 ar9580_1p0_soc_preamble,
 417                                 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
 418                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 419                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 420                                 ar9580_1p0_soc_postamble,
 421                                 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
 422
 423                 /* rx/tx gain */
 424                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 425                                 ar9580_1p0_rx_gain_table,
 426                                 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
 427                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 428                                 ar9580_1p0_low_ob_db_tx_gain_table,
 429                                 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 430                                 5);
 431
 432                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 433                                 ar9580_1p0_modes_fast_clock,
 434                                 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
 435                                 3);
 436         } else {
 437                 /* mac */
 438                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 439                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 440                                 ar9300_2p2_mac_core,
 441                                 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
 442                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 443                                 ar9300_2p2_mac_postamble,
 444                                 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
 445
 446                 /* bb */
 447                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 448                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 449                                 ar9300_2p2_baseband_core,
 450                                 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
 451                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 452                                 ar9300_2p2_baseband_postamble,
 453                                 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
 454
 455                 /* radio */
 456                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 457                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 458                                 ar9300_2p2_radio_core,
 459                                 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
 460                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 461                                 ar9300_2p2_radio_postamble,
 462                                 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
 463
 464                 /* soc */
 465                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 466                                 ar9300_2p2_soc_preamble,
 467                                 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
 468                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 469                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 470                                 ar9300_2p2_soc_postamble,
 471                                 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
 472
 473                 /* rx/tx gain */
 474                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 475                                 ar9300Common_rx_gain_table_2p2,
 476                                 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
 477                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 478                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 479                                 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 480                                 5);
 481
 482                 /* Load PCIE SERDES settings from INI */
 483
 484                 /* Awake Setting */
 485
 486                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 487                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 488                                 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 489                                 2);
 490
 491                 /* Sleep Setting */
 492
 493                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 494                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 495                                 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 496                                 2);
 497
 498                 /* Fast clock modal settings */
 499                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 500                                 ar9300Modes_fast_clock_2p2,
 501                                 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
 502                                 3);
 503         }
 504 }
 505
 506 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 507 {
 508         if (AR_SREV_9330_12(ah))
 509                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 510                         ar9331_modes_lowest_ob_db_tx_gain_1p2,
 511                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 512                         5);
 513         else if (AR_SREV_9330_11(ah))
 514                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 515                         ar9331_modes_lowest_ob_db_tx_gain_1p1,
 516                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
 517                         5);
 518         else if (AR_SREV_9340(ah))
 519                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 520                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 521                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 522                         5);
 523         else if (AR_SREV_9485_11(ah))
 524                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 525                         ar9485_modes_lowest_ob_db_tx_gain_1_1,
 526                         ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 527                         5);
 528         else if (AR_SREV_9550(ah))
 529                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 530                         ar955x_1p0_modes_xpa_tx_gain_table,
 531                         ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
 532                         9);
 533         else if (AR_SREV_9580(ah))
 534                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 535                         ar9580_1p0_lowest_ob_db_tx_gain_table,
 536                         ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
 537                         5);
 538         else if (AR_SREV_9462_20(ah))
 539                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 540                         ar9462_modes_low_ob_db_tx_gain_table_2p0,
 541                         ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
 542                         5);
 543         else
 544                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 545                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 546                         ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 547                         5);
 548 }
 549
 550 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 551 {
 552         if (AR_SREV_9330_12(ah))
 553                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 554                         ar9331_modes_high_ob_db_tx_gain_1p2,
 555                         ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
 556                         5);
 557         else if (AR_SREV_9330_11(ah))
 558                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 559                         ar9331_modes_high_ob_db_tx_gain_1p1,
 560                         ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
 561                         5);
 562         else if (AR_SREV_9340(ah))
 563                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 564                         ar9340Modes_high_ob_db_tx_gain_table_1p0,
 565                         ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
 566                         5);
 567         else if (AR_SREV_9485_11(ah))
 568                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 569                         ar9485Modes_high_ob_db_tx_gain_1_1,
 570                         ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
 571                         5);
 572         else if (AR_SREV_9580(ah))
 573                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 574                         ar9580_1p0_high_ob_db_tx_gain_table,
 575                         ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
 576                         5);
 577         else if (AR_SREV_9550(ah))
 578                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 579                         ar955x_1p0_modes_no_xpa_tx_gain_table,
 580                         ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
 581                         9);
 582         else if (AR_SREV_9462_20(ah))
 583                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 584                         ar9462_modes_high_ob_db_tx_gain_table_2p0,
 585                         ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
 586                         5);
 587         else
 588                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 589                         ar9300Modes_high_ob_db_tx_gain_table_2p2,
 590                         ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
 591                         5);
 592 }
 593
 594 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 595 {
 596         if (AR_SREV_9330_12(ah))
 597                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 598                         ar9331_modes_low_ob_db_tx_gain_1p2,
 599                         ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
 600                         5);
 601         else if (AR_SREV_9330_11(ah))
 602                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 603                         ar9331_modes_low_ob_db_tx_gain_1p1,
 604                         ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
 605                         5);
 606         else if (AR_SREV_9340(ah))
 607                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 608                         ar9340Modes_low_ob_db_tx_gain_table_1p0,
 609                         ARRAY_SIZE(ar9340Modes_low_ob_db_tx_gain_table_1p0),
 610                         5);
 611         else if (AR_SREV_9485_11(ah))
 612                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 613                         ar9485Modes_low_ob_db_tx_gain_1_1,
 614                         ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
 615                         5);
 616         else if (AR_SREV_9580(ah))
 617                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 618                         ar9580_1p0_low_ob_db_tx_gain_table,
 619                         ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 620                         5);
 621         else
 622                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 623                         ar9300Modes_low_ob_db_tx_gain_table_2p2,
 624                         ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
 625                         5);
 626 }
 627
 628 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 629 {
 630         if (AR_SREV_9330_12(ah))
 631                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 632                         ar9331_modes_high_power_tx_gain_1p2,
 633                         ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
 634                         5);
 635         else if (AR_SREV_9330_11(ah))
 636                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 637                         ar9331_modes_high_power_tx_gain_1p1,
 638                         ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
 639                         5);
 640         else if (AR_SREV_9340(ah))
 641                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 642                         ar9340Modes_high_power_tx_gain_table_1p0,
 643                         ARRAY_SIZE(ar9340Modes_high_power_tx_gain_table_1p0),
 644                         5);
 645         else if (AR_SREV_9485_11(ah))
 646                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 647                         ar9485Modes_high_power_tx_gain_1_1,
 648                         ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
 649                         5);
 650         else if (AR_SREV_9580(ah))
 651                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 652                         ar9580_1p0_high_power_tx_gain_table,
 653                         ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
 654                         5);
 655         else
 656                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 657                         ar9300Modes_high_power_tx_gain_table_2p2,
 658                         ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
 659                         5);
 660 }
 661
 662 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 663 {
 664         if (AR_SREV_9340(ah))
 665                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 666                         ar9340Modes_mixed_ob_db_tx_gain_table_1p0,
 667                         ARRAY_SIZE(ar9340Modes_mixed_ob_db_tx_gain_table_1p0),
 668                         5);
 669         else if (AR_SREV_9580(ah))
 670                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 671                         ar9580_1p0_mixed_ob_db_tx_gain_table,
 672                         ARRAY_SIZE(ar9580_1p0_mixed_ob_db_tx_gain_table),
 673                         5);
 674 }
 675
 676 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 677 {
 678         switch (ar9003_hw_get_tx_gain_idx(ah)) {
 679         case 0:
 680         default:
 681                 ar9003_tx_gain_table_mode0(ah);
 682                 break;
 683         case 1:
 684                 ar9003_tx_gain_table_mode1(ah);
 685                 break;
 686         case 2:
 687                 ar9003_tx_gain_table_mode2(ah);
 688                 break;
 689         case 3:
 690                 ar9003_tx_gain_table_mode3(ah);
 691                 break;
 692         case 4:
 693                 ar9003_tx_gain_table_mode4(ah);
 694                 break;
 695         }
 696 }
 697
 698 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 699 {
 700         if (AR_SREV_9330_12(ah))
 701                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 702                                 ar9331_common_rx_gain_1p2,
 703                                 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
 704                                 2);
 705         else if (AR_SREV_9330_11(ah))
 706                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 707                                 ar9331_common_rx_gain_1p1,
 708                                 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
 709                                 2);
 710         else if (AR_SREV_9340(ah))
 711                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 712                                 ar9340Common_rx_gain_table_1p0,
 713                                 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
 714                                 2);
 715         else if (AR_SREV_9485_11(ah))
 716                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 717                                 ar9485Common_wo_xlna_rx_gain_1_1,
 718                                 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 719                                 2);
 720         else if (AR_SREV_9550(ah)) {
 721                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 722                                 ar955x_1p0_common_rx_gain_table,
 723                                 ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
 724                                 2);
 725                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 726                                 ar955x_1p0_common_rx_gain_bounds,
 727                                 ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
 728                                 5);
 729         } else if (AR_SREV_9580(ah))
 730                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 731                                 ar9580_1p0_rx_gain_table,
 732                                 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
 733                                 2);
 734         else if (AR_SREV_9462_20(ah))
 735                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 736                                 ar9462_common_rx_gain_table_2p0,
 737                                 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
 738                                 2);
 739         else
 740                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 741                                 ar9300Common_rx_gain_table_2p2,
 742                                 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
 743                                 2);
 744 }
 745
 746 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 747 {
 748         if (AR_SREV_9330_12(ah))
 749                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 750                         ar9331_common_wo_xlna_rx_gain_1p2,
 751                         ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
 752                         2);
 753         else if (AR_SREV_9330_11(ah))
 754                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 755                         ar9331_common_wo_xlna_rx_gain_1p1,
 756                         ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
 757                         2);
 758         else if (AR_SREV_9340(ah))
 759                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 760                         ar9340Common_wo_xlna_rx_gain_table_1p0,
 761                         ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 762                         2);
 763         else if (AR_SREV_9485_11(ah))
 764                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 765                         ar9485Common_wo_xlna_rx_gain_1_1,
 766                         ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 767                         2);
 768         else if (AR_SREV_9462_20(ah))
 769                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 770                         ar9462_common_wo_xlna_rx_gain_table_2p0,
 771                         ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
 772                         2);
 773         else if (AR_SREV_9550(ah)) {
 774                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 775                         ar955x_1p0_common_wo_xlna_rx_gain_table,
 776                         ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
 777                         2);
 778                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 779                         ar955x_1p0_common_wo_xlna_rx_gain_bounds,
 780                         ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
 781                         5);
 782         } else if (AR_SREV_9580(ah))
 783                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 784                         ar9580_1p0_wo_xlna_rx_gain_table,
 785                         ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
 786                         2);
 787         else
 788                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 789                         ar9300Common_wo_xlna_rx_gain_table_2p2,
 790                         ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
 791                         2);
 792 }
 793
 794 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 795 {
 796         if (AR_SREV_9462_20(ah))
 797                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 798                                ar9462_common_mixed_rx_gain_table_2p0,
 799                                ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
 800 }
 801
 802 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 803 {
 804         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 805         case 0:
 806         default:
 807                 ar9003_rx_gain_table_mode0(ah);
 808                 break;
 809         case 1:
 810                 ar9003_rx_gain_table_mode1(ah);
 811                 break;
 812         case 2:
 813                 ar9003_rx_gain_table_mode2(ah);
 814                 break;
 815         }
 816 }
 817
 818 /* set gain table pointers according to values read from the eeprom */
 819 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 820 {
 821         ar9003_tx_gain_table_apply(ah);
 822         ar9003_rx_gain_table_apply(ah);
 823 }
 824
 825 /*
 826  * Helper for ASPM support.
 827  *
 828  * Disable PLL when in L0s as well as receiver clock when in L1.
 829  * This power saving option must be enabled through the SerDes.
 830  *
 831  * Programming the SerDes must go through the same 288 bit serial shift
 832  * register as the other analog registers.  Hence the 9 writes.
 833  */
 834 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 835                                          bool power_off)
 836 {
 837         /* Nothing to do on restore for 11N */
 838         if (!power_off /* !restore */) {
 839                 /* set bit 19 to allow forcing of pcie core into L1 state */
 840                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 841
 842                 /* Several PCIe massages to ensure proper behaviour */
 843                 if (ah->config.pcie_waen)
 844                         REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
 845                 else
 846                         REG_WRITE(ah, AR_WA, ah->WARegVal);
 847         }
 848
 849         /*
 850          * Configire PCIE after Ini init. SERDES values now come from ini file
 851          * This enables PCIe low power mode.
 852          */
 853         if (ah->config.pcieSerDesWrite) {
 854                 unsigned int i;
 855                 struct ar5416IniArray *array;
 856
 857                 array = power_off ? &ah->iniPcieSerdes :
 858                                     &ah->iniPcieSerdesLowPower;
 859
 860                 for (i = 0; i < array->ia_rows; i++) {
 861                         REG_WRITE(ah,
 862                                   INI_RA(array, i, 0),
 863                                   INI_RA(array, i, 1));
 864                 }
 865         }
 866 }
 867
 868 /* Sets up the AR9003 hardware familiy callbacks */
 869 void ar9003_hw_attach_ops(struct ath_hw *ah)
 870 {
 871         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 872         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 873
 874         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
 875         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
 876
 877         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
 878
 879         ar9003_hw_attach_phy_ops(ah);
 880         ar9003_hw_attach_calib_ops(ah);
 881         ar9003_hw_attach_mac_ops(ah);
 882 }