drivers/spi/spi-pxa2xx.h

   1 /*
   2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3  * Copyright (C) 2013, Intel Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifndef SPI_PXA2XX_H
  11 #define SPI_PXA2XX_H
  12
  13 #include <linux/atomic.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/errno.h>
  16 #include <linux/io.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pxa2xx_ssp.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/sizes.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/pxa2xx_spi.h>
  24
  25 struct driver_data {
  26         /* Driver model hookup */
  27         struct platform_device *pdev;
  28
  29         /* SSP Info */
  30         struct ssp_device *ssp;
  31
  32         /* SPI framework hookup */
  33         enum pxa_ssp_type ssp_type;
  34         struct spi_master *master;
  35
  36         /* PXA hookup */
  37         struct pxa2xx_spi_master *master_info;
  38
  39         /* SSP register addresses */
  40         void __iomem *ioaddr;
  41         u32 ssdr_physical;
  42
  43         /* SSP masks*/
  44         u32 dma_cr1;
  45         u32 int_cr1;
  46         u32 clear_sr;
  47         u32 mask_sr;
  48
  49         /* Message Transfer pump */
  50         struct tasklet_struct pump_transfers;
  51
  52         /* DMA engine support */
  53         struct dma_chan *rx_chan;
  54         struct dma_chan *tx_chan;
  55         struct sg_table rx_sgt;
  56         struct sg_table tx_sgt;
  57         int rx_nents;
  58         int tx_nents;
  59         atomic_t dma_running;
  60
  61         /* Current message transfer state info */
  62         struct spi_message *cur_msg;
  63         struct spi_transfer *cur_transfer;
  64         struct chip_data *cur_chip;
  65         size_t len;
  66         void *tx;
  67         void *tx_end;
  68         void *rx;
  69         void *rx_end;
  70         int dma_mapped;
  71         u8 n_bytes;
  72         int (*write)(struct driver_data *drv_data);
  73         int (*read)(struct driver_data *drv_data);
  74         irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
  75         void (*cs_control)(u32 command);
  76
  77         void __iomem *lpss_base;
  78 };
  79
  80 struct chip_data {
  81         u32 cr1;
  82         u32 dds_rate;
  83         u32 timeout;
  84         u8 n_bytes;
  85         u32 dma_burst_size;
  86         u32 threshold;
  87         u32 dma_threshold;
  88         u16 lpss_rx_threshold;
  89         u16 lpss_tx_threshold;
  90         u8 enable_dma;
  91         union {
  92                 int gpio_cs;
  93                 unsigned int frm;
  94         };
  95         int gpio_cs_inverted;
  96         int (*write)(struct driver_data *drv_data);
  97         int (*read)(struct driver_data *drv_data);
  98         void (*cs_control)(u32 command);
  99 };
 100
 101 static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
 102                                   unsigned reg)
 103 {
 104         return __raw_readl(drv_data->ioaddr + reg);
 105 }
 106
 107 static  inline void pxa2xx_spi_write(const struct driver_data *drv_data,
 108                                      unsigned reg, u32 val)
 109 {
 110         __raw_writel(val, drv_data->ioaddr + reg);
 111 }
 112
 113 #define START_STATE ((void *)0)
 114 #define RUNNING_STATE ((void *)1)
 115 #define DONE_STATE ((void *)2)
 116 #define ERROR_STATE ((void *)-1)
 117
 118 #define IS_DMA_ALIGNED(x)       IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
 119 #define DMA_ALIGNMENT           8
 120
 121 static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
 122 {
 123         switch (drv_data->ssp_type) {
 124         case PXA25x_SSP:
 125         case CE4100_SSP:
 126         case QUARK_X1000_SSP:
 127                 return 1;
 128         default:
 129                 return 0;
 130         }
 131 }
 132
 133 static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
 134 {
 135         if (drv_data->ssp_type == CE4100_SSP ||
 136             drv_data->ssp_type == QUARK_X1000_SSP)
 137                 val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
 138
 139         pxa2xx_spi_write(drv_data, SSSR, val);
 140 }
 141
 142 extern int pxa2xx_spi_flush(struct driver_data *drv_data);
 143 extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
 144
 145 #define MAX_DMA_LEN             SZ_64K
 146 #define DEFAULT_DMA_CR1         (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
 147
 148 extern bool pxa2xx_spi_dma_is_possible(size_t len);
 149 extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data);
 150 extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
 151 extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
 152 extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
 153 extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
 154 extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
 155 extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
 156                                                   struct spi_device *spi,
 157                                                   u8 bits_per_word,
 158                                                   u32 *burst_code,
 159                                                   u32 *threshold);
 160
 161 #endif /* SPI_PXA2XX_H */