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lkdtm: Add Control Flow Integrity test
[linux/fpc-iii.git] / drivers / net / phy / aquantia_main.c
blob3b29d381116f8e88dc25dc0d17c485db2b4ef6e2
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Aquantia PHY
4 *
5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
6 *
7 * Copyright 2015 Freescale Semiconductor, Inc.
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/bitfield.h>
14 #include <linux/phy.h>
15
16 #include "aquantia.h"
17
18 #define PHY_ID_AQ1202 0x03a1b445
19 #define PHY_ID_AQ2104 0x03a1b460
20 #define PHY_ID_AQR105 0x03a1b4a2
21 #define PHY_ID_AQR106 0x03a1b4d0
22 #define PHY_ID_AQR107 0x03a1b4e0
23 #define PHY_ID_AQCS109 0x03a1b5c2
24 #define PHY_ID_AQR405 0x03a1b4b0
25
26 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
27 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
29 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
33
34 #define MDIO_AN_VEND_PROV 0xc400
35 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
36 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
37 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
38 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
39 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
40
41 #define MDIO_AN_TX_VEND_STATUS1 0xc800
42 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
43 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0
44 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
45 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
46 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
47 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
48 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
49 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
50
51 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
52 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
53
54 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
55
56 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401
57 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
58
59 #define MDIO_AN_RX_LP_STAT1 0xe820
60 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
61 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
62 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
63 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
64 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
65
66 #define MDIO_AN_RX_LP_STAT4 0xe823
67 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
68 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
69
70 #define MDIO_AN_RX_VEND_STAT3 0xe832
71 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
72
73 /* MDIO_MMD_C22EXT */
74 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
75 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
76 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
77 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
78 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
79 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
80 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
81 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
82 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
83 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
84
85 /* Vendor specific 1, MDIO_MMD_VEND1 */
86 #define VEND1_GLOBAL_FW_ID 0x0020
87 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
88 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
89
90 #define VEND1_GLOBAL_RSVD_STAT1 0xc885
91 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
92 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
93
94 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d
95 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
96 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
97
98 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
99 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
100
101 #define VEND1_GLOBAL_INT_STD_MASK 0xff00
102 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
103 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
104 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
105 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
106 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
107 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
108 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
109 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
110 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
111 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
112 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
113
114 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01
115 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
116 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
117 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
118 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
119 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
120 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
121 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
122 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
123
124 struct aqr107_hw_stat {
125 const char *name;
126 int reg;
127 int size;
128 };
129
130 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
131 static const struct aqr107_hw_stat aqr107_hw_stats[] = {
132 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
133 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
134 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
135 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
136 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
137 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
138 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
139 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
140 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
141 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
142 };
143 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
144
145 struct aqr107_priv {
146 u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
147 };
148
149 static int aqr107_get_sset_count(struct phy_device *phydev)
150 {
151 return AQR107_SGMII_STAT_SZ;
152 }
153
154 static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
155 {
156 int i;
157
158 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
159 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
160 ETH_GSTRING_LEN);
161 }
162
163 static u64 aqr107_get_stat(struct phy_device *phydev, int index)
164 {
165 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
166 int len_l = min(stat->size, 16);
167 int len_h = stat->size - len_l;
168 u64 ret;
169 int val;
170
171 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
172 if (val < 0)
173 return U64_MAX;
174
175 ret = val & GENMASK(len_l - 1, 0);
176 if (len_h) {
177 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
178 if (val < 0)
179 return U64_MAX;
180
181 ret += (val & GENMASK(len_h - 1, 0)) << 16;
182 }
183
184 return ret;
185 }
186
187 static void aqr107_get_stats(struct phy_device *phydev,
188 struct ethtool_stats *stats, u64 *data)
189 {
190 struct aqr107_priv *priv = phydev->priv;
191 u64 val;
192 int i;
193
194 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
195 val = aqr107_get_stat(phydev, i);
196 if (val == U64_MAX)
197 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
198 aqr107_hw_stats[i].name);
199 else
200 priv->sgmii_stats[i] += val;
201
202 data[i] = priv->sgmii_stats[i];
203 }
204 }
205
206 static int aqr_config_aneg(struct phy_device *phydev)
207 {
208 bool changed = false;
209 u16 reg;
210 int ret;
211
212 if (phydev->autoneg == AUTONEG_DISABLE)
213 return genphy_c45_pma_setup_forced(phydev);
214
215 ret = genphy_c45_an_config_aneg(phydev);
216 if (ret < 0)
217 return ret;
218 if (ret > 0)
219 changed = true;
220
221 /* Clause 45 has no standardized support for 1000BaseT, therefore
222 * use vendor registers for this mode.
223 */
224 reg = 0;
225 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
226 phydev->advertising))
227 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
228
229 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
230 phydev->advertising))
231 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
232
233 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
234 MDIO_AN_VEND_PROV_1000BASET_HALF |
235 MDIO_AN_VEND_PROV_1000BASET_FULL, reg);
236 if (ret < 0)
237 return ret;
238 if (ret > 0)
239 changed = true;
240
241 return genphy_c45_check_and_restart_aneg(phydev, changed);
242 }
243
244 static int aqr_config_intr(struct phy_device *phydev)
245 {
246 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
247 int err;
248
249 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
250 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
251 if (err < 0)
252 return err;
253
254 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
255 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
256 if (err < 0)
257 return err;
258
259 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
260 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
261 VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
262 }
263
264 static int aqr_ack_interrupt(struct phy_device *phydev)
265 {
266 int reg;
267
268 reg = phy_read_mmd(phydev, MDIO_MMD_AN,
269 MDIO_AN_TX_VEND_INT_STATUS2);
270 return (reg < 0) ? reg : 0;
271 }
272
273 static int aqr_read_status(struct phy_device *phydev)
274 {
275 int val;
276
277 if (phydev->autoneg == AUTONEG_ENABLE) {
278 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
279 if (val < 0)
280 return val;
281
282 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
283 phydev->lp_advertising,
284 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
285 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
286 phydev->lp_advertising,
287 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
288 }
289
290 return genphy_c45_read_status(phydev);
291 }
292
293 static int aqr107_read_downshift_event(struct phy_device *phydev)
294 {
295 int val;
296
297 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS1);
298 if (val < 0)
299 return val;
300
301 return !!(val & MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT);
302 }
303
304 static int aqr107_read_rate(struct phy_device *phydev)
305 {
306 int val;
307
308 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
309 if (val < 0)
310 return val;
311
312 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
313 case MDIO_AN_TX_VEND_STATUS1_10BASET:
314 phydev->speed = SPEED_10;
315 break;
316 case MDIO_AN_TX_VEND_STATUS1_100BASETX:
317 phydev->speed = SPEED_100;
318 break;
319 case MDIO_AN_TX_VEND_STATUS1_1000BASET:
320 phydev->speed = SPEED_1000;
321 break;
322 case MDIO_AN_TX_VEND_STATUS1_2500BASET:
323 phydev->speed = SPEED_2500;
324 break;
325 case MDIO_AN_TX_VEND_STATUS1_5000BASET:
326 phydev->speed = SPEED_5000;
327 break;
328 case MDIO_AN_TX_VEND_STATUS1_10GBASET:
329 phydev->speed = SPEED_10000;
330 break;
331 default:
332 phydev->speed = SPEED_UNKNOWN;
333 break;
334 }
335
336 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
337 phydev->duplex = DUPLEX_FULL;
338 else
339 phydev->duplex = DUPLEX_HALF;
340
341 return 0;
342 }
343
344 static int aqr107_read_status(struct phy_device *phydev)
345 {
346 int val, ret;
347
348 ret = aqr_read_status(phydev);
349 if (ret)
350 return ret;
351
352 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
353 return 0;
354
355 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
356 if (val < 0)
357 return val;
358
359 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
360 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
361 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
362 phydev->interface = PHY_INTERFACE_MODE_10GKR;
363 break;
364 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
365 phydev->interface = PHY_INTERFACE_MODE_USXGMII;
366 break;
367 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
368 phydev->interface = PHY_INTERFACE_MODE_SGMII;
369 break;
370 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
371 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
372 break;
373 default:
374 phydev->interface = PHY_INTERFACE_MODE_NA;
375 break;
376 }
377
378 val = aqr107_read_downshift_event(phydev);
379 if (val <= 0)
380 return val;
381
382 phydev_warn(phydev, "Downshift occurred! Cabling may be defective.\n");
383
384 /* Read downshifted rate from vendor register */
385 return aqr107_read_rate(phydev);
386 }
387
388 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
389 {
390 int val, cnt, enable;
391
392 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
393 if (val < 0)
394 return val;
395
396 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
397 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
398
399 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
400
401 return 0;
402 }
403
404 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
405 {
406 int val = 0;
407
408 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
409 return -E2BIG;
410
411 if (cnt != DOWNSHIFT_DEV_DISABLE) {
412 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
413 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
414 }
415
416 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
417 MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
418 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
419 }
420
421 static int aqr107_get_tunable(struct phy_device *phydev,
422 struct ethtool_tunable *tuna, void *data)
423 {
424 switch (tuna->id) {
425 case ETHTOOL_PHY_DOWNSHIFT:
426 return aqr107_get_downshift(phydev, data);
427 default:
428 return -EOPNOTSUPP;
429 }
430 }
431
432 static int aqr107_set_tunable(struct phy_device *phydev,
433 struct ethtool_tunable *tuna, const void *data)
434 {
435 switch (tuna->id) {
436 case ETHTOOL_PHY_DOWNSHIFT:
437 return aqr107_set_downshift(phydev, *(const u8 *)data);
438 default:
439 return -EOPNOTSUPP;
440 }
441 }
442
443 /* If we configure settings whilst firmware is still initializing the chip,
444 * then these settings may be overwritten. Therefore make sure chip
445 * initialization has completed. Use presence of the firmware ID as
446 * indicator for initialization having completed.
447 * The chip also provides a "reset completed" bit, but it's cleared after
448 * read. Therefore function would time out if called again.
449 */
450 static int aqr107_wait_reset_complete(struct phy_device *phydev)
451 {
452 int val, retries = 100;
453
454 do {
455 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
456 if (val < 0)
457 return val;
458 msleep(20);
459 } while (!val && --retries);
460
461 return val ? 0 : -ETIMEDOUT;
462 }
463
464 static void aqr107_chip_info(struct phy_device *phydev)
465 {
466 u8 fw_major, fw_minor, build_id, prov_id;
467 int val;
468
469 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
470 if (val < 0)
471 return;
472
473 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
474 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
475
476 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
477 if (val < 0)
478 return;
479
480 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
481 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
482
483 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
484 fw_major, fw_minor, build_id, prov_id);
485 }
486
487 static int aqr107_config_init(struct phy_device *phydev)
488 {
489 int ret;
490
491 /* Check that the PHY interface type is compatible */
492 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
493 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
494 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
495 phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
496 phydev->interface != PHY_INTERFACE_MODE_10GKR)
497 return -ENODEV;
498
499 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
500 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
501
502 ret = aqr107_wait_reset_complete(phydev);
503 if (!ret)
504 aqr107_chip_info(phydev);
505
506 /* ensure that a latched downshift event is cleared */
507 aqr107_read_downshift_event(phydev);
508
509 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
510 }
511
512 static int aqcs109_config_init(struct phy_device *phydev)
513 {
514 int ret;
515
516 /* Check that the PHY interface type is compatible */
517 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
518 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
519 return -ENODEV;
520
521 ret = aqr107_wait_reset_complete(phydev);
522 if (!ret)
523 aqr107_chip_info(phydev);
524
525 /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
526 * PMA speed ability bits are the same for all members of the family,
527 * AQCS109 however supports speeds up to 2.5G only.
528 */
529 ret = phy_set_max_speed(phydev, SPEED_2500);
530 if (ret)
531 return ret;
532
533 /* ensure that a latched downshift event is cleared */
534 aqr107_read_downshift_event(phydev);
535
536 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
537 }
538
539 static void aqr107_link_change_notify(struct phy_device *phydev)
540 {
541 u8 fw_major, fw_minor;
542 bool downshift, short_reach, afr;
543 int mode, val;
544
545 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
546 return;
547
548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
549 /* call failed or link partner is no Aquantia PHY */
550 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
551 return;
552
553 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
554 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
555
556 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
557 if (val < 0)
558 return;
559
560 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
561 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
562
563 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
564 if (val < 0)
565 return;
566
567 afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
568
569 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
570 fw_major, fw_minor,
571 short_reach ? ", short reach mode" : "",
572 downshift ? ", fast-retrain downshift advertised" : "",
573 afr ? ", fast reframe advertised" : "");
574
575 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
576 if (val < 0)
577 return;
578
579 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
580 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
581 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
582 }
583
584 static int aqr107_suspend(struct phy_device *phydev)
585 {
586 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
587 MDIO_CTRL1_LPOWER);
588 }
589
590 static int aqr107_resume(struct phy_device *phydev)
591 {
592 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
593 MDIO_CTRL1_LPOWER);
594 }
595
596 static int aqr107_probe(struct phy_device *phydev)
597 {
598 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
599 sizeof(struct aqr107_priv), GFP_KERNEL);
600 if (!phydev->priv)
601 return -ENOMEM;
602
603 return aqr_hwmon_probe(phydev);
604 }
605
606 static struct phy_driver aqr_driver[] = {
607 {
608 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
609 .name = "Aquantia AQ1202",
610 .config_aneg = aqr_config_aneg,
611 .config_intr = aqr_config_intr,
612 .ack_interrupt = aqr_ack_interrupt,
613 .read_status = aqr_read_status,
614 },
615 {
616 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
617 .name = "Aquantia AQ2104",
618 .config_aneg = aqr_config_aneg,
619 .config_intr = aqr_config_intr,
620 .ack_interrupt = aqr_ack_interrupt,
621 .read_status = aqr_read_status,
622 },
623 {
624 PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
625 .name = "Aquantia AQR105",
626 .config_aneg = aqr_config_aneg,
627 .config_intr = aqr_config_intr,
628 .ack_interrupt = aqr_ack_interrupt,
629 .read_status = aqr_read_status,
630 },
631 {
632 PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
633 .name = "Aquantia AQR106",
634 .config_aneg = aqr_config_aneg,
635 .config_intr = aqr_config_intr,
636 .ack_interrupt = aqr_ack_interrupt,
637 .read_status = aqr_read_status,
638 },
639 {
640 PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
641 .name = "Aquantia AQR107",
642 .probe = aqr107_probe,
643 .config_init = aqr107_config_init,
644 .config_aneg = aqr_config_aneg,
645 .config_intr = aqr_config_intr,
646 .ack_interrupt = aqr_ack_interrupt,
647 .read_status = aqr107_read_status,
648 .get_tunable = aqr107_get_tunable,
649 .set_tunable = aqr107_set_tunable,
650 .suspend = aqr107_suspend,
651 .resume = aqr107_resume,
652 .get_sset_count = aqr107_get_sset_count,
653 .get_strings = aqr107_get_strings,
654 .get_stats = aqr107_get_stats,
655 .link_change_notify = aqr107_link_change_notify,
656 },
657 {
658 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
659 .name = "Aquantia AQCS109",
660 .probe = aqr107_probe,
661 .config_init = aqcs109_config_init,
662 .config_aneg = aqr_config_aneg,
663 .config_intr = aqr_config_intr,
664 .ack_interrupt = aqr_ack_interrupt,
665 .read_status = aqr107_read_status,
666 .get_tunable = aqr107_get_tunable,
667 .set_tunable = aqr107_set_tunable,
668 .suspend = aqr107_suspend,
669 .resume = aqr107_resume,
670 .get_sset_count = aqr107_get_sset_count,
671 .get_strings = aqr107_get_strings,
672 .get_stats = aqr107_get_stats,
673 .link_change_notify = aqr107_link_change_notify,
674 },
675 {
676 PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
677 .name = "Aquantia AQR405",
678 .config_aneg = aqr_config_aneg,
679 .config_intr = aqr_config_intr,
680 .ack_interrupt = aqr_ack_interrupt,
681 .read_status = aqr_read_status,
682 },
683 };
684
685 module_phy_driver(aqr_driver);
686
687 static struct mdio_device_id __maybe_unused aqr_tbl[] = {
688 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
689 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
690 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
691 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
692 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
693 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
694 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
695 { }
696 };
697
698 MODULE_DEVICE_TABLE(mdio, aqr_tbl);
699
700 MODULE_DESCRIPTION("Aquantia PHY driver");
701 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
702 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support