drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Texas Instruments DP83867 PHY
   4  *
   5  * Copyright (C) 2015 Texas Instruments Inc.
   6  */
   7
   8 #include <linux/ethtool.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/delay.h>
  15
  16 #include <dt-bindings/net/ti-dp83867.h>
  17
  18 #define DP83867_PHY_ID          0x2000a231
  19 #define DP83867_DEVADDR         0x1f
  20
  21 #define MII_DP83867_PHYCTRL     0x10
  22 #define MII_DP83867_MICR        0x12
  23 #define MII_DP83867_ISR         0x13
  24 #define DP83867_CTRL            0x1f
  25 #define DP83867_CFG3            0x1e
  26
  27 /* Extended Registers */
  28 #define DP83867_CFG4            0x0031
  29 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  30 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  31 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  32 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  33 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  34
  35 #define DP83867_RGMIICTL        0x0032
  36 #define DP83867_STRAP_STS1      0x006E
  37 #define DP83867_STRAP_STS2      0x006f
  38 #define DP83867_RGMIIDCTL       0x0086
  39 #define DP83867_IO_MUX_CFG      0x0170
  40 #define DP83867_10M_SGMII_CFG   0x016F
  41 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  42
  43 #define DP83867_SW_RESET        BIT(15)
  44 #define DP83867_SW_RESTART      BIT(14)
  45
  46 /* MICR Interrupt bits */
  47 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  48 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  49 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  50 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  51 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  52 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  53 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  54 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  55 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  56 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  57 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  58 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  59
  60 /* RGMIICTL bits */
  61 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  62 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  63
  64 /* STRAP_STS1 bits */
  65 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  66
  67 /* STRAP_STS2 bits */
  68 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  69 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  70 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  71 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  72 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  73
  74 /* PHY CTRL bits */
  75 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  76 #define DP83867_PHYCR_FIFO_DEPTH_MAX            0x03
  77 #define DP83867_PHYCR_FIFO_DEPTH_MASK           GENMASK(15, 14)
  78 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
  79
  80 /* RGMIIDCTL bits */
  81 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
  82 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  83 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
  84 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT        0
  85
  86 /* IO_MUX_CFG bits */
  87 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK    0x1f
  88 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  89 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  90 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
  91 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
  92 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  93
  94 /* CFG4 bits */
  95 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
  96
  97 enum {
  98         DP83867_PORT_MIRROING_KEEP,
  99         DP83867_PORT_MIRROING_EN,
 100         DP83867_PORT_MIRROING_DIS,
 101 };
 102
 103 struct dp83867_private {
 104         u32 rx_id_delay;
 105         u32 tx_id_delay;
 106         u32 fifo_depth;
 107         int io_impedance;
 108         int port_mirroring;
 109         bool rxctrl_strap_quirk;
 110         bool set_clk_output;
 111         u32 clk_output_sel;
 112 };
 113
 114 static int dp83867_ack_interrupt(struct phy_device *phydev)
 115 {
 116         int err = phy_read(phydev, MII_DP83867_ISR);
 117
 118         if (err < 0)
 119                 return err;
 120
 121         return 0;
 122 }
 123
 124 static int dp83867_config_intr(struct phy_device *phydev)
 125 {
 126         int micr_status;
 127
 128         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 129                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 130                 if (micr_status < 0)
 131                         return micr_status;
 132
 133                 micr_status |=
 134                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 135                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 136                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 137                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 138                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 139                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 140
 141                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 142         }
 143
 144         micr_status = 0x0;
 145         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 146 }
 147
 148 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 149 {
 150         struct dp83867_private *dp83867 =
 151                 (struct dp83867_private *)phydev->priv;
 152
 153         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 154                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 155                                  DP83867_CFG4_PORT_MIRROR_EN);
 156         else
 157                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 158                                    DP83867_CFG4_PORT_MIRROR_EN);
 159         return 0;
 160 }
 161
 162 #ifdef CONFIG_OF_MDIO
 163 static int dp83867_of_init(struct phy_device *phydev)
 164 {
 165         struct dp83867_private *dp83867 = phydev->priv;
 166         struct device *dev = &phydev->mdio.dev;
 167         struct device_node *of_node = dev->of_node;
 168         int ret;
 169
 170         if (!of_node)
 171                 return -ENODEV;
 172
 173         /* Optional configuration */
 174         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 175                                    &dp83867->clk_output_sel);
 176         /* If not set, keep default */
 177         if (!ret) {
 178                 dp83867->set_clk_output = true;
 179                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 180                  * DP83867_CLK_O_SEL_OFF.
 181                  */
 182                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 183                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 184                         phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
 185                                    dp83867->clk_output_sel);
 186                         return -EINVAL;
 187                 }
 188         }
 189
 190         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 191                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 192         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 193                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 194         else
 195                 dp83867->io_impedance = -1; /* leave at default */
 196
 197         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 198                                         "ti,dp83867-rxctrl-strap-quirk");
 199
 200         /* Existing behavior was to use default pin strapping delay in rgmii
 201          * mode, but rgmii should have meant no delay.  Warn existing users.
 202          */
 203         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 204                 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
 205                 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 206                                    DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 207                 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 208                                    DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 209
 210                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 211                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 212                         phydev_warn(phydev,
 213                                     "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 214                                     "Should be 'rgmii-id' to use internal delays\n");
 215         }
 216
 217         /* RX delay *must* be specified if internal delay of RX is used. */
 218         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 219             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 220                 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 221                                            &dp83867->rx_id_delay);
 222                 if (ret) {
 223                         phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
 224                         return ret;
 225                 }
 226                 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 227                         phydev_err(phydev,
 228                                    "ti,rx-internal-delay value of %u out of range\n",
 229                                    dp83867->rx_id_delay);
 230                         return -EINVAL;
 231                 }
 232         }
 233
 234         /* TX delay *must* be specified if internal delay of RX is used. */
 235         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 236             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 237                 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 238                                            &dp83867->tx_id_delay);
 239                 if (ret) {
 240                         phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
 241                         return ret;
 242                 }
 243                 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 244                         phydev_err(phydev,
 245                                    "ti,tx-internal-delay value of %u out of range\n",
 246                                    dp83867->tx_id_delay);
 247                         return -EINVAL;
 248                 }
 249         }
 250
 251         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 252                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 253
 254         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 255                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 256
 257         ret = of_property_read_u32(of_node, "ti,fifo-depth",
 258                                    &dp83867->fifo_depth);
 259         if (ret) {
 260                 phydev_err(phydev,
 261                            "ti,fifo-depth property is required\n");
 262                 return ret;
 263         }
 264         if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 265                 phydev_err(phydev,
 266                            "ti,fifo-depth value %u out of range\n",
 267                            dp83867->fifo_depth);
 268                 return -EINVAL;
 269         }
 270         return 0;
 271 }
 272 #else
 273 static int dp83867_of_init(struct phy_device *phydev)
 274 {
 275         return 0;
 276 }
 277 #endif /* CONFIG_OF_MDIO */
 278
 279 static int dp83867_probe(struct phy_device *phydev)
 280 {
 281         struct dp83867_private *dp83867;
 282
 283         dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 284                                GFP_KERNEL);
 285         if (!dp83867)
 286                 return -ENOMEM;
 287
 288         phydev->priv = dp83867;
 289
 290         return 0;
 291 }
 292
 293 static int dp83867_config_init(struct phy_device *phydev)
 294 {
 295         struct dp83867_private *dp83867 = phydev->priv;
 296         int ret, val, bs;
 297         u16 delay;
 298
 299         ret = dp83867_of_init(phydev);
 300         if (ret)
 301                 return ret;
 302
 303         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 304         if (dp83867->rxctrl_strap_quirk)
 305                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 306                                    BIT(7));
 307
 308         if (phy_interface_is_rgmii(phydev)) {
 309                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 310                 if (val < 0)
 311                         return val;
 312                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 313                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 314
 315                 /* The code below checks if "port mirroring" N/A MODE4 has been
 316                  * enabled during power on bootstrap.
 317                  *
 318                  * Such N/A mode enabled by mistake can put PHY IC in some
 319                  * internal testing mode and disable RGMII transmission.
 320                  *
 321                  * In this particular case one needs to check STRAP_STS1
 322                  * register's bit 11 (marked as RESERVED).
 323                  */
 324
 325                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 326                 if (bs & DP83867_STRAP_STS1_RESERVED)
 327                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 328
 329                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 330                 if (ret)
 331                         return ret;
 332
 333                 /* If rgmii mode with no internal delay is selected, we do NOT use
 334                  * aligned mode as one might expect.  Instead we use the PHY's default
 335                  * based on pin strapping.  And the "mode 0" default is to *use*
 336                  * internal delay with a value of 7 (2.00 ns).
 337                  *
 338                  * Set up RGMII delays
 339                  */
 340                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 341
 342                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 343                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 344                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 345
 346                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 347                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 348
 349                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 350                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 351
 352                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 353
 354                 delay = (dp83867->rx_id_delay |
 355                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 356
 357                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 358                               delay);
 359         }
 360
 361         /* If specified, set io impedance */
 362         if (dp83867->io_impedance >= 0)
 363                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 364                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
 365                                dp83867->io_impedance);
 366
 367         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 368                 /* For support SPEED_10 in SGMII mode
 369                  * DP83867_10M_SGMII_RATE_ADAPT bit
 370                  * has to be cleared by software. That
 371                  * does not affect SPEED_100 and
 372                  * SPEED_1000.
 373                  */
 374                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 375                                      DP83867_10M_SGMII_CFG,
 376                                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
 377                                      0);
 378                 if (ret)
 379                         return ret;
 380
 381                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 382                  * are 01). That is not enough to finalize autoneg on some
 383                  * devices. Increase this timer duration to maximum 16ms.
 384                  */
 385                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 386                                      DP83867_CFG4,
 387                                      DP83867_CFG4_SGMII_ANEG_MASK,
 388                                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
 389
 390                 if (ret)
 391                         return ret;
 392         }
 393
 394         /* Enable Interrupt output INT_OE in CFG3 register */
 395         if (phy_interrupt_is_valid(phydev)) {
 396                 val = phy_read(phydev, DP83867_CFG3);
 397                 val |= BIT(7);
 398                 phy_write(phydev, DP83867_CFG3, val);
 399         }
 400
 401         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 402                 dp83867_config_port_mirroring(phydev);
 403
 404         /* Clock output selection if muxing property is set */
 405         if (dp83867->set_clk_output) {
 406                 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 407
 408                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 409                         val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 410                 } else {
 411                         mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 412                         val = dp83867->clk_output_sel <<
 413                               DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 414                 }
 415
 416                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 417                                mask, val);
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int dp83867_phy_reset(struct phy_device *phydev)
 424 {
 425         int err;
 426
 427         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 428         if (err < 0)
 429                 return err;
 430
 431         usleep_range(10, 20);
 432
 433         return 0;
 434 }
 435
 436 static struct phy_driver dp83867_driver[] = {
 437         {
 438                 .phy_id         = DP83867_PHY_ID,
 439                 .phy_id_mask    = 0xfffffff0,
 440                 .name           = "TI DP83867",
 441                 /* PHY_GBIT_FEATURES */
 442
 443                 .probe          = dp83867_probe,
 444                 .config_init    = dp83867_config_init,
 445                 .soft_reset     = dp83867_phy_reset,
 446
 447                 /* IRQ related */
 448                 .ack_interrupt  = dp83867_ack_interrupt,
 449                 .config_intr    = dp83867_config_intr,
 450
 451                 .suspend        = genphy_suspend,
 452                 .resume         = genphy_resume,
 453         },
 454 };
 455 module_phy_driver(dp83867_driver);
 456
 457 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 458         { DP83867_PHY_ID, 0xfffffff0 },
 459         { }
 460 };
 461
 462 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 463
 464 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 465 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 466 MODULE_LICENSE("GPL v2");