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lkdtm: Add Control Flow Integrity test
[linux/fpc-iii.git] / drivers / scsi / mpt3sas / mpi / mpi2.h
blob7efd17a3c25b065d05ba4b0ab837cac79842745b
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 *
5 *
6 * Name: mpi2.h
7 * Title: MPI Message independent structures and definitions
8 * including System Interface Register Set and
9 * scatter/gather formats.
10 * Creation Date: June 21, 2006
11 *
12 * mpi2.h Version: 02.00.53
13 *
14 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
15 * prefix are for use only on MPI v2.5 products, and must not be used
16 * with MPI v2.0 products. Unless otherwise noted, names beginning with
17 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
18 *
19 * Version History
20 * ---------------
21 *
22 * Date Version Description
23 * -------- -------- ------------------------------------------------------
24 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
25 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
27 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Moved ReplyPostHostIndex register to offset 0x6C of the
29 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
30 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
31 * Added union of request descriptors.
32 * Added union of reply descriptors.
33 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
34 * Added define for MPI2_VERSION_02_00.
35 * Fixed the size of the FunctionDependent5 field in the
36 * MPI2_DEFAULT_REPLY structure.
37 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
38 * Removed the MPI-defined Fault Codes and extended the
39 * product specific codes up to 0xEFFF.
40 * Added a sixth key value for the WriteSequence register
41 * and changed the flush value to 0x0.
42 * Added message function codes for Diagnostic Buffer Post
43 * and Diagnsotic Release.
44 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
45 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
46 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
48 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
49 * Added #defines for marking a reply descriptor as unused.
50 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
51 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
52 * Moved LUN field defines from mpi2_init.h.
53 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
54 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
55 * In all request and reply descriptors, replaced VF_ID
56 * field with MSIxIndex field.
57 * Removed DevHandle field from
58 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
59 * bytes reserved.
60 * Added RAID Accelerator functionality.
61 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
62 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
63 * Added MSI-x index mask and shift for Reply Post Host
64 * Index register.
65 * Added function code for Host Based Discovery Action.
66 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
67 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
68 * Added defines for product-specific range of message
69 * function codes, 0xF0 to 0xFF.
70 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
71 * Added alternative defines for the SGE Direction bit.
72 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
73 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
74 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
75 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
76 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
77 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
80 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
81 * Incorporating additions for MPI v2.5.
82 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
83 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
84 * Added Hard Reset delay timings.
85 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
88 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
89 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
90 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
91 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
92 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
93 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
94 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT
95 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
96 * 11-18-14 02.00.36 Updated copyright information.
97 * Bumped MPI2_HEADER_VERSION_UNIT.
98 * 03-16-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT.
99 * Added Scratchpad registers to
100 * MPI2_SYSTEM_INTERFACE_REGS.
101 * Added MPI2_DIAG_SBR_RELOAD.
102 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
103 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT.
104 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
105 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
106 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
107 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines
108 * to be unique within first 32 characters.
109 * Removed AHCI support.
110 * Removed SOP support.
111 * Bumped MPI2_HEADER_VERSION_UNIT.
112 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT.
113 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT.
114 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT.
115 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT.
116 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT.
117 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT.
118 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT.
119 * 07-22-18 02.00.51 Added SECURE_BOOT define.
120 * Bumped MPI2_HEADER_VERSION_UNIT
121 * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT.
122 * 08-28-18 02.00.53 Bumped MPI2_HEADER_VERSION_UNIT.
123 * Added MPI2_IOCSTATUS_FAILURE
124 * --------------------------------------------------------------------------
125 */
126
127 #ifndef MPI2_H
128 #define MPI2_H
129
130 /*****************************************************************************
131 *
132 * MPI Version Definitions
133 *
134 *****************************************************************************/
135
136 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
137 #define MPI2_VERSION_MAJOR_SHIFT (8)
138 #define MPI2_VERSION_MINOR_MASK (0x00FF)
139 #define MPI2_VERSION_MINOR_SHIFT (0)
140
141 /*major version for all MPI v2.x */
142 #define MPI2_VERSION_MAJOR (0x02)
143
144 /*minor version for MPI v2.0 compatible products */
145 #define MPI2_VERSION_MINOR (0x00)
146 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
147 MPI2_VERSION_MINOR)
148 #define MPI2_VERSION_02_00 (0x0200)
149
150 /*minor version for MPI v2.5 compatible products */
151 #define MPI25_VERSION_MINOR (0x05)
152 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
153 MPI25_VERSION_MINOR)
154 #define MPI2_VERSION_02_05 (0x0205)
155
156 /*minor version for MPI v2.6 compatible products */
157 #define MPI26_VERSION_MINOR (0x06)
158 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
159 MPI26_VERSION_MINOR)
160 #define MPI2_VERSION_02_06 (0x0206)
161
162
163 /* Unit and Dev versioning for this MPI header set */
164 #define MPI2_HEADER_VERSION_UNIT (0x35)
165 #define MPI2_HEADER_VERSION_DEV (0x00)
166 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
167 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
168 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
169 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
170 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
171 MPI2_HEADER_VERSION_DEV)
172
173 /*****************************************************************************
174 *
175 * IOC State Definitions
176 *
177 *****************************************************************************/
178
179 #define MPI2_IOC_STATE_RESET (0x00000000)
180 #define MPI2_IOC_STATE_READY (0x10000000)
181 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
182 #define MPI2_IOC_STATE_FAULT (0x40000000)
183
184 #define MPI2_IOC_STATE_MASK (0xF0000000)
185 #define MPI2_IOC_STATE_SHIFT (28)
186
187 /*Fault state range for prodcut specific codes */
188 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
189 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
190
191 /*****************************************************************************
192 *
193 * System Interface Register Definitions
194 *
195 *****************************************************************************/
196
197 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
198 U32 Doorbell; /*0x00 */
199 U32 WriteSequence; /*0x04 */
200 U32 HostDiagnostic; /*0x08 */
201 U32 Reserved1; /*0x0C */
202 U32 DiagRWData; /*0x10 */
203 U32 DiagRWAddressLow; /*0x14 */
204 U32 DiagRWAddressHigh; /*0x18 */
205 U32 Reserved2[5]; /*0x1C */
206 U32 HostInterruptStatus; /*0x30 */
207 U32 HostInterruptMask; /*0x34 */
208 U32 DCRData; /*0x38 */
209 U32 DCRAddress; /*0x3C */
210 U32 Reserved3[2]; /*0x40 */
211 U32 ReplyFreeHostIndex; /*0x48 */
212 U32 Reserved4[8]; /*0x4C */
213 U32 ReplyPostHostIndex; /*0x6C */
214 U32 Reserved5; /*0x70 */
215 U32 HCBSize; /*0x74 */
216 U32 HCBAddressLow; /*0x78 */
217 U32 HCBAddressHigh; /*0x7C */
218 U32 Reserved6[12]; /*0x80 */
219 U32 Scratchpad[4]; /*0xB0 */
220 U32 RequestDescriptorPostLow; /*0xC0 */
221 U32 RequestDescriptorPostHigh; /*0xC4 */
222 U32 AtomicRequestDescriptorPost;/*0xC8 */
223 U32 Reserved7[13]; /*0xCC */
224 } MPI2_SYSTEM_INTERFACE_REGS,
225 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
226 Mpi2SystemInterfaceRegs_t,
227 *pMpi2SystemInterfaceRegs_t;
228
229 /*
230 *Defines for working with the Doorbell register.
231 */
232 #define MPI2_DOORBELL_OFFSET (0x00000000)
233
234 /*IOC --> System values */
235 #define MPI2_DOORBELL_USED (0x08000000)
236 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
237 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
238 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
239 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
240
241 /*System --> IOC values */
242 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
243 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
244 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
245 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
246
247 /*
248 *Defines for the WriteSequence register
249 */
250 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
251 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
252 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
253 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
254 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
255 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
256 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
257 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
258 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
259
260 /*
261 *Defines for the HostDiagnostic register
262 */
263 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
264
265 #define MPI26_DIAG_SECURE_BOOT (0x80000000)
266
267 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
268
269 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
270 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
271 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
272
273 /* Defines for V7A/V7R HostDiagnostic Register */
274 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
275 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
276 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
277 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
278
279 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
280 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
281 #define MPI2_DIAG_HCB_MODE (0x00000100)
282 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
283 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
284 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
285 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
286 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
287 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
288
289 /*
290 *Offsets for DiagRWData and address
291 */
292 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
293 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
294 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
295
296 /*
297 *Defines for the HostInterruptStatus register
298 */
299 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
300 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
301 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
302 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
303 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
304 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
305 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
306
307 /*
308 *Defines for the HostInterruptMask register
309 */
310 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
311 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
312 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
313 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
314 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
315 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
316
317 /*
318 *Offsets for DCRData and address
319 */
320 #define MPI2_DCR_DATA_OFFSET (0x00000038)
321 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
322
323 /*
324 *Offset for the Reply Free Queue
325 */
326 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
327
328 /*
329 *Defines for the Reply Descriptor Post Queue
330 */
331 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
332 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
333 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
334 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
335 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
336
337
338 /*
339 *Defines for the HCBSize and address
340 */
341 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
342 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
343 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
344
345 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
346 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
347
348 /*
349 *Offsets for the Scratchpad registers
350 */
351 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
352 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
353 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
354 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
355
356 /*
357 *Offsets for the Request Descriptor Post Queue
358 */
359 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
360 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
361 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
362
363 /*Hard Reset delay timings */
364 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
365 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
366 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
367
368 /*****************************************************************************
369 *
370 * Message Descriptors
371 *
372 *****************************************************************************/
373
374 /*Request Descriptors */
375
376 /*Default Request Descriptor */
377 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
378 U8 RequestFlags; /*0x00 */
379 U8 MSIxIndex; /*0x01 */
380 U16 SMID; /*0x02 */
381 U16 LMID; /*0x04 */
382 U16 DescriptorTypeDependent; /*0x06 */
383 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
384 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
385 Mpi2DefaultRequestDescriptor_t,
386 *pMpi2DefaultRequestDescriptor_t;
387
388 /*defines for the RequestFlags field */
389 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
390 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1)
391 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
392 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
393 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
394 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
395 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
396 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
397 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
398
399 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
400
401 /*High Priority Request Descriptor */
402 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
403 U8 RequestFlags; /*0x00 */
404 U8 MSIxIndex; /*0x01 */
405 U16 SMID; /*0x02 */
406 U16 LMID; /*0x04 */
407 U16 Reserved1; /*0x06 */
408 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
409 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
410 Mpi2HighPriorityRequestDescriptor_t,
411 *pMpi2HighPriorityRequestDescriptor_t;
412
413 /*SCSI IO Request Descriptor */
414 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
415 U8 RequestFlags; /*0x00 */
416 U8 MSIxIndex; /*0x01 */
417 U16 SMID; /*0x02 */
418 U16 LMID; /*0x04 */
419 U16 DevHandle; /*0x06 */
420 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
421 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
422 Mpi2SCSIIORequestDescriptor_t,
423 *pMpi2SCSIIORequestDescriptor_t;
424
425 /*SCSI Target Request Descriptor */
426 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
427 U8 RequestFlags; /*0x00 */
428 U8 MSIxIndex; /*0x01 */
429 U16 SMID; /*0x02 */
430 U16 LMID; /*0x04 */
431 U16 IoIndex; /*0x06 */
432 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
433 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
434 Mpi2SCSITargetRequestDescriptor_t,
435 *pMpi2SCSITargetRequestDescriptor_t;
436
437 /*RAID Accelerator Request Descriptor */
438 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
439 U8 RequestFlags; /*0x00 */
440 U8 MSIxIndex; /*0x01 */
441 U16 SMID; /*0x02 */
442 U16 LMID; /*0x04 */
443 U16 Reserved; /*0x06 */
444 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
445 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
446 Mpi2RAIDAcceleratorRequestDescriptor_t,
447 *pMpi2RAIDAcceleratorRequestDescriptor_t;
448
449 /*Fast Path SCSI IO Request Descriptor */
450 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
451 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
452 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
453 Mpi25FastPathSCSIIORequestDescriptor_t,
454 *pMpi25FastPathSCSIIORequestDescriptor_t;
455
456 /*PCIe Encapsulated Request Descriptor */
457 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
458 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
459 *PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
460 Mpi26PCIeEncapsulatedRequestDescriptor_t,
461 *pMpi26PCIeEncapsulatedRequestDescriptor_t;
462
463 /*union of Request Descriptors */
464 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
465 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
466 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
467 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
468 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
469 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
470 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
471 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated;
472 U64 Words;
473 } MPI2_REQUEST_DESCRIPTOR_UNION,
474 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
475 Mpi2RequestDescriptorUnion_t,
476 *pMpi2RequestDescriptorUnion_t;
477
478 /*Atomic Request Descriptors */
479
480 /*
481 * All Atomic Request Descriptors have the same format, so the following
482 * structure is used for all Atomic Request Descriptors:
483 * Atomic Default Request Descriptor
484 * Atomic High Priority Request Descriptor
485 * Atomic SCSI IO Request Descriptor
486 * Atomic SCSI Target Request Descriptor
487 * Atomic RAID Accelerator Request Descriptor
488 * Atomic Fast Path SCSI IO Request Descriptor
489 * Atomic PCIe Encapsulated Request Descriptor
490 */
491
492 /*Atomic Request Descriptor */
493 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR {
494 U8 RequestFlags; /* 0x00 */
495 U8 MSIxIndex; /* 0x01 */
496 U16 SMID; /* 0x02 */
497 } MPI26_ATOMIC_REQUEST_DESCRIPTOR,
498 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
499 Mpi26AtomicRequestDescriptor_t,
500 *pMpi26AtomicRequestDescriptor_t;
501
502 /*for the RequestFlags field, use the same
503 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR
504 */
505
506 /*Reply Descriptors */
507
508 /*Default Reply Descriptor */
509 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
510 U8 ReplyFlags; /*0x00 */
511 U8 MSIxIndex; /*0x01 */
512 U16 DescriptorTypeDependent1; /*0x02 */
513 U32 DescriptorTypeDependent2; /*0x04 */
514 } MPI2_DEFAULT_REPLY_DESCRIPTOR,
515 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
516 Mpi2DefaultReplyDescriptor_t,
517 *pMpi2DefaultReplyDescriptor_t;
518
519 /*defines for the ReplyFlags field */
520 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
521 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
522 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
523 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
524 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
525 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
526 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
527 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
528 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
529
530 /*values for marking a reply descriptor as unused */
531 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
532 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
533
534 /*Address Reply Descriptor */
535 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
536 U8 ReplyFlags; /*0x00 */
537 U8 MSIxIndex; /*0x01 */
538 U16 SMID; /*0x02 */
539 U32 ReplyFrameAddress; /*0x04 */
540 } MPI2_ADDRESS_REPLY_DESCRIPTOR,
541 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
542 Mpi2AddressReplyDescriptor_t,
543 *pMpi2AddressReplyDescriptor_t;
544
545 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
546
547 /*SCSI IO Success Reply Descriptor */
548 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
549 U8 ReplyFlags; /*0x00 */
550 U8 MSIxIndex; /*0x01 */
551 U16 SMID; /*0x02 */
552 U16 TaskTag; /*0x04 */
553 U16 Reserved1; /*0x06 */
554 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
555 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
556 Mpi2SCSIIOSuccessReplyDescriptor_t,
557 *pMpi2SCSIIOSuccessReplyDescriptor_t;
558
559 /*TargetAssist Success Reply Descriptor */
560 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
561 U8 ReplyFlags; /*0x00 */
562 U8 MSIxIndex; /*0x01 */
563 U16 SMID; /*0x02 */
564 U8 SequenceNumber; /*0x04 */
565 U8 Reserved1; /*0x05 */
566 U16 IoIndex; /*0x06 */
567 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
568 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
569 Mpi2TargetAssistSuccessReplyDescriptor_t,
570 *pMpi2TargetAssistSuccessReplyDescriptor_t;
571
572 /*Target Command Buffer Reply Descriptor */
573 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
574 U8 ReplyFlags; /*0x00 */
575 U8 MSIxIndex; /*0x01 */
576 U8 VP_ID; /*0x02 */
577 U8 Flags; /*0x03 */
578 U16 InitiatorDevHandle; /*0x04 */
579 U16 IoIndex; /*0x06 */
580 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
581 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
582 Mpi2TargetCommandBufferReplyDescriptor_t,
583 *pMpi2TargetCommandBufferReplyDescriptor_t;
584
585 /*defines for Flags field */
586 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
587
588 /*RAID Accelerator Success Reply Descriptor */
589 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
590 U8 ReplyFlags; /*0x00 */
591 U8 MSIxIndex; /*0x01 */
592 U16 SMID; /*0x02 */
593 U32 Reserved; /*0x04 */
594 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
595 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
596 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
597 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
598
599 /*Fast Path SCSI IO Success Reply Descriptor */
600 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
601 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
602 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
603 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
604 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
605
606 /*PCIe Encapsulated Success Reply Descriptor */
607 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
608 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
609 *PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
610 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t,
611 *pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t;
612
613 /*union of Reply Descriptors */
614 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
615 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
616 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
617 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
618 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
619 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
620 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
621 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
622 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR
623 PCIeEncapsulatedSuccess;
624 U64 Words;
625 } MPI2_REPLY_DESCRIPTORS_UNION,
626 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
627 Mpi2ReplyDescriptorsUnion_t,
628 *pMpi2ReplyDescriptorsUnion_t;
629
630 /*****************************************************************************
631 *
632 * Message Functions
633 *
634 *****************************************************************************/
635
636 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
637 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
638 #define MPI2_FUNCTION_IOC_INIT (0x02)
639 #define MPI2_FUNCTION_IOC_FACTS (0x03)
640 #define MPI2_FUNCTION_CONFIG (0x04)
641 #define MPI2_FUNCTION_PORT_FACTS (0x05)
642 #define MPI2_FUNCTION_PORT_ENABLE (0x06)
643 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
644 #define MPI2_FUNCTION_EVENT_ACK (0x08)
645 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
646 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
647 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
648 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
649 #define MPI2_FUNCTION_FW_UPLOAD (0x12)
650 #define MPI2_FUNCTION_RAID_ACTION (0x15)
651 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
652 #define MPI2_FUNCTION_TOOLBOX (0x17)
653 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
654 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
655 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
656 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B)
657 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
658 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
659 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
660 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
661 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
662 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
663 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
664 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
665 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
666 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33)
667 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
668 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
669
670 /*Doorbell functions */
671 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
672 #define MPI2_FUNCTION_HANDSHAKE (0x42)
673
674 /*****************************************************************************
675 *
676 * IOC Status Values
677 *
678 *****************************************************************************/
679
680 /*mask for IOCStatus status value */
681 #define MPI2_IOCSTATUS_MASK (0x7FFF)
682
683 /****************************************************************************
684 * Common IOCStatus values for all replies
685 ****************************************************************************/
686
687 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
688 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
689 #define MPI2_IOCSTATUS_BUSY (0x0002)
690 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
691 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
692 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
693 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
694 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
695 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
696 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
697 /*MPI v2.6 and later */
698 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
699 #define MPI2_IOCSTATUS_FAILURE (0x000F)
700
701 /****************************************************************************
702 * Config IOCStatus values
703 ****************************************************************************/
704
705 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
706 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
707 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
708 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
709 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
710 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
711
712 /****************************************************************************
713 * SCSI IO Reply
714 ****************************************************************************/
715
716 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
717 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
718 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
719 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
720 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
721 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
722 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
723 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
724 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
725 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
726 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
727 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
728
729 /****************************************************************************
730 * For use by SCSI Initiator and SCSI Target end-to-end data protection
731 ****************************************************************************/
732
733 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
734 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
735 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
736
737 /****************************************************************************
738 * SCSI Target values
739 ****************************************************************************/
740
741 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
742 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
743 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
744 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
745 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
746 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
747 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
748 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
749 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
750 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
751
752 /****************************************************************************
753 * Serial Attached SCSI values
754 ****************************************************************************/
755
756 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
757 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
758
759 /****************************************************************************
760 * Diagnostic Buffer Post / Diagnostic Release values
761 ****************************************************************************/
762
763 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
764
765 /****************************************************************************
766 * RAID Accelerator values
767 ****************************************************************************/
768
769 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
770
771 /****************************************************************************
772 * IOCStatus flag to indicate that log info is available
773 ****************************************************************************/
774
775 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
776
777 /****************************************************************************
778 * IOCLogInfo Types
779 ****************************************************************************/
780
781 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
782 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
783 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
784 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
785 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
786 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
787 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
788 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
789
790 /*****************************************************************************
791 *
792 * Standard Message Structures
793 *
794 *****************************************************************************/
795
796 /****************************************************************************
797 *Request Message Header for all request messages
798 ****************************************************************************/
799
800 typedef struct _MPI2_REQUEST_HEADER {
801 U16 FunctionDependent1; /*0x00 */
802 U8 ChainOffset; /*0x02 */
803 U8 Function; /*0x03 */
804 U16 FunctionDependent2; /*0x04 */
805 U8 FunctionDependent3; /*0x06 */
806 U8 MsgFlags; /*0x07 */
807 U8 VP_ID; /*0x08 */
808 U8 VF_ID; /*0x09 */
809 U16 Reserved1; /*0x0A */
810 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
811 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
812
813 /****************************************************************************
814 * Default Reply
815 ****************************************************************************/
816
817 typedef struct _MPI2_DEFAULT_REPLY {
818 U16 FunctionDependent1; /*0x00 */
819 U8 MsgLength; /*0x02 */
820 U8 Function; /*0x03 */
821 U16 FunctionDependent2; /*0x04 */
822 U8 FunctionDependent3; /*0x06 */
823 U8 MsgFlags; /*0x07 */
824 U8 VP_ID; /*0x08 */
825 U8 VF_ID; /*0x09 */
826 U16 Reserved1; /*0x0A */
827 U16 FunctionDependent5; /*0x0C */
828 U16 IOCStatus; /*0x0E */
829 U32 IOCLogInfo; /*0x10 */
830 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
831 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
832
833 /*common version structure/union used in messages and configuration pages */
834
835 typedef struct _MPI2_VERSION_STRUCT {
836 U8 Dev; /*0x00 */
837 U8 Unit; /*0x01 */
838 U8 Minor; /*0x02 */
839 U8 Major; /*0x03 */
840 } MPI2_VERSION_STRUCT;
841
842 typedef union _MPI2_VERSION_UNION {
843 MPI2_VERSION_STRUCT Struct;
844 U32 Word;
845 } MPI2_VERSION_UNION;
846
847 /*LUN field defines, common to many structures */
848 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
849 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
850 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
851 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
852 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
853 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
854
855 /*****************************************************************************
856 *
857 * Fusion-MPT MPI Scatter Gather Elements
858 *
859 *****************************************************************************/
860
861 /****************************************************************************
862 * MPI Simple Element structures
863 ****************************************************************************/
864
865 typedef struct _MPI2_SGE_SIMPLE32 {
866 U32 FlagsLength;
867 U32 Address;
868 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
869 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
870
871 typedef struct _MPI2_SGE_SIMPLE64 {
872 U32 FlagsLength;
873 U64 Address;
874 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
875 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
876
877 typedef struct _MPI2_SGE_SIMPLE_UNION {
878 U32 FlagsLength;
879 union {
880 U32 Address32;
881 U64 Address64;
882 } u;
883 } MPI2_SGE_SIMPLE_UNION,
884 *PTR_MPI2_SGE_SIMPLE_UNION,
885 Mpi2SGESimpleUnion_t,
886 *pMpi2SGESimpleUnion_t;
887
888 /****************************************************************************
889 * MPI Chain Element structures - for MPI v2.0 products only
890 ****************************************************************************/
891
892 typedef struct _MPI2_SGE_CHAIN32 {
893 U16 Length;
894 U8 NextChainOffset;
895 U8 Flags;
896 U32 Address;
897 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
898 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
899
900 typedef struct _MPI2_SGE_CHAIN64 {
901 U16 Length;
902 U8 NextChainOffset;
903 U8 Flags;
904 U64 Address;
905 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
906 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
907
908 typedef struct _MPI2_SGE_CHAIN_UNION {
909 U16 Length;
910 U8 NextChainOffset;
911 U8 Flags;
912 union {
913 U32 Address32;
914 U64 Address64;
915 } u;
916 } MPI2_SGE_CHAIN_UNION,
917 *PTR_MPI2_SGE_CHAIN_UNION,
918 Mpi2SGEChainUnion_t,
919 *pMpi2SGEChainUnion_t;
920
921 /****************************************************************************
922 * MPI Transaction Context Element structures - for MPI v2.0 products only
923 ****************************************************************************/
924
925 typedef struct _MPI2_SGE_TRANSACTION32 {
926 U8 Reserved;
927 U8 ContextSize;
928 U8 DetailsLength;
929 U8 Flags;
930 U32 TransactionContext[1];
931 U32 TransactionDetails[1];
932 } MPI2_SGE_TRANSACTION32,
933 *PTR_MPI2_SGE_TRANSACTION32,
934 Mpi2SGETransaction32_t,
935 *pMpi2SGETransaction32_t;
936
937 typedef struct _MPI2_SGE_TRANSACTION64 {
938 U8 Reserved;
939 U8 ContextSize;
940 U8 DetailsLength;
941 U8 Flags;
942 U32 TransactionContext[2];
943 U32 TransactionDetails[1];
944 } MPI2_SGE_TRANSACTION64,
945 *PTR_MPI2_SGE_TRANSACTION64,
946 Mpi2SGETransaction64_t,
947 *pMpi2SGETransaction64_t;
948
949 typedef struct _MPI2_SGE_TRANSACTION96 {
950 U8 Reserved;
951 U8 ContextSize;
952 U8 DetailsLength;
953 U8 Flags;
954 U32 TransactionContext[3];
955 U32 TransactionDetails[1];
956 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
957 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
958
959 typedef struct _MPI2_SGE_TRANSACTION128 {
960 U8 Reserved;
961 U8 ContextSize;
962 U8 DetailsLength;
963 U8 Flags;
964 U32 TransactionContext[4];
965 U32 TransactionDetails[1];
966 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
967 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
968
969 typedef struct _MPI2_SGE_TRANSACTION_UNION {
970 U8 Reserved;
971 U8 ContextSize;
972 U8 DetailsLength;
973 U8 Flags;
974 union {
975 U32 TransactionContext32[1];
976 U32 TransactionContext64[2];
977 U32 TransactionContext96[3];
978 U32 TransactionContext128[4];
979 } u;
980 U32 TransactionDetails[1];
981 } MPI2_SGE_TRANSACTION_UNION,
982 *PTR_MPI2_SGE_TRANSACTION_UNION,
983 Mpi2SGETransactionUnion_t,
984 *pMpi2SGETransactionUnion_t;
985
986 /****************************************************************************
987 * MPI SGE union for IO SGL's - for MPI v2.0 products only
988 ****************************************************************************/
989
990 typedef struct _MPI2_MPI_SGE_IO_UNION {
991 union {
992 MPI2_SGE_SIMPLE_UNION Simple;
993 MPI2_SGE_CHAIN_UNION Chain;
994 } u;
995 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
996 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
997
998 /****************************************************************************
999 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1000 ****************************************************************************/
1001
1002 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
1003 union {
1004 MPI2_SGE_SIMPLE_UNION Simple;
1005 MPI2_SGE_TRANSACTION_UNION Transaction;
1006 } u;
1007 } MPI2_SGE_TRANS_SIMPLE_UNION,
1008 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
1009 Mpi2SGETransSimpleUnion_t,
1010 *pMpi2SGETransSimpleUnion_t;
1011
1012 /****************************************************************************
1013 * All MPI SGE types union
1014 ****************************************************************************/
1015
1016 typedef struct _MPI2_MPI_SGE_UNION {
1017 union {
1018 MPI2_SGE_SIMPLE_UNION Simple;
1019 MPI2_SGE_CHAIN_UNION Chain;
1020 MPI2_SGE_TRANSACTION_UNION Transaction;
1021 } u;
1022 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
1023 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
1024
1025 /****************************************************************************
1026 * MPI SGE field definition and masks
1027 ****************************************************************************/
1028
1029 /*Flags field bit definitions */
1030
1031 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
1032 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
1033 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1034 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1035 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
1036 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1037 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1038
1039 #define MPI2_SGE_FLAGS_SHIFT (24)
1040
1041 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1042 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1043
1044 /*Element Type */
1045
1046 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
1047 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1048 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
1049 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1050
1051 /*Address location */
1052
1053 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1054
1055 /*Direction */
1056
1057 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1058 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1059
1060 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1061 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1062
1063 /*Address Size */
1064
1065 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1066 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1067
1068 /*Context Size */
1069
1070 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1071 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1072 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1073 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1074
1075 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1076 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
1077
1078 /****************************************************************************
1079 * MPI SGE operation Macros
1080 ****************************************************************************/
1081
1082 /*SIMPLE FlagsLength manipulations... */
1083 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1084 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
1085 MPI2_SGE_FLAGS_SHIFT)
1086 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1087 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1088
1089 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
1090 MPI2_SGE_LENGTH(l))
1091
1092 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1093 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1094 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1095 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
1096
1097 /*CAUTION - The following are READ-MODIFY-WRITE! */
1098 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1099 MPI2_SGE_SET_FLAGS(f))
1100 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1101 MPI2_SGE_LENGTH(l))
1102
1103 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
1104 MPI2_SGE_CHAIN_OFFSET_SHIFT)
1105
1106 /*****************************************************************************
1107 *
1108 * Fusion-MPT IEEE Scatter Gather Elements
1109 *
1110 *****************************************************************************/
1111
1112 /****************************************************************************
1113 * IEEE Simple Element structures
1114 ****************************************************************************/
1115
1116 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1117 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1118 U32 Address;
1119 U32 FlagsLength;
1120 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1121 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1122
1123 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1124 U64 Address;
1125 U32 Length;
1126 U16 Reserved1;
1127 U8 Reserved2;
1128 U8 Flags;
1129 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1130 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1131
1132 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1133 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1134 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1135 } MPI2_IEEE_SGE_SIMPLE_UNION,
1136 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1137 Mpi2IeeeSgeSimpleUnion_t,
1138 *pMpi2IeeeSgeSimpleUnion_t;
1139
1140 /****************************************************************************
1141 * IEEE Chain Element structures
1142 ****************************************************************************/
1143
1144 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1145 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1146
1147 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1148 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1149
1150 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1151 MPI2_IEEE_SGE_CHAIN32 Chain32;
1152 MPI2_IEEE_SGE_CHAIN64 Chain64;
1153 } MPI2_IEEE_SGE_CHAIN_UNION,
1154 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1155 Mpi2IeeeSgeChainUnion_t,
1156 *pMpi2IeeeSgeChainUnion_t;
1157
1158 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1159 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1160 U64 Address;
1161 U32 Length;
1162 U16 Reserved1;
1163 U8 NextChainOffset;
1164 U8 Flags;
1165 } MPI25_IEEE_SGE_CHAIN64,
1166 *PTR_MPI25_IEEE_SGE_CHAIN64,
1167 Mpi25IeeeSgeChain64_t,
1168 *pMpi25IeeeSgeChain64_t;
1169
1170 /****************************************************************************
1171 * All IEEE SGE types union
1172 ****************************************************************************/
1173
1174 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1175 typedef struct _MPI2_IEEE_SGE_UNION {
1176 union {
1177 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1178 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1179 } u;
1180 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1181 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1182
1183 /****************************************************************************
1184 * IEEE SGE union for IO SGL's
1185 ****************************************************************************/
1186
1187 typedef union _MPI25_SGE_IO_UNION {
1188 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1189 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1190 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1191 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1192
1193 /****************************************************************************
1194 * IEEE SGE field definitions and masks
1195 ****************************************************************************/
1196
1197 /*Flags field bit definitions */
1198
1199 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1200 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1201
1202 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1203
1204 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1205
1206 /*Element Type */
1207
1208 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1209 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1210
1211 /*Next Segment Format */
1212
1213 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1214 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1215 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1216 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1217
1218 /*Data Location Address Space */
1219
1220 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1221 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1222 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1223 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1224 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1225 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1226 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1227 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1228 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02)
1229
1230 /****************************************************************************
1231 * IEEE SGE operation Macros
1232 ****************************************************************************/
1233
1234 /*SIMPLE FlagsLength manipulations... */
1235 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1236 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1237 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1238 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1239
1240 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1241 MPI2_IEEE32_SGE_LENGTH(l))
1242
1243 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1244 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1245 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1246 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1247 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1248 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1249
1250 /*CAUTION - The following are READ-MODIFY-WRITE! */
1251 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1252 MPI2_IEEE32_SGE_SET_FLAGS(f))
1253 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1254 MPI2_IEEE32_SGE_LENGTH(l))
1255
1256 /*****************************************************************************
1257 *
1258 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1259 *
1260 *****************************************************************************/
1261
1262 typedef union _MPI2_SIMPLE_SGE_UNION {
1263 MPI2_SGE_SIMPLE_UNION MpiSimple;
1264 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1265 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1266 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1267
1268 typedef union _MPI2_SGE_IO_UNION {
1269 MPI2_SGE_SIMPLE_UNION MpiSimple;
1270 MPI2_SGE_CHAIN_UNION MpiChain;
1271 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1272 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1273 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1274 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1275
1276 /****************************************************************************
1277 *
1278 * Values for SGLFlags field, used in many request messages with an SGL
1279 *
1280 ****************************************************************************/
1281
1282 /*values for MPI SGL Data Location Address Space subfield */
1283 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1284 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1285 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1286 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1287 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1288 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1289 /*values for SGL Type subfield */
1290 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1291 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1292 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1293 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1294
1295 #endif
Linux with added FPC-III support