arch/mips/kernel/irq_cpu.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * Copyright (C) 2001 Ralf Baechle
   6  * Copyright (C) 2005  MIPS Technologies, Inc.  All rights reserved.
   7  *      Author: Maciej W. Rozycki <macro@mips.com>
   8  *
   9  * This file define the irq handler for MIPS CPU interrupts.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 /*
  18  * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
  19  * level triggered (i.e., cannot be cleared from CPU; must be cleared from
  20  * device).  The first two are software interrupts which we don't really
  21  * use or support.  The last one is usually the CPU timer interrupt if
  22  * counter register is present or, for CPUs with an external FPU, by
  23  * convention it's the FPU exception interrupt.
  24  *
  25  * Don't even think about using this on SMP.  You have been warned.
  26  *
  27  * This file exports one global function:
  28  *      void mips_cpu_irq_init(int irq_base);
  29  */
  30 #include <linux/init.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/kernel.h>
  33
  34 #include <asm/irq_cpu.h>
  35 #include <asm/mipsregs.h>
  36 #include <asm/mipsmtregs.h>
  37 #include <asm/system.h>
  38
  39 static int mips_cpu_irq_base;
  40
  41 static inline void unmask_mips_irq(unsigned int irq)
  42 {
  43         set_c0_status(0x100 << (irq - mips_cpu_irq_base));
  44         irq_enable_hazard();
  45 }
  46
  47 static inline void mask_mips_irq(unsigned int irq)
  48 {
  49         clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
  50         irq_disable_hazard();
  51 }
  52
  53 static inline void mips_cpu_irq_enable(unsigned int irq)
  54 {
  55         unsigned long flags;
  56
  57         local_irq_save(flags);
  58         unmask_mips_irq(irq);
  59         back_to_back_c0_hazard();
  60         local_irq_restore(flags);
  61 }
  62
  63 static void mips_cpu_irq_disable(unsigned int irq)
  64 {
  65         unsigned long flags;
  66
  67         local_irq_save(flags);
  68         mask_mips_irq(irq);
  69         back_to_back_c0_hazard();
  70         local_irq_restore(flags);
  71 }
  72
  73 static unsigned int mips_cpu_irq_startup(unsigned int irq)
  74 {
  75         mips_cpu_irq_enable(irq);
  76
  77         return 0;
  78 }
  79
  80 #define mips_cpu_irq_shutdown           mips_cpu_irq_disable
  81
  82 /*
  83  * While we ack the interrupt interrupts are disabled and thus we don't need
  84  * to deal with concurrency issues.  Same for mips_cpu_irq_end.
  85  */
  86 static void mips_cpu_irq_ack(unsigned int irq)
  87 {
  88         mask_mips_irq(irq);
  89 }
  90
  91 static void mips_cpu_irq_end(unsigned int irq)
  92 {
  93         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  94                 unmask_mips_irq(irq);
  95 }
  96
  97 static hw_irq_controller mips_cpu_irq_controller = {
  98         .typename       = "MIPS",
  99         .startup        = mips_cpu_irq_startup,
 100         .shutdown       = mips_cpu_irq_shutdown,
 101         .enable         = mips_cpu_irq_enable,
 102         .disable        = mips_cpu_irq_disable,
 103         .ack            = mips_cpu_irq_ack,
 104         .end            = mips_cpu_irq_end,
 105 };
 106
 107 /*
 108  * Basically the same as above but taking care of all the MT stuff
 109  */
 110
 111 #define unmask_mips_mt_irq      unmask_mips_irq
 112 #define mask_mips_mt_irq        mask_mips_irq
 113 #define mips_mt_cpu_irq_enable  mips_cpu_irq_enable
 114 #define mips_mt_cpu_irq_disable mips_cpu_irq_disable
 115
 116 static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
 117 {
 118         unsigned int vpflags = dvpe();
 119
 120         clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
 121         evpe(vpflags);
 122         mips_mt_cpu_irq_enable(irq);
 123
 124         return 0;
 125 }
 126
 127 #define mips_mt_cpu_irq_shutdown        mips_mt_cpu_irq_disable
 128
 129 /*
 130  * While we ack the interrupt interrupts are disabled and thus we don't need
 131  * to deal with concurrency issues.  Same for mips_cpu_irq_end.
 132  */
 133 static void mips_mt_cpu_irq_ack(unsigned int irq)
 134 {
 135         unsigned int vpflags = dvpe();
 136         clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
 137         evpe(vpflags);
 138         mask_mips_mt_irq(irq);
 139 }
 140
 141 #define mips_mt_cpu_irq_end mips_cpu_irq_end
 142
 143 static hw_irq_controller mips_mt_cpu_irq_controller = {
 144         .typename       = "MIPS",
 145         .startup        = mips_mt_cpu_irq_startup,
 146         .shutdown       = mips_mt_cpu_irq_shutdown,
 147         .enable         = mips_mt_cpu_irq_enable,
 148         .disable        = mips_mt_cpu_irq_disable,
 149         .ack            = mips_mt_cpu_irq_ack,
 150         .end            = mips_mt_cpu_irq_end,
 151 };
 152
 153 void __init mips_cpu_irq_init(int irq_base)
 154 {
 155         int i;
 156
 157         /* Mask interrupts. */
 158         clear_c0_status(ST0_IM);
 159         clear_c0_cause(CAUSEF_IP);
 160
 161         /*
 162          * Only MT is using the software interrupts currently, so we just
 163          * leave them uninitialized for other processors.
 164          */
 165         if (cpu_has_mipsmt)
 166                 for (i = irq_base; i < irq_base + 2; i++) {
 167                         irq_desc[i].status = IRQ_DISABLED;
 168                         irq_desc[i].action = NULL;
 169                         irq_desc[i].depth = 1;
 170                         irq_desc[i].handler = &mips_mt_cpu_irq_controller;
 171                 }
 172
 173         for (i = irq_base + 2; i < irq_base + 8; i++) {
 174                 irq_desc[i].status = IRQ_DISABLED;
 175                 irq_desc[i].action = NULL;
 176                 irq_desc[i].depth = 1;
 177                 irq_desc[i].handler = &mips_cpu_irq_controller;
 178         }
 179
 180         mips_cpu_irq_base = irq_base;
 181 }