2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
5 * ########################################################################
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 * ########################################################################
22 * Interrupt exception dispatch code.
25 #include <linux/config.h>
28 #include <asm/mipsregs.h>
29 #include <asm/regdef.h>
30 #include <asm/stackframe.h>
32 #ifdef CONFIG_MIPS_ATLAS
33 #include <asm/mips-boards/atlasint.h>
34 #define CASCADE_IRQ MIPSCPU_INT_ATLAS
35 #define CASCADE_DISPATCH atlas_hw0_irqdispatch
37 #ifdef CONFIG_MIPS_MALTA
38 #include <asm/mips-boards/maltaint.h>
39 #define CASCADE_IRQ MIPSCPU_INT_I8259A
40 #define CASCADE_DISPATCH malta_hw0_irqdispatch
42 #ifdef CONFIG_MIPS_SEAD
43 #include <asm/mips-boards/seadint.h>
46 /* A lot of complication here is taken away because:
48 * 1) We handle one interrupt and return, sitting in a loop and moving across
49 * all the pending IRQ bits in the cause register is _NOT_ the answer, the
50 * common case is one pending IRQ so optimize in that direction.
52 * 2) We need not check against bits in the status register IRQ mask, that
53 * would make this routine slow as hell.
55 * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
56 * between like BSD spl() brain-damage.
58 * Furthermore, the IRQs on the MIPS board look basically (barring software
59 * IRQs which we don't use at all and all external interrupt sources are
60 * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
64 * 0 Software (ignored)
65 * 1 Software (ignored)
66 * 2 Combined hardware interrupt (hw0)
67 * 3 Hardware (ignored)
68 * 4 Hardware (ignored)
69 * 5 Hardware (ignored)
70 * 6 Hardware (ignored)
71 * 7 R4k timer (what we use)
73 * Note: On the SEAD board thing are a little bit different.
74 * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
77 * We handle the IRQ according to _our_ priority which is:
79 * Highest ---- R4k Timer
80 * Lowest ---- Combined hardware interrupt
82 * then we just return, if multiple IRQs are pending then we will just take
83 * another exception, big deal.
90 NESTED(mipsIRQ, PT_SIZE, sp)
95 mfc0 s0, CP0_CAUSE # get irq bits
96 mfc0 s1, CP0_STATUS # get irq mask
97 andi s0, ST0_IM # CAUSE.CE may be non-zero!
100 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
105 addu a0, 31-CAUSEB_IP
133 addu a0, MIPSCPU_INT_BASE
142 addu a0, MIPSCPU_INT_BASE