drivers/scsi/sun3_scsi.h

   1 /*
   2  * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
   3  *
   4  * Sun3 DMA additions by Sam Creasey (sammy@sammy.net)
   5  *
   6  * Adapted from mac_scsinew.h:
   7  */
   8 /*
   9  * Cumana Generic NCR5380 driver defines
  10  *
  11  * Copyright 1993, Drew Eckhardt
  12  *      Visionary Computing
  13  *      (Unix and Linux consulting and custom programming)
  14  *      drew@colorado.edu
  15  *      +1 (303) 440-4894
  16  */
  17
  18 #ifndef SUN3_SCSI_H
  19 #define SUN3_SCSI_H
  20
  21 /* additional registers - mainly DMA control regs */
  22 /* these start at regbase + 8 -- directly after the NCR regs */
  23 struct sun3_dma_regs {
  24         unsigned short dma_addr_hi; /* vme only */
  25         unsigned short dma_addr_lo; /* vme only */
  26         unsigned short dma_count_hi; /* vme only */
  27         unsigned short dma_count_lo; /* vme only */
  28         unsigned short udc_data; /* udc dma data reg (obio only) */
  29         unsigned short udc_addr; /* uda dma addr reg (obio only) */
  30         unsigned short fifo_data; /* fifo data reg, holds extra byte on
  31                                      odd dma reads */
  32         unsigned short fifo_count;
  33         unsigned short csr; /* control/status reg */
  34         unsigned short bpack_hi; /* vme only */
  35         unsigned short bpack_lo; /* vme only */
  36         unsigned short ivect; /* vme only */
  37         unsigned short fifo_count_hi; /* vme only */
  38 };
  39
  40 /* ucd chip specific regs - live in dvma space */
  41 struct sun3_udc_regs {
  42      unsigned short rsel; /* select regs to load */
  43      unsigned short addr_hi; /* high word of addr */
  44      unsigned short addr_lo; /* low word */
  45      unsigned short count; /* words to be xfer'd */
  46      unsigned short mode_hi; /* high word of channel mode */
  47      unsigned short mode_lo; /* low word of channel mode */
  48 };
  49
  50 /* addresses of the udc registers */
  51 #define UDC_MODE 0x38
  52 #define UDC_CSR 0x2e /* command/status */
  53 #define UDC_CHN_HI 0x26 /* chain high word */
  54 #define UDC_CHN_LO 0x22 /* chain lo word */
  55 #define UDC_CURA_HI 0x1a /* cur reg A high */
  56 #define UDC_CURA_LO 0x0a /* cur reg A low */
  57 #define UDC_CURB_HI 0x12 /* cur reg B high */
  58 #define UDC_CURB_LO 0x02 /* cur reg B low */
  59 #define UDC_MODE_HI 0x56 /* mode reg high */
  60 #define UDC_MODE_LO 0x52 /* mode reg low */
  61 #define UDC_COUNT 0x32 /* words to xfer */
  62
  63 /* some udc commands */
  64 #define UDC_RESET 0
  65 #define UDC_CHN_START 0xa0 /* start chain */
  66 #define UDC_INT_ENABLE 0x32 /* channel 1 int on */
  67
  68 /* udc mode words */
  69 #define UDC_MODE_HIWORD 0x40
  70 #define UDC_MODE_LSEND 0xc2
  71 #define UDC_MODE_LRECV 0xd2
  72
  73 /* udc reg selections */
  74 #define UDC_RSEL_SEND 0x282
  75 #define UDC_RSEL_RECV 0x182
  76
  77 /* bits in csr reg */
  78 #define CSR_DMA_ACTIVE 0x8000
  79 #define CSR_DMA_CONFLICT 0x4000
  80 #define CSR_DMA_BUSERR 0x2000
  81
  82 #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
  83 #define CSR_SDB_INT 0x200 /* sbc interrupt pending */
  84 #define CSR_DMA_INT 0x100 /* dma interrupt pending */
  85
  86 #define CSR_LEFT 0xc0
  87 #define CSR_LEFT_3 0xc0
  88 #define CSR_LEFT_2 0x80
  89 #define CSR_LEFT_1 0x40
  90 #define CSR_PACK_ENABLE 0x20
  91
  92 #define CSR_DMA_ENABLE 0x10
  93
  94 #define CSR_SEND 0x8 /* 1 = send  0 = recv */
  95 #define CSR_FIFO 0x2 /* reset fifo */
  96 #define CSR_INTR 0x4 /* interrupt enable */
  97 #define CSR_SCSI 0x1
  98
  99 #define VME_DATA24 0x3d00
 100
 101 #endif /* SUN3_SCSI_H */
 102