1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for ICEnsemble VT1724 (Envy24HT)
5 * Lowlevel functions for Infrasonic Quartet
7 * Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <sound/core.h>
16 #include <sound/tlv.h>
17 #include <sound/info.h>
21 #include <sound/ak4113.h>
25 struct ak4113
*ak4113
;
26 unsigned int scr
; /* system control register */
27 unsigned int mcr
; /* monitoring control register */
28 unsigned int cpld
; /* cpld register */
31 struct qtet_kcontrol_private
{
33 void (*set_register
)(struct snd_ice1712
*ice
, unsigned int val
);
34 unsigned int (*get_register
)(struct snd_ice1712
*ice
);
35 const char * const texts
[2];
51 static const char * const ext_clock_names
[3] = {"IEC958 In", "Word Clock 1xFS",
54 /* chip address on I2C bus */
55 #define AK4113_ADDR 0x26 /* S/PDIF receiver */
57 /* chip address on SPI bus */
58 #define AK4620_ADDR 0x02 /* ADC/DAC */
65 /* GPIO0 - O - DATA0, def. 0 */
66 #define GPIO_D0 (1<<0)
67 /* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
68 #define GPIO_D1_JACKDTC0 (1<<1)
69 /* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
70 #define GPIO_D2_JACKDTC1 (1<<2)
71 /* GPIO3 - I/O - DATA3, def. 1 */
72 #define GPIO_D3 (1<<3)
73 /* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
74 #define GPIO_D4_SPI_CDTO (1<<4)
75 /* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
76 #define GPIO_D5_SPI_CCLK (1<<5)
77 /* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
78 #define GPIO_D6_CD (1<<6)
79 /* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
80 #define GPIO_D7_DD (1<<7)
81 /* GPIO8 - O - CPLD Chip Select, def. 1 */
82 #define GPIO_CPLD_CSN (1<<8)
83 /* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
84 #define GPIO_CPLD_RW (1<<9)
85 /* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
86 #define GPIO_SPI_CSN0 (1<<10)
87 /* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
88 #define GPIO_SPI_CSN1 (1<<11)
89 /* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
91 #define GPIO_EX_GPIOE (1<<12)
92 /* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
94 #define GPIO_SCR (1<<13)
95 /* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
97 #define GPIO_MCR (1<<14)
99 #define GPIO_SPI_ALL (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
100 GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
102 #define GPIO_DATA_MASK (GPIO_D0 | GPIO_D1_JACKDTC0 | \
103 GPIO_D2_JACKDTC1 | GPIO_D3 | \
104 GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
105 GPIO_D6_CD | GPIO_D7_DD)
107 /* System Control Register GPIO_SCR data bits */
108 /* Mic/Line select relay (0:line, 1:mic) */
109 #define SCR_RELAY GPIO_D0
110 /* Phantom power drive control (0:5V, 1:48V) */
111 #define SCR_PHP_V GPIO_D1_JACKDTC0
112 /* H/W mute control (0:Normal, 1:Mute) */
113 #define SCR_MUTE GPIO_D2_JACKDTC1
114 /* Phantom power control (0:Phantom on, 1:off) */
115 #define SCR_PHP GPIO_D3
116 /* Analog input 1/2 Source Select */
117 #define SCR_AIN12_SEL0 GPIO_D4_SPI_CDTO
118 #define SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK
119 /* Analog input 3/4 Source Select (0:line, 1:hi-z) */
120 #define SCR_AIN34_SEL GPIO_D6_CD
121 /* Codec Power Down (0:power down, 1:normal) */
122 #define SCR_CODEC_PDN GPIO_D7_DD
124 #define SCR_AIN12_LINE (0)
125 #define SCR_AIN12_MIC (SCR_AIN12_SEL0)
126 #define SCR_AIN12_LOWCUT (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
128 /* Monitor Control Register GPIO_MCR data bits */
129 /* Input 1/2 to Monitor 1/2 (0:off, 1:on) */
130 #define MCR_IN12_MON12 GPIO_D0
131 /* Input 1/2 to Monitor 3/4 (0:off, 1:on) */
132 #define MCR_IN12_MON34 GPIO_D1_JACKDTC0
133 /* Input 3/4 to Monitor 1/2 (0:off, 1:on) */
134 #define MCR_IN34_MON12 GPIO_D2_JACKDTC1
135 /* Input 3/4 to Monitor 3/4 (0:off, 1:on) */
136 #define MCR_IN34_MON34 GPIO_D3
137 /* Output to Monitor 1/2 (0:off, 1:on) */
138 #define MCR_OUT34_MON12 GPIO_D4_SPI_CDTO
139 /* Output to Monitor 3/4 (0:off, 1:on) */
140 #define MCR_OUT12_MON34 GPIO_D5_SPI_CCLK
142 /* CPLD Register DATA bits */
143 /* Clock Rate Select */
144 #define CPLD_CKS0 GPIO_D0
145 #define CPLD_CKS1 GPIO_D1_JACKDTC0
146 #define CPLD_CKS2 GPIO_D2_JACKDTC1
147 /* Sync Source Select (0:Internal, 1:External) */
148 #define CPLD_SYNC_SEL GPIO_D3
149 /* Word Clock FS Select (0:FS, 1:256FS) */
150 #define CPLD_WORD_SEL GPIO_D4_SPI_CDTO
151 /* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */
152 #define CPLD_COAX_OUT GPIO_D5_SPI_CCLK
153 /* Input 1/2 Source Select (0:Analog12, 1:An34) */
154 #define CPLD_IN12_SEL GPIO_D6_CD
155 /* Input 3/4 Source Select (0:Analog34, 1:Digital In) */
156 #define CPLD_IN34_SEL GPIO_D7_DD
158 /* internal clock (CPLD_SYNC_SEL = 0) options */
159 #define CPLD_CKS_44100HZ (0)
160 #define CPLD_CKS_48000HZ (CPLD_CKS0)
161 #define CPLD_CKS_88200HZ (CPLD_CKS1)
162 #define CPLD_CKS_96000HZ (CPLD_CKS1 | CPLD_CKS0)
163 #define CPLD_CKS_176400HZ (CPLD_CKS2)
164 #define CPLD_CKS_192000HZ (CPLD_CKS2 | CPLD_CKS0)
166 #define CPLD_CKS_MASK (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
168 /* external clock (CPLD_SYNC_SEL = 1) options */
169 /* external clock - SPDIF */
170 #define CPLD_EXT_SPDIF (0 | CPLD_SYNC_SEL)
171 /* external clock - WordClock 1xfs */
172 #define CPLD_EXT_WORDCLOCK_1FS (CPLD_CKS1 | CPLD_SYNC_SEL)
173 /* external clock - WordClock 256xfs */
174 #define CPLD_EXT_WORDCLOCK_256FS (CPLD_CKS1 | CPLD_WORD_SEL |\
177 #define EXT_SPDIF_TYPE 0
178 #define EXT_WORDCLOCK_1FS_TYPE 1
179 #define EXT_WORDCLOCK_256FS_TYPE 2
181 #define AK4620_DFS0 (1<<0)
182 #define AK4620_DFS1 (1<<1)
183 #define AK4620_CKS0 (1<<2)
184 #define AK4620_CKS1 (1<<3)
185 /* Clock and Format Control register */
186 #define AK4620_DFS_REG 0x02
188 /* Deem and Volume Control register */
189 #define AK4620_DEEMVOL_REG 0x03
190 #define AK4620_SMUTE (1<<7)
193 * Conversion from int value to its binary form. Used for debugging.
194 * The output buffer must be allocated prior to calling the function.
196 static char *get_binary(char *buffer
, int value
)
200 for (i
= 0; i
< 4; ++i
) {
201 for (j
= 0; j
< 8; ++j
) {
202 if (value
& (1 << (31-(i
*8 + j
))))
218 * Initial setup of the conversion array GPIO <-> rate
220 static const unsigned int qtet_rates
[] = {
222 96000, 176400, 192000,
225 static const unsigned int cks_vals
[] = {
226 CPLD_CKS_44100HZ
, CPLD_CKS_48000HZ
, CPLD_CKS_88200HZ
,
227 CPLD_CKS_96000HZ
, CPLD_CKS_176400HZ
, CPLD_CKS_192000HZ
,
230 static const struct snd_pcm_hw_constraint_list qtet_rates_info
= {
231 .count
= ARRAY_SIZE(qtet_rates
),
236 static void qtet_ak4113_write(void *private_data
, unsigned char reg
,
239 snd_vt1724_write_i2c((struct snd_ice1712
*)private_data
, AK4113_ADDR
,
243 static unsigned char qtet_ak4113_read(void *private_data
, unsigned char reg
)
245 return snd_vt1724_read_i2c((struct snd_ice1712
*)private_data
,
255 * Write data to addr register of ak4620
257 static void qtet_akm_write(struct snd_akm4xxx
*ak
, int chip
,
258 unsigned char addr
, unsigned char data
)
260 unsigned int tmp
, orig_dir
;
262 unsigned int addrdata
;
263 struct snd_ice1712
*ice
= ak
->private_data
[0];
265 if (snd_BUG_ON(chip
< 0 || chip
>= 4))
267 /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,
268 data=0x%x\n", chip, addr, data);*/
269 orig_dir
= ice
->gpio
.get_dir(ice
);
270 ice
->gpio
.set_dir(ice
, orig_dir
| GPIO_SPI_ALL
);
271 /* set mask - only SPI bits */
272 ice
->gpio
.set_mask(ice
, ~GPIO_SPI_ALL
);
274 tmp
= ice
->gpio
.get_data(ice
);
277 ice
->gpio
.set_data(ice
, tmp
);
279 /* drop chip select */
282 tmp
&= ~GPIO_SPI_CSN1
;
284 tmp
&= ~GPIO_SPI_CSN0
;
285 ice
->gpio
.set_data(ice
, tmp
);
288 /* build I2C address + data byte */
289 addrdata
= (AK4620_ADDR
<< 6) | 0x20 | (addr
& 0x1f);
290 addrdata
= (addrdata
<< 8) | data
;
291 for (idx
= 15; idx
>= 0; idx
--) {
293 tmp
&= ~GPIO_D5_SPI_CCLK
;
294 ice
->gpio
.set_data(ice
, tmp
);
297 if (addrdata
& (1 << idx
))
298 tmp
|= GPIO_D4_SPI_CDTO
;
300 tmp
&= ~GPIO_D4_SPI_CDTO
;
301 ice
->gpio
.set_data(ice
, tmp
);
304 tmp
|= GPIO_D5_SPI_CCLK
;
305 ice
->gpio
.set_data(ice
, tmp
);
310 ice
->gpio
.set_data(ice
, tmp
);
313 /* return all gpios to non-writable */
314 ice
->gpio
.set_mask(ice
, 0xffffff);
315 /* restore GPIOs direction */
316 ice
->gpio
.set_dir(ice
, orig_dir
);
319 static void qtet_akm_set_regs(struct snd_akm4xxx
*ak
, unsigned char addr
,
320 unsigned char mask
, unsigned char value
)
324 for (chip
= 0; chip
< ak
->num_chips
; chip
++) {
325 tmp
= snd_akm4xxx_get(ak
, chip
, addr
);
328 /* set the new bits */
330 snd_akm4xxx_write(ak
, chip
, addr
, tmp
);
335 * change the rate of AK4620
337 static void qtet_akm_set_rate_val(struct snd_akm4xxx
*ak
, unsigned int rate
)
339 unsigned char ak4620_dfs
;
341 if (rate
== 0) /* no hint - S/PDIF input is master or the new spdif
342 input rate undetected, simply return */
345 /* adjust DFS on codecs - see datasheet */
347 ak4620_dfs
= AK4620_DFS1
| AK4620_CKS1
;
348 else if (rate
> 54000)
349 ak4620_dfs
= AK4620_DFS0
| AK4620_CKS0
;
354 qtet_akm_set_regs(ak
, AK4620_DFS_REG
, AK4620_DFS0
| AK4620_DFS1
|
355 AK4620_CKS0
| AK4620_CKS1
, ak4620_dfs
);
358 #define AK_CONTROL(xname, xch) { .name = xname, .num_channels = xch }
360 #define PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume"
361 #define PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume"
362 #define PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume"
363 #define PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume"
365 static const struct snd_akm4xxx_dac_channel qtet_dac
[] = {
366 AK_CONTROL(PCM_12_PLAYBACK_VOLUME
, 2),
367 AK_CONTROL(PCM_34_PLAYBACK_VOLUME
, 2),
370 static const struct snd_akm4xxx_adc_channel qtet_adc
[] = {
371 AK_CONTROL(PCM_12_CAPTURE_VOLUME
, 2),
372 AK_CONTROL(PCM_34_CAPTURE_VOLUME
, 2),
375 static const struct snd_akm4xxx akm_qtet_dac
= {
377 .num_dacs
= 4, /* DAC1 - Output 12
379 .num_adcs
= 4, /* ADC1 - Input 12
382 .write
= qtet_akm_write
,
383 .set_rate_val
= qtet_akm_set_rate_val
,
385 .dac_info
= qtet_dac
,
386 .adc_info
= qtet_adc
,
389 /* Communication routines with the CPLD */
392 /* Writes data to external register reg, both reg and data are
393 * GPIO representations */
394 static void reg_write(struct snd_ice1712
*ice
, unsigned int reg
,
399 mutex_lock(&ice
->gpio_mutex
);
400 /* set direction of used GPIOs*/
403 ice
->gpio
.set_dir(ice
, tmp
);
404 /* mask - writable bits */
405 ice
->gpio
.set_mask(ice
, ~(tmp
));
407 tmp
= ice
->gpio
.get_data(ice
);
408 tmp
&= ~GPIO_DATA_MASK
;
410 ice
->gpio
.set_data(ice
, tmp
);
412 /* drop output enable */
413 tmp
&= ~GPIO_EX_GPIOE
;
414 ice
->gpio
.set_data(ice
, tmp
);
416 /* drop the register gpio */
418 ice
->gpio
.set_data(ice
, tmp
);
420 /* raise the register GPIO */
422 ice
->gpio
.set_data(ice
, tmp
);
425 /* raise all data gpios */
426 tmp
|= GPIO_DATA_MASK
;
427 ice
->gpio
.set_data(ice
, tmp
);
428 /* mask - immutable bits */
429 ice
->gpio
.set_mask(ice
, 0xffffff);
430 /* outputs only 8-15 */
431 ice
->gpio
.set_dir(ice
, 0x00ff00);
432 mutex_unlock(&ice
->gpio_mutex
);
435 static unsigned int get_scr(struct snd_ice1712
*ice
)
437 struct qtet_spec
*spec
= ice
->spec
;
441 static unsigned int get_mcr(struct snd_ice1712
*ice
)
443 struct qtet_spec
*spec
= ice
->spec
;
447 static unsigned int get_cpld(struct snd_ice1712
*ice
)
449 struct qtet_spec
*spec
= ice
->spec
;
453 static void set_scr(struct snd_ice1712
*ice
, unsigned int val
)
455 struct qtet_spec
*spec
= ice
->spec
;
456 reg_write(ice
, GPIO_SCR
, val
);
460 static void set_mcr(struct snd_ice1712
*ice
, unsigned int val
)
462 struct qtet_spec
*spec
= ice
->spec
;
463 reg_write(ice
, GPIO_MCR
, val
);
467 static void set_cpld(struct snd_ice1712
*ice
, unsigned int val
)
469 struct qtet_spec
*spec
= ice
->spec
;
470 reg_write(ice
, GPIO_CPLD_CSN
, val
);
474 static void proc_regs_read(struct snd_info_entry
*entry
,
475 struct snd_info_buffer
*buffer
)
477 struct snd_ice1712
*ice
= entry
->private_data
;
480 snd_iprintf(buffer
, "SCR: %s\n", get_binary(bin_buffer
,
482 snd_iprintf(buffer
, "MCR: %s\n", get_binary(bin_buffer
,
484 snd_iprintf(buffer
, "CPLD: %s\n", get_binary(bin_buffer
,
488 static void proc_init(struct snd_ice1712
*ice
)
490 snd_card_ro_proc_new(ice
->card
, "quartet", ice
, proc_regs_read
);
493 static int qtet_mute_get(struct snd_kcontrol
*kcontrol
,
494 struct snd_ctl_elem_value
*ucontrol
)
496 struct snd_ice1712
*ice
= snd_kcontrol_chip(kcontrol
);
498 val
= get_scr(ice
) & SCR_MUTE
;
499 ucontrol
->value
.integer
.value
[0] = (val
) ? 0 : 1;
503 static int qtet_mute_put(struct snd_kcontrol
*kcontrol
,
504 struct snd_ctl_elem_value
*ucontrol
)
506 struct snd_ice1712
*ice
= snd_kcontrol_chip(kcontrol
);
507 unsigned int old
, new, smute
;
508 old
= get_scr(ice
) & SCR_MUTE
;
509 if (ucontrol
->value
.integer
.value
[0]) {
518 smute
= AK4620_SMUTE
;
521 struct snd_akm4xxx
*ak
= ice
->akm
;
522 set_scr(ice
, (get_scr(ice
) & ~SCR_MUTE
) | new);
524 qtet_akm_set_regs(ak
, AK4620_DEEMVOL_REG
, AK4620_SMUTE
, smute
);
531 static int qtet_ain12_enum_info(struct snd_kcontrol
*kcontrol
,
532 struct snd_ctl_elem_info
*uinfo
)
534 static const char * const texts
[3] =
535 {"Line In 1/2", "Mic", "Mic + Low-cut"};
536 return snd_ctl_enum_info(uinfo
, 1, ARRAY_SIZE(texts
), texts
);
539 static int qtet_ain12_sw_get(struct snd_kcontrol
*kcontrol
,
540 struct snd_ctl_elem_value
*ucontrol
)
542 struct snd_ice1712
*ice
= snd_kcontrol_chip(kcontrol
);
543 unsigned int val
, result
;
544 val
= get_scr(ice
) & (SCR_AIN12_SEL1
| SCR_AIN12_SEL0
);
552 case SCR_AIN12_LOWCUT
:
556 /* BUG - no other combinations allowed */
560 ucontrol
->value
.integer
.value
[0] = result
;
564 static int qtet_ain12_sw_put(struct snd_kcontrol
*kcontrol
,
565 struct snd_ctl_elem_value
*ucontrol
)
567 struct snd_ice1712
*ice
= snd_kcontrol_chip(kcontrol
);
568 unsigned int old
, new, tmp
, masked_old
;
569 old
= new = get_scr(ice
);
570 masked_old
= old
& (SCR_AIN12_SEL1
| SCR_AIN12_SEL0
);
571 tmp
= ucontrol
->value
.integer
.value
[0];
573 tmp
= 3; /* binary 10 is not supported */
574 tmp
<<= 4; /* shifting to SCR_AIN12_SEL0 */
575 if (tmp
!= masked_old
) {
576 /* change requested */
579 new = old
& ~(SCR_AIN12_SEL1
| SCR_AIN12_SEL0
);
587 new = old
| SCR_RELAY
;
589 new = (new & ~SCR_AIN12_SEL1
) | SCR_AIN12_SEL0
;
592 case SCR_AIN12_LOWCUT
:
594 new = old
| SCR_RELAY
;
596 new |= SCR_AIN12_SEL1
| SCR_AIN12_SEL0
;
608 static int qtet_php_get(struct snd_kcontrol
*kcontrol
,
609 struct snd_ctl_elem_value
*ucontrol
)
611 struct snd_ice1712
*ice
= snd_kcontrol_chip(kcontrol
);
613 /* if phantom voltage =48V, phantom on */
614 val
= get_scr(ice
) & SCR_PHP_V
;
615 ucontrol
->value
.integer
.value
[0] = val
? 1 : 0;
619 static int qtet_php_put(struct snd_kcontrol
*kcontrol
,
620 struct snd_ctl_elem_value
*ucontrol
)
622 struct snd_ice1712
*ice
= snd_kcontrol_chip(kcontrol
);
623 unsigned int old
, new;
624 old
= new = get_scr(ice
);
625 if (ucontrol
->value
.integer
.value
[0] /* phantom on requested */
626 && (~old
& SCR_PHP_V
)) /* 0 = voltage 5V */ {
627 /* is off, turn on */
628 /* turn voltage on first, = 1 */
629 new = old
| SCR_PHP_V
;
631 /* turn phantom on, = 0 */
634 } else if (!ucontrol
->value
.integer
.value
[0] && (old
& SCR_PHP_V
)) {
635 /* phantom off requested and 1 = voltage 48V */
636 /* is on, turn off */
637 /* turn voltage off first, = 0 */
638 new = old
& ~SCR_PHP_V
;
640 /* turn phantom off, = 1 */
650 #define PRIV_SW(xid, xbit, xreg) [xid] = {.bit = xbit,\
651 .set_register = set_##xreg,\
652 .get_register = get_##xreg, }
655 #define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) [xid] = {.bit = xbit,\
656 .set_register = set_##xreg,\
657 .get_register = get_##xreg,\
658 .texts = {xtext1, xtext2} }
660 static const struct qtet_kcontrol_private qtet_privates
[] = {
661 PRIV_ENUM2(IN12_SEL
, CPLD_IN12_SEL
, cpld
, "An In 1/2", "An In 3/4"),
662 PRIV_ENUM2(IN34_SEL
, CPLD_IN34_SEL
, cpld
, "An In 3/4", "IEC958 In"),
663 PRIV_ENUM2(AIN34_SEL
, SCR_AIN34_SEL
, scr
, "Line In 3/4", "Hi-Z"),
664 PRIV_ENUM2(COAX_OUT
, CPLD_COAX_OUT
, cpld
, "IEC958", "I2S"),
665 PRIV_SW(IN12_MON12
, MCR_IN12_MON12
, mcr
),
666 PRIV_SW(IN12_MON34
, MCR_IN12_MON34
, mcr
),
667 PRIV_SW(IN34_MON12
, MCR_IN34_MON12
, mcr
),
668 PRIV_SW(IN34_MON34
, MCR_IN34_MON34
, mcr
),
669 PRIV_SW(OUT12_MON34
, MCR_OUT12_MON34
, mcr
),
670 PRIV_SW(OUT34_MON12
, MCR_OUT34_MON12
, mcr
),
673 static int qtet_enum_info(struct snd_kcontrol
*kcontrol
,
674 struct snd_ctl_elem_info
*uinfo
)
676 struct qtet_kcontrol_private
private =
677 qtet_privates
[kcontrol
->private_value
];
678 return snd_ctl_enum_info(uinfo
, 1, ARRAY_SIZE(private.texts
),
682 static int qtet_sw_get(struct snd_kcontrol
*kcontrol
,
683 struct snd_ctl_elem_value
*ucontrol
)
685 struct qtet_kcontrol_private
private =
686 qtet_privates
[kcontrol
->private_value
];
687 struct snd_ice1712
*ice
= snd_kcontrol_chip(kcontrol
);
688 ucontrol
->value
.integer
.value
[0] =
689 (private.get_register(ice
) & private.bit
) ? 1 : 0;
693 static int qtet_sw_put(struct snd_kcontrol
*kcontrol
,
694 struct snd_ctl_elem_value
*ucontrol
)
696 struct qtet_kcontrol_private
private =
697 qtet_privates
[kcontrol
->private_value
];
698 struct snd_ice1712
*ice
= snd_kcontrol_chip(kcontrol
);
699 unsigned int old
, new;
700 old
= private.get_register(ice
);
701 if (ucontrol
->value
.integer
.value
[0])
702 new = old
| private.bit
;
704 new = old
& ~private.bit
;
706 private.set_register(ice
, new);
713 #define qtet_sw_info snd_ctl_boolean_mono_info
715 #define QTET_CONTROL(xname, xtype, xpriv) \
716 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
718 .info = qtet_##xtype##_info,\
721 .private_value = xpriv }
723 static const struct snd_kcontrol_new qtet_controls
[] = {
725 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
726 .name
= "Master Playback Switch",
727 .info
= qtet_sw_info
,
728 .get
= qtet_mute_get
,
729 .put
= qtet_mute_put
,
733 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
734 .name
= "Phantom Power",
735 .info
= qtet_sw_info
,
741 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
742 .name
= "Analog In 1/2 Capture Switch",
743 .info
= qtet_ain12_enum_info
,
744 .get
= qtet_ain12_sw_get
,
745 .put
= qtet_ain12_sw_put
,
748 QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL
),
749 QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL
),
750 QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL
),
751 QTET_CONTROL("Coax Output Source", enum, COAX_OUT
),
752 QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw
, IN12_MON12
),
753 QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw
, IN12_MON34
),
754 QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw
, IN34_MON12
),
755 QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw
, IN34_MON34
),
756 QTET_CONTROL("Output 1/2 to Monitor 3/4", sw
, OUT12_MON34
),
757 QTET_CONTROL("Output 3/4 to Monitor 1/2", sw
, OUT34_MON12
),
760 static const char * const follower_vols
[] = {
761 PCM_12_PLAYBACK_VOLUME
,
762 PCM_34_PLAYBACK_VOLUME
,
767 DECLARE_TLV_DB_SCALE(qtet_master_db_scale
, -6350, 50, 1);
769 static struct snd_kcontrol
*ctl_find(struct snd_card
*card
,
772 struct snd_ctl_elem_id sid
= {0};
774 strlcpy(sid
.name
, name
, sizeof(sid
.name
));
775 sid
.iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
776 return snd_ctl_find_id(card
, &sid
);
779 static void add_followers(struct snd_card
*card
,
780 struct snd_kcontrol
*master
, const char * const *list
)
782 for (; *list
; list
++) {
783 struct snd_kcontrol
*follower
= ctl_find(card
, *list
);
785 snd_ctl_add_follower(master
, follower
);
789 static int qtet_add_controls(struct snd_ice1712
*ice
)
791 struct qtet_spec
*spec
= ice
->spec
;
793 struct snd_kcontrol
*vmaster
;
794 err
= snd_ice1712_akm4xxx_build_controls(ice
);
797 for (i
= 0; i
< ARRAY_SIZE(qtet_controls
); i
++) {
798 err
= snd_ctl_add(ice
->card
,
799 snd_ctl_new1(&qtet_controls
[i
], ice
));
804 /* Create virtual master control */
805 vmaster
= snd_ctl_make_virtual_master("Master Playback Volume",
806 qtet_master_db_scale
);
809 add_followers(ice
->card
, vmaster
, follower_vols
);
810 err
= snd_ctl_add(ice
->card
, vmaster
);
813 /* only capture SPDIF over AK4113 */
814 return snd_ak4113_build(spec
->ak4113
,
815 ice
->pcm
->streams
[SNDRV_PCM_STREAM_CAPTURE
].substream
);
818 static inline int qtet_is_spdif_master(struct snd_ice1712
*ice
)
820 /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */
821 return (get_cpld(ice
) & CPLD_SYNC_SEL
) ? 1 : 0;
824 static unsigned int qtet_get_rate(struct snd_ice1712
*ice
)
827 unsigned char result
;
829 result
= get_cpld(ice
) & CPLD_CKS_MASK
;
830 for (i
= 0; i
< ARRAY_SIZE(cks_vals
); i
++)
831 if (cks_vals
[i
] == result
)
832 return qtet_rates
[i
];
836 static int get_cks_val(int rate
)
839 for (i
= 0; i
< ARRAY_SIZE(qtet_rates
); i
++)
840 if (qtet_rates
[i
] == rate
)
845 /* setting new rate */
846 static void qtet_set_rate(struct snd_ice1712
*ice
, unsigned int rate
)
850 /* switching ice1724 to external clock - supplied by ext. circuits */
851 val
= inb(ICEMT1724(ice
, RATE
));
852 outb(val
| VT1724_SPDIF_MASTER
, ICEMT1724(ice
, RATE
));
854 new = (get_cpld(ice
) & ~CPLD_CKS_MASK
) | get_cks_val(rate
);
855 /* switch to internal clock, drop CPLD_SYNC_SEL */
856 new &= ~CPLD_SYNC_SEL
;
857 /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",
858 get_cpld(ice), new); */
862 static inline unsigned char qtet_set_mclk(struct snd_ice1712
*ice
,
865 /* no change in master clock */
869 /* setting clock to external - SPDIF */
870 static int qtet_set_spdif_clock(struct snd_ice1712
*ice
, int type
)
872 unsigned int old
, new;
874 old
= new = get_cpld(ice
);
875 new &= ~(CPLD_CKS_MASK
| CPLD_WORD_SEL
);
878 new |= CPLD_EXT_SPDIF
;
880 case EXT_WORDCLOCK_1FS_TYPE
:
881 new |= CPLD_EXT_WORDCLOCK_1FS
;
883 case EXT_WORDCLOCK_256FS_TYPE
:
884 new |= CPLD_EXT_WORDCLOCK_256FS
;
897 static int qtet_get_spdif_master_type(struct snd_ice1712
*ice
)
902 /* checking only rate/clock-related bits */
903 val
&= (CPLD_CKS_MASK
| CPLD_WORD_SEL
| CPLD_SYNC_SEL
);
904 if (!(val
& CPLD_SYNC_SEL
)) {
905 /* switched to internal clock, is not any external type */
909 case (CPLD_EXT_SPDIF
):
910 result
= EXT_SPDIF_TYPE
;
912 case (CPLD_EXT_WORDCLOCK_1FS
):
913 result
= EXT_WORDCLOCK_1FS_TYPE
;
915 case (CPLD_EXT_WORDCLOCK_256FS
):
916 result
= EXT_WORDCLOCK_256FS_TYPE
;
919 /* undefined combination of external clock setup */
927 /* Called when ak4113 detects change in the input SPDIF stream */
928 static void qtet_ak4113_change(struct ak4113
*ak4113
, unsigned char c0
,
931 struct snd_ice1712
*ice
= ak4113
->change_callback_private
;
933 if ((qtet_get_spdif_master_type(ice
) == EXT_SPDIF_TYPE
) &&
935 /* only for SPDIF master mode, rate was changed */
936 rate
= snd_ak4113_external_rate(ak4113
);
937 /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",
939 qtet_akm_set_rate_val(ice
->akm
, rate
);
944 * If clock slaved to SPDIF-IN, setting runtime rate
945 * to the detected external rate
947 static void qtet_spdif_in_open(struct snd_ice1712
*ice
,
948 struct snd_pcm_substream
*substream
)
950 struct qtet_spec
*spec
= ice
->spec
;
951 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
954 if (qtet_get_spdif_master_type(ice
) != EXT_SPDIF_TYPE
)
955 /* not external SPDIF, no rate limitation */
957 /* only external SPDIF can detect incoming sample rate */
958 rate
= snd_ak4113_external_rate(spec
->ak4113
);
959 if (rate
>= runtime
->hw
.rate_min
&& rate
<= runtime
->hw
.rate_max
) {
960 runtime
->hw
.rate_min
= rate
;
961 runtime
->hw
.rate_max
= rate
;
966 * initialize the chip
968 static int qtet_init(struct snd_ice1712
*ice
)
970 static const unsigned char ak4113_init_vals
[] = {
971 /* AK4113_REG_PWRDN */ AK4113_RST
| AK4113_PWN
|
972 AK4113_OCKS0
| AK4113_OCKS1
,
973 /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S
| AK4113_VTX
|
974 AK4113_DEM_OFF
| AK4113_DEAU
,
975 /* AK4113_REG_IO0 */ AK4113_OPS2
| AK4113_TXE
|
977 /* AK4113_REG_IO1 */ AK4113_EFH_1024LRCLK
| AK4113_IPS(0),
978 /* AK4113_REG_INT0_MASK */ 0,
979 /* AK4113_REG_INT1_MASK */ 0,
980 /* AK4113_REG_DATDTS */ 0,
983 struct qtet_spec
*spec
;
984 struct snd_akm4xxx
*ak
;
987 /* switching ice1724 to external clock - supplied by ext. circuits */
988 val
= inb(ICEMT1724(ice
, RATE
));
989 outb(val
| VT1724_SPDIF_MASTER
, ICEMT1724(ice
, RATE
));
991 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
994 /* qtet is clocked by Xilinx array */
995 ice
->hw_rates
= &qtet_rates_info
;
996 ice
->is_spdif_master
= qtet_is_spdif_master
;
997 ice
->get_rate
= qtet_get_rate
;
998 ice
->set_rate
= qtet_set_rate
;
999 ice
->set_mclk
= qtet_set_mclk
;
1000 ice
->set_spdif_clock
= qtet_set_spdif_clock
;
1001 ice
->get_spdif_master_type
= qtet_get_spdif_master_type
;
1002 ice
->ext_clock_names
= ext_clock_names
;
1003 ice
->ext_clock_count
= ARRAY_SIZE(ext_clock_names
);
1004 /* since Qtet can detect correct SPDIF-in rate, all streams can be
1005 * limited to this specific rate */
1006 ice
->spdif
.ops
.open
= ice
->pro_open
= qtet_spdif_in_open
;
1011 /* keep codec power down first */
1012 set_scr(ice
, SCR_PHP
);
1014 /* codec power up */
1015 set_scr(ice
, SCR_PHP
| SCR_CODEC_PDN
);
1017 /* MCR Initialize */
1020 /* CPLD Initialize */
1024 ice
->num_total_dacs
= 2;
1025 ice
->num_total_adcs
= 2;
1027 ice
->akm
= kcalloc(2, sizeof(struct snd_akm4xxx
), GFP_KERNEL
);
1031 /* only one codec with two chips */
1032 ice
->akm_codecs
= 1;
1033 err
= snd_ice1712_akm4xxx_init(ak
, &akm_qtet_dac
, NULL
, ice
);
1036 err
= snd_ak4113_create(ice
->card
,
1040 ice
, &spec
->ak4113
);
1043 /* callback for codecs rate setting */
1044 spec
->ak4113
->change_callback
= qtet_ak4113_change
;
1045 spec
->ak4113
->change_callback_private
= ice
;
1046 /* AK41143 in Quartet can detect external rate correctly
1047 * (i.e. check_flags = 0) */
1048 spec
->ak4113
->check_flags
= 0;
1052 qtet_set_rate(ice
, 44100);
1056 static const unsigned char qtet_eeprom
[] = {
1057 [ICE_EEP2_SYSCONF
] = 0x28, /* clock 256(24MHz), mpu401, 1xADC,
1059 [ICE_EEP2_ACLINK
] = 0x80, /* I2S */
1060 [ICE_EEP2_I2S
] = 0x78, /* 96k, 24bit, 192k */
1061 [ICE_EEP2_SPDIF
] = 0xc3, /* out-en, out-int, in, out-ext */
1062 [ICE_EEP2_GPIO_DIR
] = 0x00, /* 0-7 inputs, switched to output
1063 only during output operations */
1064 [ICE_EEP2_GPIO_DIR1
] = 0xff, /* 8-15 outputs */
1065 [ICE_EEP2_GPIO_DIR2
] = 0x00,
1066 [ICE_EEP2_GPIO_MASK
] = 0xff, /* changed only for OUT operations */
1067 [ICE_EEP2_GPIO_MASK1
] = 0x00,
1068 [ICE_EEP2_GPIO_MASK2
] = 0xff,
1070 [ICE_EEP2_GPIO_STATE
] = 0x00, /* inputs */
1071 [ICE_EEP2_GPIO_STATE1
] = 0x7d, /* all 1, but GPIO_CPLD_RW
1072 and GPIO15 always zero */
1073 [ICE_EEP2_GPIO_STATE2
] = 0x00, /* inputs */
1077 struct snd_ice1712_card_info snd_vt1724_qtet_cards
[] = {
1079 .subvendor
= VT1724_SUBDEVICE_QTET
,
1080 .name
= "Infrasonic Quartet",
1082 .chip_init
= qtet_init
,
1083 .build_controls
= qtet_add_controls
,
1084 .eeprom_size
= sizeof(qtet_eeprom
),
1085 .eeprom_data
= qtet_eeprom
,
1087 { } /* terminator */