sound/ppc/snd_ps3_reg.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Audio support for PS3
   4  * Copyright (C) 2007 Sony Computer Entertainment Inc.
   5  * Copyright 2006, 2007 Sony Corporation
   6  * All rights reserved.
   7  */
   8
   9 /*
  10  * interrupt / configure registers
  11  */
  12
  13 #define PS3_AUDIO_INTR_0                 (0x00000100)
  14 #define PS3_AUDIO_INTR_EN_0              (0x00000140)
  15 #define PS3_AUDIO_CONFIG                 (0x00000200)
  16
  17 /*
  18  * DMAC registers
  19  * n:0..9
  20  */
  21 #define PS3_AUDIO_DMAC_REGBASE(x)         (0x0000210 + 0x20 * (x))
  22
  23 #define PS3_AUDIO_KICK(n)                 (PS3_AUDIO_DMAC_REGBASE(n) + 0x00)
  24 #define PS3_AUDIO_SOURCE(n)               (PS3_AUDIO_DMAC_REGBASE(n) + 0x04)
  25 #define PS3_AUDIO_DEST(n)                 (PS3_AUDIO_DMAC_REGBASE(n) + 0x08)
  26 #define PS3_AUDIO_DMASIZE(n)              (PS3_AUDIO_DMAC_REGBASE(n) + 0x0C)
  27
  28 /*
  29  * mute control
  30  */
  31 #define PS3_AUDIO_AX_MCTRL                (0x00004000)
  32 #define PS3_AUDIO_AX_ISBP                 (0x00004004)
  33 #define PS3_AUDIO_AX_AOBP                 (0x00004008)
  34 #define PS3_AUDIO_AX_IC                   (0x00004010)
  35 #define PS3_AUDIO_AX_IE                   (0x00004014)
  36 #define PS3_AUDIO_AX_IS                   (0x00004018)
  37
  38 /*
  39  * three wire serial
  40  * n:0..3
  41  */
  42 #define PS3_AUDIO_AO_MCTRL                (0x00006000)
  43 #define PS3_AUDIO_AO_3WMCTRL              (0x00006004)
  44
  45 #define PS3_AUDIO_AO_3WCTRL(n)            (0x00006200 + 0x200 * (n))
  46
  47 /*
  48  * S/PDIF
  49  * n:0..1
  50  * x:0..11
  51  * y:0..5
  52  */
  53 #define PS3_AUDIO_AO_SPD_REGBASE(n)       (0x00007200 + 0x200 * (n))
  54
  55 #define PS3_AUDIO_AO_SPDCTRL(n) \
  56         (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x00)
  57 #define PS3_AUDIO_AO_SPDUB(n, x) \
  58         (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x04 + 0x04 * (x))
  59 #define PS3_AUDIO_AO_SPDCS(n, y) \
  60         (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x34 + 0x04 * (y))
  61
  62
  63 /*
  64   PS3_AUDIO_INTR_0 register tells an interrupt handler which audio
  65   DMA channel triggered the interrupt.  The interrupt status for a channel
  66   can be cleared by writing a '1' to the corresponding bit.  A new interrupt
  67   cannot be generated until the previous interrupt has been cleared.
  68
  69   Note that the status reported by PS3_AUDIO_INTR_0 is independent of the
  70   value of PS3_AUDIO_INTR_EN_0.
  71
  72  31            24 23           16 15            8 7             0
  73  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
  74  |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_0
  75  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
  76 */
  77 #define PS3_AUDIO_INTR_0_CHAN(n)        (1 << ((n) * 2))
  78 #define PS3_AUDIO_INTR_0_CHAN9     PS3_AUDIO_INTR_0_CHAN(9)
  79 #define PS3_AUDIO_INTR_0_CHAN8     PS3_AUDIO_INTR_0_CHAN(8)
  80 #define PS3_AUDIO_INTR_0_CHAN7     PS3_AUDIO_INTR_0_CHAN(7)
  81 #define PS3_AUDIO_INTR_0_CHAN6     PS3_AUDIO_INTR_0_CHAN(6)
  82 #define PS3_AUDIO_INTR_0_CHAN5     PS3_AUDIO_INTR_0_CHAN(5)
  83 #define PS3_AUDIO_INTR_0_CHAN4     PS3_AUDIO_INTR_0_CHAN(4)
  84 #define PS3_AUDIO_INTR_0_CHAN3     PS3_AUDIO_INTR_0_CHAN(3)
  85 #define PS3_AUDIO_INTR_0_CHAN2     PS3_AUDIO_INTR_0_CHAN(2)
  86 #define PS3_AUDIO_INTR_0_CHAN1     PS3_AUDIO_INTR_0_CHAN(1)
  87 #define PS3_AUDIO_INTR_0_CHAN0     PS3_AUDIO_INTR_0_CHAN(0)
  88
  89 /*
  90   The PS3_AUDIO_INTR_EN_0 register specifies which DMA channels can generate
  91   an interrupt to the PU.  Each bit of PS3_AUDIO_INTR_EN_0 is ANDed with the
  92   corresponding bit in PS3_AUDIO_INTR_0.  The resulting bits are OR'd together
  93   to generate the Audio interrupt.
  94
  95  31            24 23           16 15            8 7             0
  96  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
  97  |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_EN_0
  98  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
  99
 100   Bit assignments are same as PS3_AUDIO_INTR_0
 101 */
 102
 103 /*
 104   PS3_AUDIO_CONFIG
 105   31            24 23           16 15            8 7             0
 106  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 107  |0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 C|0 0 0 0 0 0 0 0| CONFIG
 108  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 109
 110 */
 111
 112 /* The CLEAR field cancels all pending transfers, and stops any running DMA
 113    transfers.  Any interrupts associated with the canceled transfers
 114    will occur as if the transfer had finished.
 115    Since this bit is designed to recover from DMA related issues
 116    which are caused by unpredictable situations, it is preferred to wait
 117    for normal DMA transfer end without using this bit.
 118 */
 119 #define PS3_AUDIO_CONFIG_CLEAR          (1 << 8)  /* RWIVF */
 120
 121 /*
 122   PS3_AUDIO_AX_MCTRL: Audio Port Mute Control Register
 123
 124  31            24 23           16 15            8 7             0
 125  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 126  |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|A|A|0 0 0 0 0 0 0|S|S|A|A|A|A| AX_MCTRL
 127  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 128 */
 129
 130 /* 3 Wire Audio Serial Output Channel Mutes (0..3)  */
 131 #define PS3_AUDIO_AX_MCTRL_ASOMT(n)     (1 << (3 - (n)))  /* RWIVF */
 132 #define PS3_AUDIO_AX_MCTRL_ASO3MT       (1 << 0)          /* RWIVF */
 133 #define PS3_AUDIO_AX_MCTRL_ASO2MT       (1 << 1)          /* RWIVF */
 134 #define PS3_AUDIO_AX_MCTRL_ASO1MT       (1 << 2)          /* RWIVF */
 135 #define PS3_AUDIO_AX_MCTRL_ASO0MT       (1 << 3)          /* RWIVF */
 136
 137 /* S/PDIF mutes (0,1)*/
 138 #define PS3_AUDIO_AX_MCTRL_SPOMT(n)     (1 << (5 - (n)))  /* RWIVF */
 139 #define PS3_AUDIO_AX_MCTRL_SPO1MT       (1 << 4)          /* RWIVF */
 140 #define PS3_AUDIO_AX_MCTRL_SPO0MT       (1 << 5)          /* RWIVF */
 141
 142 /* All 3 Wire Serial Outputs Mute */
 143 #define PS3_AUDIO_AX_MCTRL_AASOMT       (1 << 13)         /* RWIVF */
 144
 145 /* All S/PDIF Mute */
 146 #define PS3_AUDIO_AX_MCTRL_ASPOMT       (1 << 14)         /* RWIVF */
 147
 148 /* All Audio Outputs Mute */
 149 #define PS3_AUDIO_AX_MCTRL_AAOMT        (1 << 15)         /* RWIVF */
 150
 151 /*
 152   S/PDIF Outputs Buffer Read/Write Pointer Register
 153
 154  31            24 23           16 15            8 7             0
 155  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 156  |0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B| AX_ISBP
 157  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 158
 159 */
 160 /*
 161  S/PDIF Output Channel Read Buffer Numbers
 162  Buffer number is  value of field.
 163  Indicates current read access buffer ID from Audio Data
 164  Transfer controller of S/PDIF Output
 165 */
 166
 167 #define PS3_AUDIO_AX_ISBP_SPOBRN_MASK(n) (0x7 << 4 * (1 - (n))) /* R-IUF */
 168 #define PS3_AUDIO_AX_ISBP_SPO1BRN_MASK          (0x7 << 0) /* R-IUF */
 169 #define PS3_AUDIO_AX_ISBP_SPO0BRN_MASK          (0x7 << 4) /* R-IUF */
 170
 171 /*
 172 S/PDIF Output Channel Buffer Write Numbers
 173 Indicates current write access buffer ID from bus master.
 174 */
 175 #define PS3_AUDIO_AX_ISBP_SPOBWN_MASK(n) (0x7 <<  4 * (5 - (n))) /* R-IUF */
 176 #define PS3_AUDIO_AX_ISBP_SPO1BWN_MASK          (0x7 << 16) /* R-IUF */
 177 #define PS3_AUDIO_AX_ISBP_SPO0BWN_MASK          (0x7 << 20) /* R-IUF */
 178
 179 /*
 180   3 Wire Audio Serial Outputs Buffer Read/Write
 181   Pointer Register
 182   Buffer number is  value of field
 183
 184  31            24 23           16 15            8 7             0
 185  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 186  |0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B| AX_AOBP
 187  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 188 */
 189
 190 /*
 191 3 Wire Audio Serial Output Channel Buffer Read Numbers
 192 Indicates current read access buffer Id from Audio Data Transfer
 193 Controller of 3 Wire Audio Serial Output Channels
 194 */
 195 #define PS3_AUDIO_AX_AOBP_ASOBRN_MASK(n) (0x7 << 4 * (3 - (n))) /* R-IUF */
 196
 197 #define PS3_AUDIO_AX_AOBP_ASO3BRN_MASK  (0x7 << 0) /* R-IUF */
 198 #define PS3_AUDIO_AX_AOBP_ASO2BRN_MASK  (0x7 << 4) /* R-IUF */
 199 #define PS3_AUDIO_AX_AOBP_ASO1BRN_MASK  (0x7 << 8) /* R-IUF */
 200 #define PS3_AUDIO_AX_AOBP_ASO0BRN_MASK  (0x7 << 12) /* R-IUF */
 201
 202 /*
 203 3 Wire Audio Serial Output Channel Buffer Write Numbers
 204 Indicates current write access buffer ID from bus master.
 205 */
 206 #define PS3_AUDIO_AX_AOBP_ASOBWN_MASK(n) (0x7 << 4 * (7 - (n))) /* R-IUF */
 207
 208 #define PS3_AUDIO_AX_AOBP_ASO3BWN_MASK        (0x7 << 16) /* R-IUF */
 209 #define PS3_AUDIO_AX_AOBP_ASO2BWN_MASK        (0x7 << 20) /* R-IUF */
 210 #define PS3_AUDIO_AX_AOBP_ASO1BWN_MASK        (0x7 << 24) /* R-IUF */
 211 #define PS3_AUDIO_AX_AOBP_ASO0BWN_MASK        (0x7 << 28) /* R-IUF */
 212
 213
 214
 215 /*
 216 Audio Port Interrupt Condition Register
 217 For the fields in this register, the following values apply:
 218 0 = Interrupt is generated every interrupt event.
 219 1 = Interrupt is generated every 2 interrupt events.
 220 2 = Interrupt is generated every 4 interrupt events.
 221 3 = Reserved
 222
 223
 224  31            24 23           16 15            8 7             0
 225  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 226  |0 0 0 0 0 0 0 0|0 0|SPO|0 0|SPO|0 0|AAS|0 0 0 0 0 0 0 0 0 0 0 0| AX_IC
 227  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 228 */
 229 /*
 230 All 3-Wire Audio Serial Outputs Interrupt Mode
 231 Configures the Interrupt and Signal Notification
 232 condition of all 3-wire Audio Serial Outputs.
 233 */
 234 #define PS3_AUDIO_AX_IC_AASOIMD_MASK          (0x3 << 12) /* RWIVF */
 235 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY1        (0x0 << 12) /* RWI-V */
 236 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2        (0x1 << 12) /* RW--V */
 237 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY4        (0x2 << 12) /* RW--V */
 238
 239 /*
 240 S/PDIF Output Channel Interrupt Modes
 241 Configures the Interrupt and signal Notification
 242 conditions of S/PDIF output channels.
 243 */
 244 #define PS3_AUDIO_AX_IC_SPO1IMD_MASK          (0x3 << 16) /* RWIVF */
 245 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY1        (0x0 << 16) /* RWI-V */
 246 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY2        (0x1 << 16) /* RW--V */
 247 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY4        (0x2 << 16) /* RW--V */
 248
 249 #define PS3_AUDIO_AX_IC_SPO0IMD_MASK          (0x3 << 20) /* RWIVF */
 250 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY1        (0x0 << 20) /* RWI-V */
 251 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY2        (0x1 << 20) /* RW--V */
 252 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY4        (0x2 << 20) /* RW--V */
 253
 254 /*
 255 Audio Port interrupt Enable Register
 256 Configures whether to enable or disable each Interrupt Generation.
 257
 258
 259  31            24 23           16 15            8 7             0
 260  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 261  |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IE
 262  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 263
 264 */
 265
 266 /*
 267 3 Wire Audio Serial Output Channel Buffer Underflow
 268 Interrupt Enables
 269 Select enable/disable of Buffer Underflow Interrupts for
 270 3-Wire Audio Serial Output Channels
 271 DISABLED=Interrupt generation disabled.
 272 */
 273 #define PS3_AUDIO_AX_IE_ASOBUIE(n)      (1 << (3 - (n))) /* RWIVF */
 274 #define PS3_AUDIO_AX_IE_ASO3BUIE        (1 << 0) /* RWIVF */
 275 #define PS3_AUDIO_AX_IE_ASO2BUIE        (1 << 1) /* RWIVF */
 276 #define PS3_AUDIO_AX_IE_ASO1BUIE        (1 << 2) /* RWIVF */
 277 #define PS3_AUDIO_AX_IE_ASO0BUIE        (1 << 3) /* RWIVF */
 278
 279 /* S/PDIF Output Channel Buffer Underflow Interrupt Enables */
 280
 281 #define PS3_AUDIO_AX_IE_SPOBUIE(n)      (1 << (7 - (n))) /* RWIVF */
 282 #define PS3_AUDIO_AX_IE_SPO1BUIE        (1 << 6) /* RWIVF */
 283 #define PS3_AUDIO_AX_IE_SPO0BUIE        (1 << 7) /* RWIVF */
 284
 285 /* S/PDIF Output Channel One Block Transfer Completion Interrupt Enables */
 286
 287 #define PS3_AUDIO_AX_IE_SPOBTCIE(n)     (1 << (11 - (n))) /* RWIVF */
 288 #define PS3_AUDIO_AX_IE_SPO1BTCIE       (1 << 10) /* RWIVF */
 289 #define PS3_AUDIO_AX_IE_SPO0BTCIE       (1 << 11) /* RWIVF */
 290
 291 /* 3-Wire Audio Serial Output Channel Buffer Empty Interrupt Enables */
 292
 293 #define PS3_AUDIO_AX_IE_ASOBEIE(n)      (1 << (19 - (n))) /* RWIVF */
 294 #define PS3_AUDIO_AX_IE_ASO3BEIE        (1 << 16) /* RWIVF */
 295 #define PS3_AUDIO_AX_IE_ASO2BEIE        (1 << 17) /* RWIVF */
 296 #define PS3_AUDIO_AX_IE_ASO1BEIE        (1 << 18) /* RWIVF */
 297 #define PS3_AUDIO_AX_IE_ASO0BEIE        (1 << 19) /* RWIVF */
 298
 299 /* S/PDIF Output Channel Buffer Empty Interrupt Enables */
 300
 301 #define PS3_AUDIO_AX_IE_SPOBEIE(n)      (1 << (23 - (n))) /* RWIVF */
 302 #define PS3_AUDIO_AX_IE_SPO1BEIE        (1 << 22) /* RWIVF */
 303 #define PS3_AUDIO_AX_IE_SPO0BEIE        (1 << 23) /* RWIVF */
 304
 305 /*
 306 Audio Port Interrupt Status Register
 307 Indicates Interrupt status, which interrupt has occurred, and can clear
 308 each interrupt in this register.
 309 Writing 1b to a field containing 1b clears field and de-asserts interrupt.
 310 Writing 0b to a field has no effect.
 311 Field vaules are the following:
 312 0 - Interrupt hasn't occurred.
 313 1 - Interrupt has occurred.
 314
 315
 316  31            24 23           16 15            8 7             0
 317  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 318  |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IS
 319  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 320
 321  Bit assignment are same as AX_IE
 322 */
 323
 324 /*
 325 Audio Output Master Control Register
 326 Configures Master Clock and other master Audio Output Settings
 327
 328
 329  31            24 23           16 15            8 7             0
 330  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 331  |0|SCKSE|0|SCKSE|  MR0  |  MR1  |MCL|MCL|0 0 0 0|0 0 0 0 0 0 0 0| AO_MCTRL
 332  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 333 */
 334
 335 /*
 336 MCLK Output Control
 337 Controls mclko[1] output.
 338 0 - Disable output (fixed at High)
 339 1 - Output clock produced by clock selected
 340 with scksel1 by mr1
 341 2 - Reserved
 342 3 - Reserved
 343 */
 344
 345 #define PS3_AUDIO_AO_MCTRL_MCLKC1_MASK          (0x3 << 12) /* RWIVF */
 346 #define PS3_AUDIO_AO_MCTRL_MCLKC1_DISABLED      (0x0 << 12) /* RWI-V */
 347 #define PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED       (0x1 << 12) /* RW--V */
 348 #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD2        (0x2 << 12) /* RW--V */
 349 #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD3        (0x3 << 12) /* RW--V */
 350
 351 /*
 352 MCLK Output Control
 353 Controls mclko[0] output.
 354 0 - Disable output (fixed at High)
 355 1 - Output clock produced by clock selected
 356 with SCKSEL0 by MR0
 357 2 - Reserved
 358 3 - Reserved
 359 */
 360 #define PS3_AUDIO_AO_MCTRL_MCLKC0_MASK          (0x3 << 14) /* RWIVF */
 361 #define PS3_AUDIO_AO_MCTRL_MCLKC0_DISABLED      (0x0 << 14) /* RWI-V */
 362 #define PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED       (0x1 << 14) /* RW--V */
 363 #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD2        (0x2 << 14) /* RW--V */
 364 #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD3        (0x3 << 14) /* RW--V */
 365 /*
 366 Master Clock Rate 1
 367 Sets the divide ration of Master Clock1 (clock output from
 368 mclko[1] for the input clock selected by scksel1.
 369 */
 370 #define PS3_AUDIO_AO_MCTRL_MR1_MASK     (0xf << 16)
 371 #define PS3_AUDIO_AO_MCTRL_MR1_DEFAULT  (0x0 << 16) /* RWI-V */
 372 /*
 373 Master Clock Rate 0
 374 Sets the divide ratio of Master Clock0 (clock output from
 375 mclko[0] for the input clock selected by scksel0).
 376 */
 377 #define PS3_AUDIO_AO_MCTRL_MR0_MASK     (0xf << 20) /* RWIVF */
 378 #define PS3_AUDIO_AO_MCTRL_MR0_DEFAULT  (0x0 << 20) /* RWI-V */
 379 /*
 380 System Clock Select 0/1
 381 Selects the system clock to be used as Master Clock 0/1
 382 Input the system clock that is appropriate for the sampling
 383 rate.
 384 */
 385 #define PS3_AUDIO_AO_MCTRL_SCKSEL1_MASK         (0x7 << 24) /* RWIVF */
 386 #define PS3_AUDIO_AO_MCTRL_SCKSEL1_DEFAULT      (0x2 << 24) /* RWI-V */
 387
 388 #define PS3_AUDIO_AO_MCTRL_SCKSEL0_MASK         (0x7 << 28) /* RWIVF */
 389 #define PS3_AUDIO_AO_MCTRL_SCKSEL0_DEFAULT      (0x2 << 28) /* RWI-V */
 390
 391
 392 /*
 393 3-Wire Audio Output Master Control Register
 394 Configures clock, 3-Wire Audio Serial Output Enable, and
 395 other 3-Wire Audio Serial Output Master Settings
 396
 397
 398  31            24 23           16 15            8 7             0
 399  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 400  |A|A|A|A|0 0 0|A| ASOSR |0 0 0 0|A|A|A|A|A|A|0|1|0 0 0 0 0 0 0 0| AO_3WMCTRL
 401  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 402 */
 403
 404
 405 /*
 406 LRCKO Polarity
 407 0 - Reserved
 408 1 - default
 409 */
 410 #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK           (1 << 8) /* RWIVF */
 411 #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK_DEFAULT   (1 << 8) /* RW--V */
 412
 413 /* LRCK Output Disable */
 414
 415 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD           (1 << 10) /* RWIVF */
 416 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_ENABLED   (0 << 10) /* RW--V */
 417 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_DISABLED  (1 << 10) /* RWI-V */
 418
 419 /* Bit Clock Output Disable */
 420
 421 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD           (1 << 11) /* RWIVF */
 422 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_ENABLED   (0 << 11) /* RW--V */
 423 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_DISABLED  (1 << 11) /* RWI-V */
 424
 425 /*
 426 3-Wire Audio Serial Output Channel 0-3 Operational
 427 Status.  Each bit becomes 1 after each 3-Wire Audio
 428 Serial Output Channel N is in action by setting 1 to
 429 asoen.
 430 Each bit becomes 0 after each 3-Wire Audio Serial Output
 431 Channel N is out of action by setting 0 to asoen.
 432 */
 433 #define PS3_AUDIO_AO_3WMCTRL_ASORUN(n)          (1 << (15 - (n))) /* R-IVF */
 434 #define PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(n)  (0 << (15 - (n))) /* R-I-V */
 435 #define PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(n)  (1 << (15 - (n))) /* R---V */
 436 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0            \
 437         PS3_AUDIO_AO_3WMCTRL_ASORUN(0)
 438 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_STOPPED    \
 439         PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(0)
 440 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_RUNNING    \
 441         PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(0)
 442 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1            \
 443         PS3_AUDIO_AO_3WMCTRL_ASORUN(1)
 444 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_STOPPED    \
 445         PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(1)
 446 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_RUNNING    \
 447         PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(1)
 448 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2            \
 449         PS3_AUDIO_AO_3WMCTRL_ASORUN(2)
 450 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_STOPPED    \
 451         PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(2)
 452 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_RUNNING    \
 453         PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(2)
 454 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3            \
 455         PS3_AUDIO_AO_3WMCTRL_ASORUN(3)
 456 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_STOPPED    \
 457         PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(3)
 458 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_RUNNING    \
 459         PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(3)
 460
 461 /*
 462 Sampling Rate
 463 Specifies the divide ratio of the bit clock (clock output
 464 from bclko) used by the 3-wire Audio Output Clock, which
 465 is applied to the master clock selected by mcksel.
 466 Data output is synchronized with this clock.
 467 */
 468 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_MASK         (0xf << 20) /* RWIVF */
 469 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2         (0x1 << 20) /* RWI-V */
 470 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV4         (0x2 << 20) /* RW--V */
 471 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV8         (0x4 << 20) /* RW--V */
 472 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV12        (0x6 << 20) /* RW--V */
 473
 474 /*
 475 Master Clock Select
 476 0 - Master Clock 0
 477 1 - Master Clock 1
 478 */
 479 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL          (1 << 24) /* RWIVF */
 480 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK0     (0 << 24) /* RWI-V */
 481 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK1     (1 << 24) /* RW--V */
 482
 483 /*
 484 Enables and disables 4ch 3-Wire Audio Serial Output
 485 operation.  Each Bit from 0 to 3 corresponds to an
 486 output channel, which means that each output channel
 487 can be enabled or disabled individually.  When
 488 multiple channels are enabled at the same time, output
 489 operations are performed in synchronization.
 490 Bit 0 - Output Channel 0 (SDOUT[0])
 491 Bit 1 - Output Channel 1 (SDOUT[1])
 492 Bit 2 - Output Channel 2 (SDOUT[2])
 493 Bit 3 - Output Channel 3 (SDOUT[3])
 494 */
 495 #define PS3_AUDIO_AO_3WMCTRL_ASOEN(n)           (1 << (31 - (n))) /* RWIVF */
 496 #define PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(n)  (0 << (31 - (n))) /* RWI-V */
 497 #define PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(n)   (1 << (31 - (n))) /* RW--V */
 498
 499 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0 \
 500         PS3_AUDIO_AO_3WMCTRL_ASOEN(0) /* RWIVF */
 501 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_DISABLED \
 502         PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(0) /* RWI-V */
 503 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_ENABLED \
 504         PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(0) /* RW--V */
 505 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0 \
 506         PS3_AUDIO_AO_3WMCTRL_ASOEN(1) /* RWIVF */
 507 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_DISABLED \
 508         PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(1) /* RWI-V */
 509 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_ENABLED \
 510         PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(1) /* RW--V */
 511 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0 \
 512         PS3_AUDIO_AO_3WMCTRL_ASOEN(2) /* RWIVF */
 513 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_DISABLED \
 514         PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(2) /* RWI-V */
 515 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_ENABLED \
 516         PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(2) /* RW--V */
 517 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0 \
 518         PS3_AUDIO_AO_3WMCTRL_ASOEN(3) /* RWIVF */
 519 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_DISABLED \
 520         PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(3) /* RWI-V */
 521 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_ENABLED \
 522         PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(3) /* RW--V */
 523
 524 /*
 525 3-Wire Audio Serial output Channel 0-3 Control Register
 526 Configures settings for 3-Wire Serial Audio Output Channel 0-3
 527
 528
 529  31            24 23           16 15            8 7             0
 530  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 531  |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|0 0 0 0|A|0|ASO|0 0 0|0|0|0|0|0| AO_3WCTRL
 532  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 533
 534 */
 535 /*
 536 Data Bit Mode
 537 Specifies the number of data bits
 538 0 - 16 bits
 539 1 - reserved
 540 2 - 20 bits
 541 3 - 24 bits
 542 */
 543 #define PS3_AUDIO_AO_3WCTRL_ASODB_MASK  (0x3 << 8) /* RWIVF */
 544 #define PS3_AUDIO_AO_3WCTRL_ASODB_16BIT (0x0 << 8) /* RWI-V */
 545 #define PS3_AUDIO_AO_3WCTRL_ASODB_RESVD (0x1 << 8) /* RWI-V */
 546 #define PS3_AUDIO_AO_3WCTRL_ASODB_20BIT (0x2 << 8) /* RW--V */
 547 #define PS3_AUDIO_AO_3WCTRL_ASODB_24BIT (0x3 << 8) /* RW--V */
 548 /*
 549 Data Format Mode
 550 Specifies the data format where (LSB side or MSB) the data(in 20 bit
 551 or 24 bit resolution mode) is put in a 32 bit field.
 552 0 - Data put on LSB side
 553 1 - Data put on MSB side
 554 */
 555 #define PS3_AUDIO_AO_3WCTRL_ASODF       (1 << 11) /* RWIVF */
 556 #define PS3_AUDIO_AO_3WCTRL_ASODF_LSB   (0 << 11) /* RWI-V */
 557 #define PS3_AUDIO_AO_3WCTRL_ASODF_MSB   (1 << 11) /* RW--V */
 558 /*
 559 Buffer Reset
 560 Performs buffer reset.  Writing 1 to this bit initializes the
 561 corresponding 3-Wire Audio Output buffers(both L and R).
 562 */
 563 #define PS3_AUDIO_AO_3WCTRL_ASOBRST             (1 << 16) /* CWIVF */
 564 #define PS3_AUDIO_AO_3WCTRL_ASOBRST_IDLE        (0 << 16) /* -WI-V */
 565 #define PS3_AUDIO_AO_3WCTRL_ASOBRST_RESET       (1 << 16) /* -W--T */
 566
 567 /*
 568 S/PDIF Audio Output Channel 0/1 Control Register
 569 Configures settings for S/PDIF Audio Output Channel 0/1.
 570
 571  31            24 23           16 15            8 7             0
 572  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 573  |S|0 0 0|S|0 0|S| SPOSR |0 0|SPO|0 0 0 0|S|0|SPO|0 0 0 0 0 0 0|S| AO_SPDCTRL
 574  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 575 */
 576 /*
 577 Buffer reset.  Writing 1 to this bit initializes the
 578 corresponding S/PDIF output buffer pointer.
 579 */
 580 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST            (1 << 0) /* CWIVF */
 581 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_IDLE       (0 << 0) /* -WI-V */
 582 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_RESET      (1 << 0) /* -W--T */
 583
 584 /*
 585 Data Bit Mode
 586 Specifies number of data bits
 587 0 - 16 bits
 588 1 - Reserved
 589 2 - 20 bits
 590 3 - 24 bits
 591 */
 592 #define PS3_AUDIO_AO_SPDCTRL_SPODB_MASK         (0x3 << 8) /* RWIVF */
 593 #define PS3_AUDIO_AO_SPDCTRL_SPODB_16BIT        (0x0 << 8) /* RWI-V */
 594 #define PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD        (0x1 << 8) /* RW--V */
 595 #define PS3_AUDIO_AO_SPDCTRL_SPODB_20BIT        (0x2 << 8) /* RW--V */
 596 #define PS3_AUDIO_AO_SPDCTRL_SPODB_24BIT        (0x3 << 8) /* RW--V */
 597 /*
 598 Data format Mode
 599 Specifies the data format, where (LSB side or MSB)
 600 the data(in 20 or 24 bit resolution) is put in the
 601 32 bit field.
 602 0 - LSB Side
 603 1 - MSB Side
 604 */
 605 #define PS3_AUDIO_AO_SPDCTRL_SPODF      (1 << 11) /* RWIVF */
 606 #define PS3_AUDIO_AO_SPDCTRL_SPODF_LSB  (0 << 11) /* RWI-V */
 607 #define PS3_AUDIO_AO_SPDCTRL_SPODF_MSB  (1 << 11) /* RW--V */
 608 /*
 609 Source Select
 610 Specifies the source of the S/PDIF output.  When 0, output
 611 operation is controlled by 3wen[0] of AO_3WMCTRL register.
 612 The SR must have the same setting as the a0_3wmctrl reg.
 613 0 - 3-Wire Audio OUT Ch0 Buffer
 614 1 - S/PDIF buffer
 615 */
 616 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_MASK         (0x3 << 16) /* RWIVF */
 617 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_3WEN         (0x0 << 16) /* RWI-V */
 618 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF        (0x1 << 16) /* RW--V */
 619 /*
 620 Sampling Rate
 621 Specifies the divide ratio of the bit clock (clock output
 622 from bclko) used by the S/PDIF Output Clock, which
 623 is applied to the master clock selected by mcksel.
 624 */
 625 #define PS3_AUDIO_AO_SPDCTRL_SPOSR              (0xf << 20) /* RWIVF */
 626 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2         (0x1 << 20) /* RWI-V */
 627 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV4         (0x2 << 20) /* RW--V */
 628 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV8         (0x4 << 20) /* RW--V */
 629 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV12        (0x6 << 20) /* RW--V */
 630 /*
 631 Master Clock Select
 632 0 - Master Clock 0
 633 1 - Master Clock 1
 634 */
 635 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL          (1 << 24) /* RWIVF */
 636 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK0     (0 << 24) /* RWI-V */
 637 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK1     (1 << 24) /* RW--V */
 638
 639 /*
 640 S/PDIF Output Channel Operational Status
 641 This bit becomes 1 after S/PDIF Output Channel is in
 642 action by setting 1 to spoen.  This bit becomes 0
 643 after S/PDIF Output Channel is out of action by setting
 644 0 to spoen.
 645 */
 646 #define PS3_AUDIO_AO_SPDCTRL_SPORUN             (1 << 27) /* R-IVF */
 647 #define PS3_AUDIO_AO_SPDCTRL_SPORUN_STOPPED     (0 << 27) /* R-I-V */
 648 #define PS3_AUDIO_AO_SPDCTRL_SPORUN_RUNNING     (1 << 27) /* R---V */
 649
 650 /*
 651 S/PDIF Audio Output Channel Output Enable
 652 Enables and disables output operation.  This bit is used
 653 only when sposs = 1
 654 */
 655 #define PS3_AUDIO_AO_SPDCTRL_SPOEN              (1 << 31) /* RWIVF */
 656 #define PS3_AUDIO_AO_SPDCTRL_SPOEN_DISABLED     (0 << 31) /* RWI-V */
 657 #define PS3_AUDIO_AO_SPDCTRL_SPOEN_ENABLED      (1 << 31) /* RW--V */
 658
 659 /*
 660 S/PDIF Audio Output Channel Channel Status
 661 Setting Registers.
 662 Configures channel status bit settings for each block
 663 (192 bits).
 664 Output is performed from the MSB(AO_SPDCS0 register bit 31).
 665 The same value is added for subframes within the same frame.
 666  31            24 23           16 15            8 7             0
 667  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 668  |                             SPOCS                             | AO_SPDCS
 669  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 670
 671 S/PDIF Audio Output Channel User Bit Setting
 672 Configures user bit settings for each block (384 bits).
 673 Output is performed from the MSB(ao_spdub0 register bit 31).
 674
 675
 676  31            24 23           16 15            8 7             0
 677  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 678  |                             SPOUB                             | AO_SPDUB
 679  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 680 */
 681 /*****************************************************************************
 682  *
 683  * DMAC register
 684  *
 685  *****************************************************************************/
 686 /*
 687 The PS3_AUDIO_KICK register is used to initiate a DMA transfer and monitor
 688 its status
 689
 690  31            24 23           16 15            8 7             0
 691  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 692  |0 0 0 0 0|STATU|0 0 0|  EVENT  |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|R| KICK
 693  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 694 */
 695 /*
 696 The REQUEST field is written to ACTIVE to initiate a DMA request when EVENT
 697 occurs.
 698 It will return to the DONE state when the request is completed.
 699 The registers for a DMA channel should only be written if REQUEST is IDLE.
 700 */
 701
 702 #define PS3_AUDIO_KICK_REQUEST                (1 << 0) /* RWIVF */
 703 #define PS3_AUDIO_KICK_REQUEST_IDLE           (0 << 0) /* RWI-V */
 704 #define PS3_AUDIO_KICK_REQUEST_ACTIVE         (1 << 0) /* -W--T */
 705
 706 /*
 707  *The EVENT field is used to set the event in which
 708  *the DMA request becomes active.
 709  */
 710 #define PS3_AUDIO_KICK_EVENT_MASK             (0x1f << 16) /* RWIVF */
 711 #define PS3_AUDIO_KICK_EVENT_ALWAYS           (0x00 << 16) /* RWI-V */
 712 #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_EMPTY (0x01 << 16) /* RW--V */
 713 #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_UNDERFLOW       (0x02 << 16) /* RW--V */
 714 #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_EMPTY           (0x03 << 16) /* RW--V */
 715 #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_UNDERFLOW       (0x04 << 16) /* RW--V */
 716 #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_EMPTY           (0x05 << 16) /* RW--V */
 717 #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_UNDERFLOW       (0x06 << 16) /* RW--V */
 718 #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_EMPTY           (0x07 << 16) /* RW--V */
 719 #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_UNDERFLOW       (0x08 << 16) /* RW--V */
 720 #define PS3_AUDIO_KICK_EVENT_SPDIF0_BLOCKTRANSFERCOMPLETE \
 721         (0x09 << 16) /* RW--V */
 722 #define PS3_AUDIO_KICK_EVENT_SPDIF0_UNDERFLOW           (0x0A << 16) /* RW--V */
 723 #define PS3_AUDIO_KICK_EVENT_SPDIF0_EMPTY               (0x0B << 16) /* RW--V */
 724 #define PS3_AUDIO_KICK_EVENT_SPDIF1_BLOCKTRANSFERCOMPLETE \
 725         (0x0C << 16) /* RW--V */
 726 #define PS3_AUDIO_KICK_EVENT_SPDIF1_UNDERFLOW           (0x0D << 16) /* RW--V */
 727 #define PS3_AUDIO_KICK_EVENT_SPDIF1_EMPTY               (0x0E << 16) /* RW--V */
 728
 729 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA(n) \
 730         ((0x13 + (n)) << 16) /* RW--V */
 731 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA0         (0x13 << 16) /* RW--V */
 732 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA1         (0x14 << 16) /* RW--V */
 733 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA2         (0x15 << 16) /* RW--V */
 734 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA3         (0x16 << 16) /* RW--V */
 735 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA4         (0x17 << 16) /* RW--V */
 736 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA5         (0x18 << 16) /* RW--V */
 737 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA6         (0x19 << 16) /* RW--V */
 738 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA7         (0x1A << 16) /* RW--V */
 739 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA8         (0x1B << 16) /* RW--V */
 740 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA9         (0x1C << 16) /* RW--V */
 741
 742 /*
 743 The STATUS field can be used to monitor the progress of a DMA request.
 744 DONE indicates the previous request has completed.
 745 EVENT indicates that the DMA engine is waiting for the EVENT to occur.
 746 PENDING indicates that the DMA engine has not started processing this
 747 request, but the EVENT has occurred.
 748 DMA indicates that the data transfer is in progress.
 749 NOTIFY indicates that the notifier signalling end of transfer is being written.
 750 CLEAR indicated that the previous transfer was cleared.
 751 ERROR indicates the previous transfer requested an unsupported
 752 source/destination combination.
 753 */
 754
 755 #define PS3_AUDIO_KICK_STATUS_MASK      (0x7 << 24) /* R-IVF */
 756 #define PS3_AUDIO_KICK_STATUS_DONE      (0x0 << 24) /* R-I-V */
 757 #define PS3_AUDIO_KICK_STATUS_EVENT     (0x1 << 24) /* R---V */
 758 #define PS3_AUDIO_KICK_STATUS_PENDING   (0x2 << 24) /* R---V */
 759 #define PS3_AUDIO_KICK_STATUS_DMA       (0x3 << 24) /* R---V */
 760 #define PS3_AUDIO_KICK_STATUS_NOTIFY    (0x4 << 24) /* R---V */
 761 #define PS3_AUDIO_KICK_STATUS_CLEAR     (0x5 << 24) /* R---V */
 762 #define PS3_AUDIO_KICK_STATUS_ERROR     (0x6 << 24) /* R---V */
 763
 764 /*
 765 The PS3_AUDIO_SOURCE register specifies the source address for transfers.
 766
 767
 768  31            24 23           16 15            8 7             0
 769  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 770  |                      START                      |0 0 0 0 0|TAR| SOURCE
 771  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 772 */
 773
 774 /*
 775 The Audio DMA engine uses 128-byte transfers, thus the address must be aligned
 776 to a 128 byte boundary.  The low seven bits are assumed to be 0.
 777 */
 778
 779 #define PS3_AUDIO_SOURCE_START_MASK     (0x01FFFFFF << 7) /* RWIUF */
 780
 781 /*
 782 The TARGET field specifies the memory space containing the source address.
 783 */
 784
 785 #define PS3_AUDIO_SOURCE_TARGET_MASK            (3 << 0) /* RWIVF */
 786 #define PS3_AUDIO_SOURCE_TARGET_SYSTEM_MEMORY   (2 << 0) /* RW--V */
 787
 788 /*
 789 The PS3_AUDIO_DEST register specifies the destination address for transfers.
 790
 791
 792  31            24 23           16 15            8 7             0
 793  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 794  |                      START                      |0 0 0 0 0|TAR| DEST
 795  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 796 */
 797
 798 /*
 799 The Audio DMA engine uses 128-byte transfers, thus the address must be aligned
 800 to a 128 byte boundary.  The low seven bits are assumed to be 0.
 801 */
 802
 803 #define PS3_AUDIO_DEST_START_MASK       (0x01FFFFFF << 7) /* RWIUF */
 804
 805 /*
 806 The TARGET field specifies the memory space containing the destination address
 807 AUDIOFIFO = Audio WriteData FIFO,
 808 */
 809
 810 #define PS3_AUDIO_DEST_TARGET_MASK              (3 << 0) /* RWIVF */
 811 #define PS3_AUDIO_DEST_TARGET_AUDIOFIFO         (1 << 0) /* RW--V */
 812
 813 /*
 814 PS3_AUDIO_DMASIZE specifies the number of 128-byte blocks + 1 to transfer.
 815 So a value of 0 means 128-bytes will get transferred.
 816
 817
 818  31            24 23           16 15            8 7             0
 819  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 820  |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|   BLOCKS    | DMASIZE
 821  +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
 822 */
 823
 824
 825 #define PS3_AUDIO_DMASIZE_BLOCKS_MASK   (0x7f << 0) /* RWIUF */
 826
 827 /*
 828  * source/destination address for internal fifos
 829  */
 830 #define PS3_AUDIO_AO_3W_LDATA(n)        (0x1000 + (0x100 * (n)))
 831 #define PS3_AUDIO_AO_3W_RDATA(n)        (0x1080 + (0x100 * (n)))
 832
 833 #define PS3_AUDIO_AO_SPD_DATA(n)        (0x2000 + (0x400 * (n)))
 834
 835
 836 /*
 837  * field attiribute
 838  *
 839  *      Read
 840  *        ' ' = Other Information
 841  *        '-' = Field is part of a write-only register
 842  *        'C' = Value read is always the same, constant value line follows (C)
 843  *        'R' = Value is read
 844  *
 845  *      Write
 846  *        ' ' = Other Information
 847  *        '-' = Must not be written (D), value ignored when written (R,A,F)
 848  *        'W' = Can be written
 849  *
 850  *      Internal State
 851  *        ' ' = Other Information
 852  *        '-' = No internal state
 853  *        'X' = Internal state, initial value is unknown
 854  *        'I' = Internal state, initial value is known and follows (I)
 855  *
 856  *      Declaration/Size
 857  *        ' ' = Other Information
 858  *        '-' = Does Not Apply
 859  *        'V' = Type is void
 860  *        'U' = Type is unsigned integer
 861  *        'S' = Type is signed integer
 862  *        'F' = Type is IEEE floating point
 863  *        '1' = Byte size (008)
 864  *        '2' = Short size (016)
 865  *        '3' = Three byte size (024)
 866  *        '4' = Word size (032)
 867  *        '8' = Double size (064)
 868  *
 869  *      Define Indicator
 870  *        ' ' = Other Information
 871  *        'D' = Device
 872  *        'M' = Memory
 873  *        'R' = Register
 874  *        'A' = Array of Registers
 875  *        'F' = Field
 876  *        'V' = Value
 877  *        'T' = Task
 878  */
 879