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Merge tag 'powerpc-5.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[linux/fpc-iii.git] / sound / soc / amd / include / acp_2_2_enum.h
blobf3577c851086b0b977d66e72da48bc8165315bee
1 /*
2 * ACP_2_2 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef ACP_2_2_ENUM_H
25 #define ACP_2_2_ENUM_H
26
27 typedef enum DebugBlockId {
28 DBG_BLOCK_ID_RESERVED = 0x0,
29 DBG_BLOCK_ID_DBG = 0x1,
30 DBG_BLOCK_ID_VMC = 0x2,
31 DBG_BLOCK_ID_PDMA = 0x3,
32 DBG_BLOCK_ID_CG = 0x4,
33 DBG_BLOCK_ID_SRBM = 0x5,
34 DBG_BLOCK_ID_GRBM = 0x6,
35 DBG_BLOCK_ID_RLC = 0x7,
36 DBG_BLOCK_ID_CSC = 0x8,
37 DBG_BLOCK_ID_SEM = 0x9,
38 DBG_BLOCK_ID_IH = 0xa,
39 DBG_BLOCK_ID_SC = 0xb,
40 DBG_BLOCK_ID_SQ = 0xc,
41 DBG_BLOCK_ID_UVDU = 0xd,
42 DBG_BLOCK_ID_SQA = 0xe,
43 DBG_BLOCK_ID_SDMA0 = 0xf,
44 DBG_BLOCK_ID_SDMA1 = 0x10,
45 DBG_BLOCK_ID_SPIM = 0x11,
46 DBG_BLOCK_ID_GDS = 0x12,
47 DBG_BLOCK_ID_VC0 = 0x13,
48 DBG_BLOCK_ID_VC1 = 0x14,
49 DBG_BLOCK_ID_PA0 = 0x15,
50 DBG_BLOCK_ID_PA1 = 0x16,
51 DBG_BLOCK_ID_CP0 = 0x17,
52 DBG_BLOCK_ID_CP1 = 0x18,
53 DBG_BLOCK_ID_CP2 = 0x19,
54 DBG_BLOCK_ID_XBR = 0x1a,
55 DBG_BLOCK_ID_UVDM = 0x1b,
56 DBG_BLOCK_ID_VGT0 = 0x1c,
57 DBG_BLOCK_ID_VGT1 = 0x1d,
58 DBG_BLOCK_ID_IA = 0x1e,
59 DBG_BLOCK_ID_SXM0 = 0x1f,
60 DBG_BLOCK_ID_SXM1 = 0x20,
61 DBG_BLOCK_ID_SCT0 = 0x21,
62 DBG_BLOCK_ID_SCT1 = 0x22,
63 DBG_BLOCK_ID_SPM0 = 0x23,
64 DBG_BLOCK_ID_SPM1 = 0x24,
65 DBG_BLOCK_ID_UNUSED0 = 0x25,
66 DBG_BLOCK_ID_UNUSED1 = 0x26,
67 DBG_BLOCK_ID_TCAA = 0x27,
68 DBG_BLOCK_ID_TCAB = 0x28,
69 DBG_BLOCK_ID_TCCA = 0x29,
70 DBG_BLOCK_ID_TCCB = 0x2a,
71 DBG_BLOCK_ID_MCC0 = 0x2b,
72 DBG_BLOCK_ID_MCC1 = 0x2c,
73 DBG_BLOCK_ID_MCC2 = 0x2d,
74 DBG_BLOCK_ID_MCC3 = 0x2e,
75 DBG_BLOCK_ID_SXS0 = 0x2f,
76 DBG_BLOCK_ID_SXS1 = 0x30,
77 DBG_BLOCK_ID_SXS2 = 0x31,
78 DBG_BLOCK_ID_SXS3 = 0x32,
79 DBG_BLOCK_ID_SXS4 = 0x33,
80 DBG_BLOCK_ID_SXS5 = 0x34,
81 DBG_BLOCK_ID_SXS6 = 0x35,
82 DBG_BLOCK_ID_SXS7 = 0x36,
83 DBG_BLOCK_ID_SXS8 = 0x37,
84 DBG_BLOCK_ID_SXS9 = 0x38,
85 DBG_BLOCK_ID_BCI0 = 0x39,
86 DBG_BLOCK_ID_BCI1 = 0x3a,
87 DBG_BLOCK_ID_BCI2 = 0x3b,
88 DBG_BLOCK_ID_BCI3 = 0x3c,
89 DBG_BLOCK_ID_MCB = 0x3d,
90 DBG_BLOCK_ID_UNUSED6 = 0x3e,
91 DBG_BLOCK_ID_SQA00 = 0x3f,
92 DBG_BLOCK_ID_SQA01 = 0x40,
93 DBG_BLOCK_ID_SQA02 = 0x41,
94 DBG_BLOCK_ID_SQA10 = 0x42,
95 DBG_BLOCK_ID_SQA11 = 0x43,
96 DBG_BLOCK_ID_SQA12 = 0x44,
97 DBG_BLOCK_ID_UNUSED7 = 0x45,
98 DBG_BLOCK_ID_UNUSED8 = 0x46,
99 DBG_BLOCK_ID_SQB00 = 0x47,
100 DBG_BLOCK_ID_SQB01 = 0x48,
101 DBG_BLOCK_ID_SQB10 = 0x49,
102 DBG_BLOCK_ID_SQB11 = 0x4a,
103 DBG_BLOCK_ID_SQ00 = 0x4b,
104 DBG_BLOCK_ID_SQ01 = 0x4c,
105 DBG_BLOCK_ID_SQ10 = 0x4d,
106 DBG_BLOCK_ID_SQ11 = 0x4e,
107 DBG_BLOCK_ID_CB00 = 0x4f,
108 DBG_BLOCK_ID_CB01 = 0x50,
109 DBG_BLOCK_ID_CB02 = 0x51,
110 DBG_BLOCK_ID_CB03 = 0x52,
111 DBG_BLOCK_ID_CB04 = 0x53,
112 DBG_BLOCK_ID_UNUSED9 = 0x54,
113 DBG_BLOCK_ID_UNUSED10 = 0x55,
114 DBG_BLOCK_ID_UNUSED11 = 0x56,
115 DBG_BLOCK_ID_CB10 = 0x57,
116 DBG_BLOCK_ID_CB11 = 0x58,
117 DBG_BLOCK_ID_CB12 = 0x59,
118 DBG_BLOCK_ID_CB13 = 0x5a,
119 DBG_BLOCK_ID_CB14 = 0x5b,
120 DBG_BLOCK_ID_UNUSED12 = 0x5c,
121 DBG_BLOCK_ID_UNUSED13 = 0x5d,
122 DBG_BLOCK_ID_UNUSED14 = 0x5e,
123 DBG_BLOCK_ID_TCP0 = 0x5f,
124 DBG_BLOCK_ID_TCP1 = 0x60,
125 DBG_BLOCK_ID_TCP2 = 0x61,
126 DBG_BLOCK_ID_TCP3 = 0x62,
127 DBG_BLOCK_ID_TCP4 = 0x63,
128 DBG_BLOCK_ID_TCP5 = 0x64,
129 DBG_BLOCK_ID_TCP6 = 0x65,
130 DBG_BLOCK_ID_TCP7 = 0x66,
131 DBG_BLOCK_ID_TCP8 = 0x67,
132 DBG_BLOCK_ID_TCP9 = 0x68,
133 DBG_BLOCK_ID_TCP10 = 0x69,
134 DBG_BLOCK_ID_TCP11 = 0x6a,
135 DBG_BLOCK_ID_TCP12 = 0x6b,
136 DBG_BLOCK_ID_TCP13 = 0x6c,
137 DBG_BLOCK_ID_TCP14 = 0x6d,
138 DBG_BLOCK_ID_TCP15 = 0x6e,
139 DBG_BLOCK_ID_TCP16 = 0x6f,
140 DBG_BLOCK_ID_TCP17 = 0x70,
141 DBG_BLOCK_ID_TCP18 = 0x71,
142 DBG_BLOCK_ID_TCP19 = 0x72,
143 DBG_BLOCK_ID_TCP20 = 0x73,
144 DBG_BLOCK_ID_TCP21 = 0x74,
145 DBG_BLOCK_ID_TCP22 = 0x75,
146 DBG_BLOCK_ID_TCP23 = 0x76,
147 DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
148 DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
149 DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
150 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
151 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
152 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
153 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
154 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
155 DBG_BLOCK_ID_DB00 = 0x7f,
156 DBG_BLOCK_ID_DB01 = 0x80,
157 DBG_BLOCK_ID_DB02 = 0x81,
158 DBG_BLOCK_ID_DB03 = 0x82,
159 DBG_BLOCK_ID_DB04 = 0x83,
160 DBG_BLOCK_ID_UNUSED15 = 0x84,
161 DBG_BLOCK_ID_UNUSED16 = 0x85,
162 DBG_BLOCK_ID_UNUSED17 = 0x86,
163 DBG_BLOCK_ID_DB10 = 0x87,
164 DBG_BLOCK_ID_DB11 = 0x88,
165 DBG_BLOCK_ID_DB12 = 0x89,
166 DBG_BLOCK_ID_DB13 = 0x8a,
167 DBG_BLOCK_ID_DB14 = 0x8b,
168 DBG_BLOCK_ID_UNUSED18 = 0x8c,
169 DBG_BLOCK_ID_UNUSED19 = 0x8d,
170 DBG_BLOCK_ID_UNUSED20 = 0x8e,
171 DBG_BLOCK_ID_TCC0 = 0x8f,
172 DBG_BLOCK_ID_TCC1 = 0x90,
173 DBG_BLOCK_ID_TCC2 = 0x91,
174 DBG_BLOCK_ID_TCC3 = 0x92,
175 DBG_BLOCK_ID_TCC4 = 0x93,
176 DBG_BLOCK_ID_TCC5 = 0x94,
177 DBG_BLOCK_ID_TCC6 = 0x95,
178 DBG_BLOCK_ID_TCC7 = 0x96,
179 DBG_BLOCK_ID_SPS00 = 0x97,
180 DBG_BLOCK_ID_SPS01 = 0x98,
181 DBG_BLOCK_ID_SPS02 = 0x99,
182 DBG_BLOCK_ID_SPS10 = 0x9a,
183 DBG_BLOCK_ID_SPS11 = 0x9b,
184 DBG_BLOCK_ID_SPS12 = 0x9c,
185 DBG_BLOCK_ID_UNUSED21 = 0x9d,
186 DBG_BLOCK_ID_UNUSED22 = 0x9e,
187 DBG_BLOCK_ID_TA00 = 0x9f,
188 DBG_BLOCK_ID_TA01 = 0xa0,
189 DBG_BLOCK_ID_TA02 = 0xa1,
190 DBG_BLOCK_ID_TA03 = 0xa2,
191 DBG_BLOCK_ID_TA04 = 0xa3,
192 DBG_BLOCK_ID_TA05 = 0xa4,
193 DBG_BLOCK_ID_TA06 = 0xa5,
194 DBG_BLOCK_ID_TA07 = 0xa6,
195 DBG_BLOCK_ID_TA08 = 0xa7,
196 DBG_BLOCK_ID_TA09 = 0xa8,
197 DBG_BLOCK_ID_TA0A = 0xa9,
198 DBG_BLOCK_ID_TA0B = 0xaa,
199 DBG_BLOCK_ID_UNUSED23 = 0xab,
200 DBG_BLOCK_ID_UNUSED24 = 0xac,
201 DBG_BLOCK_ID_UNUSED25 = 0xad,
202 DBG_BLOCK_ID_UNUSED26 = 0xae,
203 DBG_BLOCK_ID_TA10 = 0xaf,
204 DBG_BLOCK_ID_TA11 = 0xb0,
205 DBG_BLOCK_ID_TA12 = 0xb1,
206 DBG_BLOCK_ID_TA13 = 0xb2,
207 DBG_BLOCK_ID_TA14 = 0xb3,
208 DBG_BLOCK_ID_TA15 = 0xb4,
209 DBG_BLOCK_ID_TA16 = 0xb5,
210 DBG_BLOCK_ID_TA17 = 0xb6,
211 DBG_BLOCK_ID_TA18 = 0xb7,
212 DBG_BLOCK_ID_TA19 = 0xb8,
213 DBG_BLOCK_ID_TA1A = 0xb9,
214 DBG_BLOCK_ID_TA1B = 0xba,
215 DBG_BLOCK_ID_UNUSED27 = 0xbb,
216 DBG_BLOCK_ID_UNUSED28 = 0xbc,
217 DBG_BLOCK_ID_UNUSED29 = 0xbd,
218 DBG_BLOCK_ID_UNUSED30 = 0xbe,
219 DBG_BLOCK_ID_TD00 = 0xbf,
220 DBG_BLOCK_ID_TD01 = 0xc0,
221 DBG_BLOCK_ID_TD02 = 0xc1,
222 DBG_BLOCK_ID_TD03 = 0xc2,
223 DBG_BLOCK_ID_TD04 = 0xc3,
224 DBG_BLOCK_ID_TD05 = 0xc4,
225 DBG_BLOCK_ID_TD06 = 0xc5,
226 DBG_BLOCK_ID_TD07 = 0xc6,
227 DBG_BLOCK_ID_TD08 = 0xc7,
228 DBG_BLOCK_ID_TD09 = 0xc8,
229 DBG_BLOCK_ID_TD0A = 0xc9,
230 DBG_BLOCK_ID_TD0B = 0xca,
231 DBG_BLOCK_ID_UNUSED31 = 0xcb,
232 DBG_BLOCK_ID_UNUSED32 = 0xcc,
233 DBG_BLOCK_ID_UNUSED33 = 0xcd,
234 DBG_BLOCK_ID_UNUSED34 = 0xce,
235 DBG_BLOCK_ID_TD10 = 0xcf,
236 DBG_BLOCK_ID_TD11 = 0xd0,
237 DBG_BLOCK_ID_TD12 = 0xd1,
238 DBG_BLOCK_ID_TD13 = 0xd2,
239 DBG_BLOCK_ID_TD14 = 0xd3,
240 DBG_BLOCK_ID_TD15 = 0xd4,
241 DBG_BLOCK_ID_TD16 = 0xd5,
242 DBG_BLOCK_ID_TD17 = 0xd6,
243 DBG_BLOCK_ID_TD18 = 0xd7,
244 DBG_BLOCK_ID_TD19 = 0xd8,
245 DBG_BLOCK_ID_TD1A = 0xd9,
246 DBG_BLOCK_ID_TD1B = 0xda,
247 DBG_BLOCK_ID_UNUSED35 = 0xdb,
248 DBG_BLOCK_ID_UNUSED36 = 0xdc,
249 DBG_BLOCK_ID_UNUSED37 = 0xdd,
250 DBG_BLOCK_ID_UNUSED38 = 0xde,
251 DBG_BLOCK_ID_LDS00 = 0xdf,
252 DBG_BLOCK_ID_LDS01 = 0xe0,
253 DBG_BLOCK_ID_LDS02 = 0xe1,
254 DBG_BLOCK_ID_LDS03 = 0xe2,
255 DBG_BLOCK_ID_LDS04 = 0xe3,
256 DBG_BLOCK_ID_LDS05 = 0xe4,
257 DBG_BLOCK_ID_LDS06 = 0xe5,
258 DBG_BLOCK_ID_LDS07 = 0xe6,
259 DBG_BLOCK_ID_LDS08 = 0xe7,
260 DBG_BLOCK_ID_LDS09 = 0xe8,
261 DBG_BLOCK_ID_LDS0A = 0xe9,
262 DBG_BLOCK_ID_LDS0B = 0xea,
263 DBG_BLOCK_ID_UNUSED39 = 0xeb,
264 DBG_BLOCK_ID_UNUSED40 = 0xec,
265 DBG_BLOCK_ID_UNUSED41 = 0xed,
266 DBG_BLOCK_ID_UNUSED42 = 0xee,
267 DBG_BLOCK_ID_LDS10 = 0xef,
268 DBG_BLOCK_ID_LDS11 = 0xf0,
269 DBG_BLOCK_ID_LDS12 = 0xf1,
270 DBG_BLOCK_ID_LDS13 = 0xf2,
271 DBG_BLOCK_ID_LDS14 = 0xf3,
272 DBG_BLOCK_ID_LDS15 = 0xf4,
273 DBG_BLOCK_ID_LDS16 = 0xf5,
274 DBG_BLOCK_ID_LDS17 = 0xf6,
275 DBG_BLOCK_ID_LDS18 = 0xf7,
276 DBG_BLOCK_ID_LDS19 = 0xf8,
277 DBG_BLOCK_ID_LDS1A = 0xf9,
278 DBG_BLOCK_ID_LDS1B = 0xfa,
279 DBG_BLOCK_ID_UNUSED43 = 0xfb,
280 DBG_BLOCK_ID_UNUSED44 = 0xfc,
281 DBG_BLOCK_ID_UNUSED45 = 0xfd,
282 DBG_BLOCK_ID_UNUSED46 = 0xfe,
283 } DebugBlockId;
284 typedef enum DebugBlockId_BY2 {
285 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
286 DBG_BLOCK_ID_VMC_BY2 = 0x1,
287 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
288 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
289 DBG_BLOCK_ID_CSC_BY2 = 0x4,
290 DBG_BLOCK_ID_IH_BY2 = 0x5,
291 DBG_BLOCK_ID_SQ_BY2 = 0x6,
292 DBG_BLOCK_ID_UVD_BY2 = 0x7,
293 DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
294 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
295 DBG_BLOCK_ID_VC0_BY2 = 0xa,
296 DBG_BLOCK_ID_PA_BY2 = 0xb,
297 DBG_BLOCK_ID_CP0_BY2 = 0xc,
298 DBG_BLOCK_ID_CP2_BY2 = 0xd,
299 DBG_BLOCK_ID_PC0_BY2 = 0xe,
300 DBG_BLOCK_ID_BCI0_BY2 = 0xf,
301 DBG_BLOCK_ID_SXM0_BY2 = 0x10,
302 DBG_BLOCK_ID_SCT0_BY2 = 0x11,
303 DBG_BLOCK_ID_SPM0_BY2 = 0x12,
304 DBG_BLOCK_ID_BCI2_BY2 = 0x13,
305 DBG_BLOCK_ID_TCA_BY2 = 0x14,
306 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
307 DBG_BLOCK_ID_MCC_BY2 = 0x16,
308 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
309 DBG_BLOCK_ID_MCD_BY2 = 0x18,
310 DBG_BLOCK_ID_MCD2_BY2 = 0x19,
311 DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
312 DBG_BLOCK_ID_MCB_BY2 = 0x1b,
313 DBG_BLOCK_ID_SQA_BY2 = 0x1c,
314 DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
315 DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
316 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
317 DBG_BLOCK_ID_SQB_BY2 = 0x20,
318 DBG_BLOCK_ID_SQB10_BY2 = 0x21,
319 DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
320 DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
321 DBG_BLOCK_ID_CB_BY2 = 0x24,
322 DBG_BLOCK_ID_CB02_BY2 = 0x25,
323 DBG_BLOCK_ID_CB10_BY2 = 0x26,
324 DBG_BLOCK_ID_CB12_BY2 = 0x27,
325 DBG_BLOCK_ID_SXS_BY2 = 0x28,
326 DBG_BLOCK_ID_SXS2_BY2 = 0x29,
327 DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
328 DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
329 DBG_BLOCK_ID_DB_BY2 = 0x2c,
330 DBG_BLOCK_ID_DB02_BY2 = 0x2d,
331 DBG_BLOCK_ID_DB10_BY2 = 0x2e,
332 DBG_BLOCK_ID_DB12_BY2 = 0x2f,
333 DBG_BLOCK_ID_TCP_BY2 = 0x30,
334 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
335 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
336 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
337 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
338 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
339 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
340 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
341 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
342 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
343 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
344 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
345 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
346 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
347 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
348 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
349 DBG_BLOCK_ID_TCC_BY2 = 0x40,
350 DBG_BLOCK_ID_TCC2_BY2 = 0x41,
351 DBG_BLOCK_ID_TCC4_BY2 = 0x42,
352 DBG_BLOCK_ID_TCC6_BY2 = 0x43,
353 DBG_BLOCK_ID_SPS_BY2 = 0x44,
354 DBG_BLOCK_ID_SPS02_BY2 = 0x45,
355 DBG_BLOCK_ID_SPS11_BY2 = 0x46,
356 DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
357 DBG_BLOCK_ID_TA_BY2 = 0x48,
358 DBG_BLOCK_ID_TA02_BY2 = 0x49,
359 DBG_BLOCK_ID_TA04_BY2 = 0x4a,
360 DBG_BLOCK_ID_TA06_BY2 = 0x4b,
361 DBG_BLOCK_ID_TA08_BY2 = 0x4c,
362 DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
363 DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
364 DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
365 DBG_BLOCK_ID_TA10_BY2 = 0x50,
366 DBG_BLOCK_ID_TA12_BY2 = 0x51,
367 DBG_BLOCK_ID_TA14_BY2 = 0x52,
368 DBG_BLOCK_ID_TA16_BY2 = 0x53,
369 DBG_BLOCK_ID_TA18_BY2 = 0x54,
370 DBG_BLOCK_ID_TA1A_BY2 = 0x55,
371 DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
372 DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
373 DBG_BLOCK_ID_TD_BY2 = 0x58,
374 DBG_BLOCK_ID_TD02_BY2 = 0x59,
375 DBG_BLOCK_ID_TD04_BY2 = 0x5a,
376 DBG_BLOCK_ID_TD06_BY2 = 0x5b,
377 DBG_BLOCK_ID_TD08_BY2 = 0x5c,
378 DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
379 DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
380 DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
381 DBG_BLOCK_ID_TD10_BY2 = 0x60,
382 DBG_BLOCK_ID_TD12_BY2 = 0x61,
383 DBG_BLOCK_ID_TD14_BY2 = 0x62,
384 DBG_BLOCK_ID_TD16_BY2 = 0x63,
385 DBG_BLOCK_ID_TD18_BY2 = 0x64,
386 DBG_BLOCK_ID_TD1A_BY2 = 0x65,
387 DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
388 DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
389 DBG_BLOCK_ID_LDS_BY2 = 0x68,
390 DBG_BLOCK_ID_LDS02_BY2 = 0x69,
391 DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
392 DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
393 DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
394 DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
395 DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
396 DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
397 DBG_BLOCK_ID_LDS10_BY2 = 0x70,
398 DBG_BLOCK_ID_LDS12_BY2 = 0x71,
399 DBG_BLOCK_ID_LDS14_BY2 = 0x72,
400 DBG_BLOCK_ID_LDS16_BY2 = 0x73,
401 DBG_BLOCK_ID_LDS18_BY2 = 0x74,
402 DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
403 DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
404 DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
405 } DebugBlockId_BY2;
406 typedef enum DebugBlockId_BY4 {
407 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
408 DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
409 DBG_BLOCK_ID_CSC_BY4 = 0x2,
410 DBG_BLOCK_ID_SQ_BY4 = 0x3,
411 DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
412 DBG_BLOCK_ID_VC0_BY4 = 0x5,
413 DBG_BLOCK_ID_CP0_BY4 = 0x6,
414 DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
415 DBG_BLOCK_ID_SXM0_BY4 = 0x8,
416 DBG_BLOCK_ID_SPM0_BY4 = 0x9,
417 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
418 DBG_BLOCK_ID_MCC_BY4 = 0xb,
419 DBG_BLOCK_ID_MCD_BY4 = 0xc,
420 DBG_BLOCK_ID_MCD4_BY4 = 0xd,
421 DBG_BLOCK_ID_SQA_BY4 = 0xe,
422 DBG_BLOCK_ID_SQA11_BY4 = 0xf,
423 DBG_BLOCK_ID_SQB_BY4 = 0x10,
424 DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
425 DBG_BLOCK_ID_CB_BY4 = 0x12,
426 DBG_BLOCK_ID_CB10_BY4 = 0x13,
427 DBG_BLOCK_ID_SXS_BY4 = 0x14,
428 DBG_BLOCK_ID_SXS4_BY4 = 0x15,
429 DBG_BLOCK_ID_DB_BY4 = 0x16,
430 DBG_BLOCK_ID_DB10_BY4 = 0x17,
431 DBG_BLOCK_ID_TCP_BY4 = 0x18,
432 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
433 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
434 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
435 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
436 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
437 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
438 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
439 DBG_BLOCK_ID_TCC_BY4 = 0x20,
440 DBG_BLOCK_ID_TCC4_BY4 = 0x21,
441 DBG_BLOCK_ID_SPS_BY4 = 0x22,
442 DBG_BLOCK_ID_SPS11_BY4 = 0x23,
443 DBG_BLOCK_ID_TA_BY4 = 0x24,
444 DBG_BLOCK_ID_TA04_BY4 = 0x25,
445 DBG_BLOCK_ID_TA08_BY4 = 0x26,
446 DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
447 DBG_BLOCK_ID_TA10_BY4 = 0x28,
448 DBG_BLOCK_ID_TA14_BY4 = 0x29,
449 DBG_BLOCK_ID_TA18_BY4 = 0x2a,
450 DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
451 DBG_BLOCK_ID_TD_BY4 = 0x2c,
452 DBG_BLOCK_ID_TD04_BY4 = 0x2d,
453 DBG_BLOCK_ID_TD08_BY4 = 0x2e,
454 DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
455 DBG_BLOCK_ID_TD10_BY4 = 0x30,
456 DBG_BLOCK_ID_TD14_BY4 = 0x31,
457 DBG_BLOCK_ID_TD18_BY4 = 0x32,
458 DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
459 DBG_BLOCK_ID_LDS_BY4 = 0x34,
460 DBG_BLOCK_ID_LDS04_BY4 = 0x35,
461 DBG_BLOCK_ID_LDS08_BY4 = 0x36,
462 DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
463 DBG_BLOCK_ID_LDS10_BY4 = 0x38,
464 DBG_BLOCK_ID_LDS14_BY4 = 0x39,
465 DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
466 DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
467 } DebugBlockId_BY4;
468 typedef enum DebugBlockId_BY8 {
469 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
470 DBG_BLOCK_ID_CSC_BY8 = 0x1,
471 DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
472 DBG_BLOCK_ID_CP0_BY8 = 0x3,
473 DBG_BLOCK_ID_SXM0_BY8 = 0x4,
474 DBG_BLOCK_ID_TCA_BY8 = 0x5,
475 DBG_BLOCK_ID_MCD_BY8 = 0x6,
476 DBG_BLOCK_ID_SQA_BY8 = 0x7,
477 DBG_BLOCK_ID_SQB_BY8 = 0x8,
478 DBG_BLOCK_ID_CB_BY8 = 0x9,
479 DBG_BLOCK_ID_SXS_BY8 = 0xa,
480 DBG_BLOCK_ID_DB_BY8 = 0xb,
481 DBG_BLOCK_ID_TCP_BY8 = 0xc,
482 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
483 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
484 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
485 DBG_BLOCK_ID_TCC_BY8 = 0x10,
486 DBG_BLOCK_ID_SPS_BY8 = 0x11,
487 DBG_BLOCK_ID_TA_BY8 = 0x12,
488 DBG_BLOCK_ID_TA08_BY8 = 0x13,
489 DBG_BLOCK_ID_TA10_BY8 = 0x14,
490 DBG_BLOCK_ID_TA18_BY8 = 0x15,
491 DBG_BLOCK_ID_TD_BY8 = 0x16,
492 DBG_BLOCK_ID_TD08_BY8 = 0x17,
493 DBG_BLOCK_ID_TD10_BY8 = 0x18,
494 DBG_BLOCK_ID_TD18_BY8 = 0x19,
495 DBG_BLOCK_ID_LDS_BY8 = 0x1a,
496 DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
497 DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
498 DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
499 } DebugBlockId_BY8;
500 typedef enum DebugBlockId_BY16 {
501 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
502 DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
503 DBG_BLOCK_ID_SXM_BY16 = 0x2,
504 DBG_BLOCK_ID_MCD_BY16 = 0x3,
505 DBG_BLOCK_ID_SQB_BY16 = 0x4,
506 DBG_BLOCK_ID_SXS_BY16 = 0x5,
507 DBG_BLOCK_ID_TCP_BY16 = 0x6,
508 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
509 DBG_BLOCK_ID_TCC_BY16 = 0x8,
510 DBG_BLOCK_ID_TA_BY16 = 0x9,
511 DBG_BLOCK_ID_TA10_BY16 = 0xa,
512 DBG_BLOCK_ID_TD_BY16 = 0xb,
513 DBG_BLOCK_ID_TD10_BY16 = 0xc,
514 DBG_BLOCK_ID_LDS_BY16 = 0xd,
515 DBG_BLOCK_ID_LDS10_BY16 = 0xe,
516 } DebugBlockId_BY16;
517 typedef enum SurfaceEndian {
518 ENDIAN_NONE = 0x0,
519 ENDIAN_8IN16 = 0x1,
520 ENDIAN_8IN32 = 0x2,
521 ENDIAN_8IN64 = 0x3,
522 } SurfaceEndian;
523 typedef enum ArrayMode {
524 ARRAY_LINEAR_GENERAL = 0x0,
525 ARRAY_LINEAR_ALIGNED = 0x1,
526 ARRAY_1D_TILED_THIN1 = 0x2,
527 ARRAY_1D_TILED_THICK = 0x3,
528 ARRAY_2D_TILED_THIN1 = 0x4,
529 ARRAY_PRT_TILED_THIN1 = 0x5,
530 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
531 ARRAY_2D_TILED_THICK = 0x7,
532 ARRAY_2D_TILED_XTHICK = 0x8,
533 ARRAY_PRT_TILED_THICK = 0x9,
534 ARRAY_PRT_2D_TILED_THICK = 0xa,
535 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
536 ARRAY_3D_TILED_THIN1 = 0xc,
537 ARRAY_3D_TILED_THICK = 0xd,
538 ARRAY_3D_TILED_XTHICK = 0xe,
539 ARRAY_PRT_3D_TILED_THICK = 0xf,
540 } ArrayMode;
541 typedef enum PipeTiling {
542 CONFIG_1_PIPE = 0x0,
543 CONFIG_2_PIPE = 0x1,
544 CONFIG_4_PIPE = 0x2,
545 CONFIG_8_PIPE = 0x3,
546 } PipeTiling;
547 typedef enum BankTiling {
548 CONFIG_4_BANK = 0x0,
549 CONFIG_8_BANK = 0x1,
550 } BankTiling;
551 typedef enum GroupInterleave {
552 CONFIG_256B_GROUP = 0x0,
553 CONFIG_512B_GROUP = 0x1,
554 } GroupInterleave;
555 typedef enum RowTiling {
556 CONFIG_1KB_ROW = 0x0,
557 CONFIG_2KB_ROW = 0x1,
558 CONFIG_4KB_ROW = 0x2,
559 CONFIG_8KB_ROW = 0x3,
560 CONFIG_1KB_ROW_OPT = 0x4,
561 CONFIG_2KB_ROW_OPT = 0x5,
562 CONFIG_4KB_ROW_OPT = 0x6,
563 CONFIG_8KB_ROW_OPT = 0x7,
564 } RowTiling;
565 typedef enum BankSwapBytes {
566 CONFIG_128B_SWAPS = 0x0,
567 CONFIG_256B_SWAPS = 0x1,
568 CONFIG_512B_SWAPS = 0x2,
569 CONFIG_1KB_SWAPS = 0x3,
570 } BankSwapBytes;
571 typedef enum SampleSplitBytes {
572 CONFIG_1KB_SPLIT = 0x0,
573 CONFIG_2KB_SPLIT = 0x1,
574 CONFIG_4KB_SPLIT = 0x2,
575 CONFIG_8KB_SPLIT = 0x3,
576 } SampleSplitBytes;
577 typedef enum NumPipes {
578 ADDR_CONFIG_1_PIPE = 0x0,
579 ADDR_CONFIG_2_PIPE = 0x1,
580 ADDR_CONFIG_4_PIPE = 0x2,
581 ADDR_CONFIG_8_PIPE = 0x3,
582 } NumPipes;
583 typedef enum PipeInterleaveSize {
584 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
585 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
586 } PipeInterleaveSize;
587 typedef enum BankInterleaveSize {
588 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
589 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
590 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
591 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
592 } BankInterleaveSize;
593 typedef enum NumShaderEngines {
594 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
595 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
596 } NumShaderEngines;
597 typedef enum ShaderEngineTileSize {
598 ADDR_CONFIG_SE_TILE_16 = 0x0,
599 ADDR_CONFIG_SE_TILE_32 = 0x1,
600 } ShaderEngineTileSize;
601 typedef enum NumGPUs {
602 ADDR_CONFIG_1_GPU = 0x0,
603 ADDR_CONFIG_2_GPU = 0x1,
604 ADDR_CONFIG_4_GPU = 0x2,
605 } NumGPUs;
606 typedef enum MultiGPUTileSize {
607 ADDR_CONFIG_GPU_TILE_16 = 0x0,
608 ADDR_CONFIG_GPU_TILE_32 = 0x1,
609 ADDR_CONFIG_GPU_TILE_64 = 0x2,
610 ADDR_CONFIG_GPU_TILE_128 = 0x3,
611 } MultiGPUTileSize;
612 typedef enum RowSize {
613 ADDR_CONFIG_1KB_ROW = 0x0,
614 ADDR_CONFIG_2KB_ROW = 0x1,
615 ADDR_CONFIG_4KB_ROW = 0x2,
616 } RowSize;
617 typedef enum NumLowerPipes {
618 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
619 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
620 } NumLowerPipes;
621 typedef enum ColorTransform {
622 DCC_CT_AUTO = 0x0,
623 DCC_CT_NONE = 0x1,
624 ABGR_TO_A_BG_G_RB = 0x2,
625 BGRA_TO_BG_G_RB_A = 0x3,
626 } ColorTransform;
627 typedef enum CompareRef {
628 REF_NEVER = 0x0,
629 REF_LESS = 0x1,
630 REF_EQUAL = 0x2,
631 REF_LEQUAL = 0x3,
632 REF_GREATER = 0x4,
633 REF_NOTEQUAL = 0x5,
634 REF_GEQUAL = 0x6,
635 REF_ALWAYS = 0x7,
636 } CompareRef;
637 typedef enum ReadSize {
638 READ_256_BITS = 0x0,
639 READ_512_BITS = 0x1,
640 } ReadSize;
641 typedef enum DepthFormat {
642 DEPTH_INVALID = 0x0,
643 DEPTH_16 = 0x1,
644 DEPTH_X8_24 = 0x2,
645 DEPTH_8_24 = 0x3,
646 DEPTH_X8_24_FLOAT = 0x4,
647 DEPTH_8_24_FLOAT = 0x5,
648 DEPTH_32_FLOAT = 0x6,
649 DEPTH_X24_8_32_FLOAT = 0x7,
650 } DepthFormat;
651 typedef enum ZFormat {
652 Z_INVALID = 0x0,
653 Z_16 = 0x1,
654 Z_24 = 0x2,
655 Z_32_FLOAT = 0x3,
656 } ZFormat;
657 typedef enum StencilFormat {
658 STENCIL_INVALID = 0x0,
659 STENCIL_8 = 0x1,
660 } StencilFormat;
661 typedef enum CmaskMode {
662 CMASK_CLEAR_NONE = 0x0,
663 CMASK_CLEAR_ONE = 0x1,
664 CMASK_CLEAR_ALL = 0x2,
665 CMASK_ANY_EXPANDED = 0x3,
666 CMASK_ALPHA0_FRAG1 = 0x4,
667 CMASK_ALPHA0_FRAG2 = 0x5,
668 CMASK_ALPHA0_FRAG4 = 0x6,
669 CMASK_ALPHA0_FRAGS = 0x7,
670 CMASK_ALPHA1_FRAG1 = 0x8,
671 CMASK_ALPHA1_FRAG2 = 0x9,
672 CMASK_ALPHA1_FRAG4 = 0xa,
673 CMASK_ALPHA1_FRAGS = 0xb,
674 CMASK_ALPHAX_FRAG1 = 0xc,
675 CMASK_ALPHAX_FRAG2 = 0xd,
676 CMASK_ALPHAX_FRAG4 = 0xe,
677 CMASK_ALPHAX_FRAGS = 0xf,
678 } CmaskMode;
679 typedef enum QuadExportFormat {
680 EXPORT_UNUSED = 0x0,
681 EXPORT_32_R = 0x1,
682 EXPORT_32_GR = 0x2,
683 EXPORT_32_AR = 0x3,
684 EXPORT_FP16_ABGR = 0x4,
685 EXPORT_UNSIGNED16_ABGR = 0x5,
686 EXPORT_SIGNED16_ABGR = 0x6,
687 EXPORT_32_ABGR = 0x7,
688 } QuadExportFormat;
689 typedef enum QuadExportFormatOld {
690 EXPORT_4P_32BPC_ABGR = 0x0,
691 EXPORT_4P_16BPC_ABGR = 0x1,
692 EXPORT_4P_32BPC_GR = 0x2,
693 EXPORT_4P_32BPC_AR = 0x3,
694 EXPORT_2P_32BPC_ABGR = 0x4,
695 EXPORT_8P_32BPC_R = 0x5,
696 } QuadExportFormatOld;
697 typedef enum ColorFormat {
698 COLOR_INVALID = 0x0,
699 COLOR_8 = 0x1,
700 COLOR_16 = 0x2,
701 COLOR_8_8 = 0x3,
702 COLOR_32 = 0x4,
703 COLOR_16_16 = 0x5,
704 COLOR_10_11_11 = 0x6,
705 COLOR_11_11_10 = 0x7,
706 COLOR_10_10_10_2 = 0x8,
707 COLOR_2_10_10_10 = 0x9,
708 COLOR_8_8_8_8 = 0xa,
709 COLOR_32_32 = 0xb,
710 COLOR_16_16_16_16 = 0xc,
711 COLOR_RESERVED_13 = 0xd,
712 COLOR_32_32_32_32 = 0xe,
713 COLOR_RESERVED_15 = 0xf,
714 COLOR_5_6_5 = 0x10,
715 COLOR_1_5_5_5 = 0x11,
716 COLOR_5_5_5_1 = 0x12,
717 COLOR_4_4_4_4 = 0x13,
718 COLOR_8_24 = 0x14,
719 COLOR_24_8 = 0x15,
720 COLOR_X24_8_32_FLOAT = 0x16,
721 COLOR_RESERVED_23 = 0x17,
722 } ColorFormat;
723 typedef enum SurfaceFormat {
724 FMT_INVALID = 0x0,
725 FMT_8 = 0x1,
726 FMT_16 = 0x2,
727 FMT_8_8 = 0x3,
728 FMT_32 = 0x4,
729 FMT_16_16 = 0x5,
730 FMT_10_11_11 = 0x6,
731 FMT_11_11_10 = 0x7,
732 FMT_10_10_10_2 = 0x8,
733 FMT_2_10_10_10 = 0x9,
734 FMT_8_8_8_8 = 0xa,
735 FMT_32_32 = 0xb,
736 FMT_16_16_16_16 = 0xc,
737 FMT_32_32_32 = 0xd,
738 FMT_32_32_32_32 = 0xe,
739 FMT_RESERVED_4 = 0xf,
740 FMT_5_6_5 = 0x10,
741 FMT_1_5_5_5 = 0x11,
742 FMT_5_5_5_1 = 0x12,
743 FMT_4_4_4_4 = 0x13,
744 FMT_8_24 = 0x14,
745 FMT_24_8 = 0x15,
746 FMT_X24_8_32_FLOAT = 0x16,
747 FMT_RESERVED_33 = 0x17,
748 FMT_11_11_10_FLOAT = 0x18,
749 FMT_16_FLOAT = 0x19,
750 FMT_32_FLOAT = 0x1a,
751 FMT_16_16_FLOAT = 0x1b,
752 FMT_8_24_FLOAT = 0x1c,
753 FMT_24_8_FLOAT = 0x1d,
754 FMT_32_32_FLOAT = 0x1e,
755 FMT_10_11_11_FLOAT = 0x1f,
756 FMT_16_16_16_16_FLOAT = 0x20,
757 FMT_3_3_2 = 0x21,
758 FMT_6_5_5 = 0x22,
759 FMT_32_32_32_32_FLOAT = 0x23,
760 FMT_RESERVED_36 = 0x24,
761 FMT_1 = 0x25,
762 FMT_1_REVERSED = 0x26,
763 FMT_GB_GR = 0x27,
764 FMT_BG_RG = 0x28,
765 FMT_32_AS_8 = 0x29,
766 FMT_32_AS_8_8 = 0x2a,
767 FMT_5_9_9_9_SHAREDEXP = 0x2b,
768 FMT_8_8_8 = 0x2c,
769 FMT_16_16_16 = 0x2d,
770 FMT_16_16_16_FLOAT = 0x2e,
771 FMT_4_4 = 0x2f,
772 FMT_32_32_32_FLOAT = 0x30,
773 FMT_BC1 = 0x31,
774 FMT_BC2 = 0x32,
775 FMT_BC3 = 0x33,
776 FMT_BC4 = 0x34,
777 FMT_BC5 = 0x35,
778 FMT_BC6 = 0x36,
779 FMT_BC7 = 0x37,
780 FMT_32_AS_32_32_32_32 = 0x38,
781 FMT_APC3 = 0x39,
782 FMT_APC4 = 0x3a,
783 FMT_APC5 = 0x3b,
784 FMT_APC6 = 0x3c,
785 FMT_APC7 = 0x3d,
786 FMT_CTX1 = 0x3e,
787 FMT_RESERVED_63 = 0x3f,
788 } SurfaceFormat;
789 typedef enum BUF_DATA_FORMAT {
790 BUF_DATA_FORMAT_INVALID = 0x0,
791 BUF_DATA_FORMAT_8 = 0x1,
792 BUF_DATA_FORMAT_16 = 0x2,
793 BUF_DATA_FORMAT_8_8 = 0x3,
794 BUF_DATA_FORMAT_32 = 0x4,
795 BUF_DATA_FORMAT_16_16 = 0x5,
796 BUF_DATA_FORMAT_10_11_11 = 0x6,
797 BUF_DATA_FORMAT_11_11_10 = 0x7,
798 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
799 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
800 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
801 BUF_DATA_FORMAT_32_32 = 0xb,
802 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
803 BUF_DATA_FORMAT_32_32_32 = 0xd,
804 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
805 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
806 } BUF_DATA_FORMAT;
807 typedef enum IMG_DATA_FORMAT {
808 IMG_DATA_FORMAT_INVALID = 0x0,
809 IMG_DATA_FORMAT_8 = 0x1,
810 IMG_DATA_FORMAT_16 = 0x2,
811 IMG_DATA_FORMAT_8_8 = 0x3,
812 IMG_DATA_FORMAT_32 = 0x4,
813 IMG_DATA_FORMAT_16_16 = 0x5,
814 IMG_DATA_FORMAT_10_11_11 = 0x6,
815 IMG_DATA_FORMAT_11_11_10 = 0x7,
816 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
817 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
818 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
819 IMG_DATA_FORMAT_32_32 = 0xb,
820 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
821 IMG_DATA_FORMAT_32_32_32 = 0xd,
822 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
823 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
824 IMG_DATA_FORMAT_5_6_5 = 0x10,
825 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
826 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
827 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
828 IMG_DATA_FORMAT_8_24 = 0x14,
829 IMG_DATA_FORMAT_24_8 = 0x15,
830 IMG_DATA_FORMAT_X24_8_32 = 0x16,
831 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
832 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
833 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
834 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
835 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
836 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
837 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
838 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
839 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
840 IMG_DATA_FORMAT_GB_GR = 0x20,
841 IMG_DATA_FORMAT_BG_RG = 0x21,
842 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
843 IMG_DATA_FORMAT_BC1 = 0x23,
844 IMG_DATA_FORMAT_BC2 = 0x24,
845 IMG_DATA_FORMAT_BC3 = 0x25,
846 IMG_DATA_FORMAT_BC4 = 0x26,
847 IMG_DATA_FORMAT_BC5 = 0x27,
848 IMG_DATA_FORMAT_BC6 = 0x28,
849 IMG_DATA_FORMAT_BC7 = 0x29,
850 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
851 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
852 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
853 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
854 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
855 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
856 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
857 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
858 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
859 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
860 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
861 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
862 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
863 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
864 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
865 IMG_DATA_FORMAT_4_4 = 0x39,
866 IMG_DATA_FORMAT_6_5_5 = 0x3a,
867 IMG_DATA_FORMAT_1 = 0x3b,
868 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
869 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
870 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
871 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
872 } IMG_DATA_FORMAT;
873 typedef enum BUF_NUM_FORMAT {
874 BUF_NUM_FORMAT_UNORM = 0x0,
875 BUF_NUM_FORMAT_SNORM = 0x1,
876 BUF_NUM_FORMAT_USCALED = 0x2,
877 BUF_NUM_FORMAT_SSCALED = 0x3,
878 BUF_NUM_FORMAT_UINT = 0x4,
879 BUF_NUM_FORMAT_SINT = 0x5,
880 BUF_NUM_FORMAT_RESERVED_6 = 0x6,
881 BUF_NUM_FORMAT_FLOAT = 0x7,
882 } BUF_NUM_FORMAT;
883 typedef enum IMG_NUM_FORMAT {
884 IMG_NUM_FORMAT_UNORM = 0x0,
885 IMG_NUM_FORMAT_SNORM = 0x1,
886 IMG_NUM_FORMAT_USCALED = 0x2,
887 IMG_NUM_FORMAT_SSCALED = 0x3,
888 IMG_NUM_FORMAT_UINT = 0x4,
889 IMG_NUM_FORMAT_SINT = 0x5,
890 IMG_NUM_FORMAT_RESERVED_6 = 0x6,
891 IMG_NUM_FORMAT_FLOAT = 0x7,
892 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
893 IMG_NUM_FORMAT_SRGB = 0x9,
894 IMG_NUM_FORMAT_RESERVED_10 = 0xa,
895 IMG_NUM_FORMAT_RESERVED_11 = 0xb,
896 IMG_NUM_FORMAT_RESERVED_12 = 0xc,
897 IMG_NUM_FORMAT_RESERVED_13 = 0xd,
898 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
899 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
900 } IMG_NUM_FORMAT;
901 typedef enum TileType {
902 ARRAY_COLOR_TILE = 0x0,
903 ARRAY_DEPTH_TILE = 0x1,
904 } TileType;
905 typedef enum NonDispTilingOrder {
906 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
907 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
908 } NonDispTilingOrder;
909 typedef enum MicroTileMode {
910 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
911 ADDR_SURF_THIN_MICRO_TILING = 0x1,
912 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
913 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
914 ADDR_SURF_THICK_MICRO_TILING = 0x4,
915 } MicroTileMode;
916 typedef enum TileSplit {
917 ADDR_SURF_TILE_SPLIT_64B = 0x0,
918 ADDR_SURF_TILE_SPLIT_128B = 0x1,
919 ADDR_SURF_TILE_SPLIT_256B = 0x2,
920 ADDR_SURF_TILE_SPLIT_512B = 0x3,
921 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
922 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
923 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
924 } TileSplit;
925 typedef enum SampleSplit {
926 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
927 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
928 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
929 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
930 } SampleSplit;
931 typedef enum PipeConfig {
932 ADDR_SURF_P2 = 0x0,
933 ADDR_SURF_P2_RESERVED0 = 0x1,
934 ADDR_SURF_P2_RESERVED1 = 0x2,
935 ADDR_SURF_P2_RESERVED2 = 0x3,
936 ADDR_SURF_P4_8x16 = 0x4,
937 ADDR_SURF_P4_16x16 = 0x5,
938 ADDR_SURF_P4_16x32 = 0x6,
939 ADDR_SURF_P4_32x32 = 0x7,
940 ADDR_SURF_P8_16x16_8x16 = 0x8,
941 ADDR_SURF_P8_16x32_8x16 = 0x9,
942 ADDR_SURF_P8_32x32_8x16 = 0xa,
943 ADDR_SURF_P8_16x32_16x16 = 0xb,
944 ADDR_SURF_P8_32x32_16x16 = 0xc,
945 ADDR_SURF_P8_32x32_16x32 = 0xd,
946 ADDR_SURF_P8_32x64_32x32 = 0xe,
947 ADDR_SURF_P8_RESERVED0 = 0xf,
948 ADDR_SURF_P16_32x32_8x16 = 0x10,
949 ADDR_SURF_P16_32x32_16x16 = 0x11,
950 } PipeConfig;
951 typedef enum NumBanks {
952 ADDR_SURF_2_BANK = 0x0,
953 ADDR_SURF_4_BANK = 0x1,
954 ADDR_SURF_8_BANK = 0x2,
955 ADDR_SURF_16_BANK = 0x3,
956 } NumBanks;
957 typedef enum BankWidth {
958 ADDR_SURF_BANK_WIDTH_1 = 0x0,
959 ADDR_SURF_BANK_WIDTH_2 = 0x1,
960 ADDR_SURF_BANK_WIDTH_4 = 0x2,
961 ADDR_SURF_BANK_WIDTH_8 = 0x3,
962 } BankWidth;
963 typedef enum BankHeight {
964 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
965 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
966 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
967 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
968 } BankHeight;
969 typedef enum BankWidthHeight {
970 ADDR_SURF_BANK_WH_1 = 0x0,
971 ADDR_SURF_BANK_WH_2 = 0x1,
972 ADDR_SURF_BANK_WH_4 = 0x2,
973 ADDR_SURF_BANK_WH_8 = 0x3,
974 } BankWidthHeight;
975 typedef enum MacroTileAspect {
976 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
977 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
978 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
979 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
980 } MacroTileAspect;
981 typedef enum GATCL1RequestType {
982 GATCL1_TYPE_NORMAL = 0x0,
983 GATCL1_TYPE_SHOOTDOWN = 0x1,
984 GATCL1_TYPE_BYPASS = 0x2,
985 } GATCL1RequestType;
986 typedef enum TCC_CACHE_POLICIES {
987 TCC_CACHE_POLICY_LRU = 0x0,
988 TCC_CACHE_POLICY_STREAM = 0x1,
989 } TCC_CACHE_POLICIES;
990 typedef enum MTYPE {
991 MTYPE_NC_NV = 0x0,
992 MTYPE_NC = 0x1,
993 MTYPE_CC = 0x2,
994 MTYPE_UC = 0x3,
995 } MTYPE;
996 typedef enum PERFMON_COUNTER_MODE {
997 PERFMON_COUNTER_MODE_ACCUM = 0x0,
998 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
999 PERFMON_COUNTER_MODE_MAX = 0x2,
1000 PERFMON_COUNTER_MODE_DIRTY = 0x3,
1001 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1002 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1003 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1004 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1005 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1006 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1007 PERFMON_COUNTER_MODE_RESERVED = 0xf,
1008 } PERFMON_COUNTER_MODE;
1009 typedef enum PERFMON_SPM_MODE {
1010 PERFMON_SPM_MODE_OFF = 0x0,
1011 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1012 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1013 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1014 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1015 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1016 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1017 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1018 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1019 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1020 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1021 } PERFMON_SPM_MODE;
1022 typedef enum SurfaceTiling {
1023 ARRAY_LINEAR = 0x0,
1024 ARRAY_TILED = 0x1,
1025 } SurfaceTiling;
1026 typedef enum SurfaceArray {
1027 ARRAY_1D = 0x0,
1028 ARRAY_2D = 0x1,
1029 ARRAY_3D = 0x2,
1030 ARRAY_3D_SLICE = 0x3,
1031 } SurfaceArray;
1032 typedef enum ColorArray {
1033 ARRAY_2D_ALT_COLOR = 0x0,
1034 ARRAY_2D_COLOR = 0x1,
1035 ARRAY_3D_SLICE_COLOR = 0x3,
1036 } ColorArray;
1037 typedef enum DepthArray {
1038 ARRAY_2D_ALT_DEPTH = 0x0,
1039 ARRAY_2D_DEPTH = 0x1,
1040 } DepthArray;
1041 typedef enum ENUM_NUM_SIMD_PER_CU {
1042 NUM_SIMD_PER_CU = 0x4,
1043 } ENUM_NUM_SIMD_PER_CU;
1044 typedef enum MEM_PWR_FORCE_CTRL {
1045 NO_FORCE_REQUEST = 0x0,
1046 FORCE_LIGHT_SLEEP_REQUEST = 0x1,
1047 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1048 FORCE_SHUT_DOWN_REQUEST = 0x3,
1049 } MEM_PWR_FORCE_CTRL;
1050 typedef enum MEM_PWR_FORCE_CTRL2 {
1051 NO_FORCE_REQ = 0x0,
1052 FORCE_LIGHT_SLEEP_REQ = 0x1,
1053 } MEM_PWR_FORCE_CTRL2;
1054 typedef enum MEM_PWR_DIS_CTRL {
1055 ENABLE_MEM_PWR_CTRL = 0x0,
1056 DISABLE_MEM_PWR_CTRL = 0x1,
1057 } MEM_PWR_DIS_CTRL;
1058 typedef enum MEM_PWR_SEL_CTRL {
1059 DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
1060 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
1061 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
1062 } MEM_PWR_SEL_CTRL;
1063 typedef enum MEM_PWR_SEL_CTRL2 {
1064 DYNAMIC_DEEP_SLEEP_EN = 0x0,
1065 DYNAMIC_LIGHT_SLEEP_EN = 0x1,
1066 } MEM_PWR_SEL_CTRL2;
1067
1068 #endif /* ACP_2_2_ENUM_H */
Linux with added FPC-III support