sound/soc/intel/common/sst-dsp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Intel Smart Sound Technology (SST) DSP Core Driver
   4  *
   5  * Copyright (C) 2013, Intel Corporation. All rights reserved.
   6  */
   7
   8 #include <linux/slab.h>
   9 #include <linux/export.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/io-64-nonatomic-lo-hi.h>
  14 #include <linux/delay.h>
  15
  16 #include "sst-dsp.h"
  17 #include "sst-dsp-priv.h"
  18
  19 #define CREATE_TRACE_POINTS
  20 #include <trace/events/intel-sst.h>
  21
  22 /* Internal generic low-level SST IO functions - can be overidden */
  23 void sst_shim32_write(void __iomem *addr, u32 offset, u32 value)
  24 {
  25         writel(value, addr + offset);
  26 }
  27 EXPORT_SYMBOL_GPL(sst_shim32_write);
  28
  29 u32 sst_shim32_read(void __iomem *addr, u32 offset)
  30 {
  31         return readl(addr + offset);
  32 }
  33 EXPORT_SYMBOL_GPL(sst_shim32_read);
  34
  35 void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value)
  36 {
  37         writeq(value, addr + offset);
  38 }
  39 EXPORT_SYMBOL_GPL(sst_shim32_write64);
  40
  41 u64 sst_shim32_read64(void __iomem *addr, u32 offset)
  42 {
  43         return readq(addr + offset);
  44 }
  45 EXPORT_SYMBOL_GPL(sst_shim32_read64);
  46
  47 /* Public API */
  48 void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value)
  49 {
  50         unsigned long flags;
  51
  52         spin_lock_irqsave(&sst->spinlock, flags);
  53         sst->ops->write(sst->addr.shim, offset, value);
  54         spin_unlock_irqrestore(&sst->spinlock, flags);
  55 }
  56 EXPORT_SYMBOL_GPL(sst_dsp_shim_write);
  57
  58 u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset)
  59 {
  60         unsigned long flags;
  61         u32 val;
  62
  63         spin_lock_irqsave(&sst->spinlock, flags);
  64         val = sst->ops->read(sst->addr.shim, offset);
  65         spin_unlock_irqrestore(&sst->spinlock, flags);
  66
  67         return val;
  68 }
  69 EXPORT_SYMBOL_GPL(sst_dsp_shim_read);
  70
  71 void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value)
  72 {
  73         sst->ops->write(sst->addr.shim, offset, value);
  74 }
  75 EXPORT_SYMBOL_GPL(sst_dsp_shim_write_unlocked);
  76
  77 u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset)
  78 {
  79         return sst->ops->read(sst->addr.shim, offset);
  80 }
  81 EXPORT_SYMBOL_GPL(sst_dsp_shim_read_unlocked);
  82
  83 int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
  84                                 u32 mask, u32 value)
  85 {
  86         bool change;
  87         unsigned int old, new;
  88         u32 ret;
  89
  90         ret = sst_dsp_shim_read_unlocked(sst, offset);
  91
  92         old = ret;
  93         new = (old & (~mask)) | (value & mask);
  94
  95         change = (old != new);
  96         if (change)
  97                 sst_dsp_shim_write_unlocked(sst, offset, new);
  98
  99         return change;
 100 }
 101 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_unlocked);
 102
 103 /* This is for registers bits with attribute RWC */
 104 void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
 105                                 u32 mask, u32 value)
 106 {
 107         unsigned int old, new;
 108         u32 ret;
 109
 110         ret = sst_dsp_shim_read_unlocked(sst, offset);
 111
 112         old = ret;
 113         new = (old & (~mask)) | (value & mask);
 114
 115         sst_dsp_shim_write_unlocked(sst, offset, new);
 116 }
 117 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced_unlocked);
 118
 119 int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
 120                                 u32 mask, u32 value)
 121 {
 122         unsigned long flags;
 123         bool change;
 124
 125         spin_lock_irqsave(&sst->spinlock, flags);
 126         change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value);
 127         spin_unlock_irqrestore(&sst->spinlock, flags);
 128         return change;
 129 }
 130 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits);
 131
 132 /* This is for registers bits with attribute RWC */
 133 void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
 134                                 u32 mask, u32 value)
 135 {
 136         unsigned long flags;
 137
 138         spin_lock_irqsave(&sst->spinlock, flags);
 139         sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value);
 140         spin_unlock_irqrestore(&sst->spinlock, flags);
 141 }
 142 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced);
 143
 144 int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
 145                          u32 target, u32 time, char *operation)
 146 {
 147         u32 reg;
 148         unsigned long timeout;
 149         int k = 0, s = 500;
 150
 151         /*
 152          * split the loop into sleeps of varying resolution. more accurately,
 153          * the range of wakeups are:
 154          * Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms.
 155          * Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms
 156          * (usleep_range (500, 1000) and usleep_range(5000, 10000) are
 157          * both possible in this phase depending on whether k > 10 or not).
 158          * Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms.
 159          */
 160
 161         timeout = jiffies + msecs_to_jiffies(time);
 162         while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target)
 163                 && time_before(jiffies, timeout)) {
 164                 k++;
 165                 if (k > 10)
 166                         s = 5000;
 167
 168                 usleep_range(s, 2*s);
 169         }
 170
 171         if ((reg & mask) == target) {
 172                 dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n",
 173                                         reg, operation);
 174
 175                 return 0;
 176         }
 177
 178         dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n",
 179                                         reg, operation);
 180         return -ETIME;
 181 }
 182 EXPORT_SYMBOL_GPL(sst_dsp_register_poll);
 183
 184 int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset, size_t inbox_size,
 185         u32 outbox_offset, size_t outbox_size)
 186 {
 187         sst->mailbox.in_base = sst->addr.lpe + inbox_offset;
 188         sst->mailbox.out_base = sst->addr.lpe + outbox_offset;
 189         sst->mailbox.in_size = inbox_size;
 190         sst->mailbox.out_size = outbox_size;
 191         return 0;
 192 }
 193 EXPORT_SYMBOL_GPL(sst_dsp_mailbox_init);
 194
 195 void sst_dsp_outbox_write(struct sst_dsp *sst, void *message, size_t bytes)
 196 {
 197         u32 i;
 198
 199         trace_sst_ipc_outbox_write(bytes);
 200
 201         memcpy_toio(sst->mailbox.out_base, message, bytes);
 202
 203         for (i = 0; i < bytes; i += 4)
 204                 trace_sst_ipc_outbox_wdata(i, *(u32 *)(message + i));
 205 }
 206 EXPORT_SYMBOL_GPL(sst_dsp_outbox_write);
 207
 208 void sst_dsp_outbox_read(struct sst_dsp *sst, void *message, size_t bytes)
 209 {
 210         u32 i;
 211
 212         trace_sst_ipc_outbox_read(bytes);
 213
 214         memcpy_fromio(message, sst->mailbox.out_base, bytes);
 215
 216         for (i = 0; i < bytes; i += 4)
 217                 trace_sst_ipc_outbox_rdata(i, *(u32 *)(message + i));
 218 }
 219 EXPORT_SYMBOL_GPL(sst_dsp_outbox_read);
 220
 221 void sst_dsp_inbox_write(struct sst_dsp *sst, void *message, size_t bytes)
 222 {
 223         u32 i;
 224
 225         trace_sst_ipc_inbox_write(bytes);
 226
 227         memcpy_toio(sst->mailbox.in_base, message, bytes);
 228
 229         for (i = 0; i < bytes; i += 4)
 230                 trace_sst_ipc_inbox_wdata(i, *(u32 *)(message + i));
 231 }
 232 EXPORT_SYMBOL_GPL(sst_dsp_inbox_write);
 233
 234 void sst_dsp_inbox_read(struct sst_dsp *sst, void *message, size_t bytes)
 235 {
 236         u32 i;
 237
 238         trace_sst_ipc_inbox_read(bytes);
 239
 240         memcpy_fromio(message, sst->mailbox.in_base, bytes);
 241
 242         for (i = 0; i < bytes; i += 4)
 243                 trace_sst_ipc_inbox_rdata(i, *(u32 *)(message + i));
 244 }
 245 EXPORT_SYMBOL_GPL(sst_dsp_inbox_read);
 246
 247 /* Module information */
 248 MODULE_AUTHOR("Liam Girdwood");
 249 MODULE_DESCRIPTION("Intel SST Core");
 250 MODULE_LICENSE("GPL v2");