sound/soc/intel/skylake/skl-sst-dsp.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Skylake SST DSP Support
   4  *
   5  * Copyright (C) 2014-15, Intel Corporation.
   6  */
   7
   8 #ifndef __SKL_SST_DSP_H__
   9 #define __SKL_SST_DSP_H__
  10
  11 #include <linux/interrupt.h>
  12 #include <linux/uuid.h>
  13 #include <linux/firmware.h>
  14 #include <sound/memalloc.h>
  15 #include "skl-sst-cldma.h"
  16
  17 struct sst_dsp;
  18 struct sst_dsp_device;
  19 struct skl_lib_info;
  20 struct skl_dev;
  21
  22 /* Intel HD Audio General DSP Registers */
  23 #define SKL_ADSP_GEN_BASE               0x0
  24 #define SKL_ADSP_REG_ADSPCS             (SKL_ADSP_GEN_BASE + 0x04)
  25 #define SKL_ADSP_REG_ADSPIC             (SKL_ADSP_GEN_BASE + 0x08)
  26 #define SKL_ADSP_REG_ADSPIS             (SKL_ADSP_GEN_BASE + 0x0C)
  27 #define SKL_ADSP_REG_ADSPIC2            (SKL_ADSP_GEN_BASE + 0x10)
  28 #define SKL_ADSP_REG_ADSPIS2            (SKL_ADSP_GEN_BASE + 0x14)
  29
  30 /* Intel HD Audio Inter-Processor Communication Registers */
  31 #define SKL_ADSP_IPC_BASE               0x40
  32 #define SKL_ADSP_REG_HIPCT              (SKL_ADSP_IPC_BASE + 0x00)
  33 #define SKL_ADSP_REG_HIPCTE             (SKL_ADSP_IPC_BASE + 0x04)
  34 #define SKL_ADSP_REG_HIPCI              (SKL_ADSP_IPC_BASE + 0x08)
  35 #define SKL_ADSP_REG_HIPCIE             (SKL_ADSP_IPC_BASE + 0x0C)
  36 #define SKL_ADSP_REG_HIPCCTL            (SKL_ADSP_IPC_BASE + 0x10)
  37
  38 /*  HIPCI */
  39 #define SKL_ADSP_REG_HIPCI_BUSY         BIT(31)
  40
  41 /* HIPCIE */
  42 #define SKL_ADSP_REG_HIPCIE_DONE        BIT(30)
  43
  44 /* HIPCCTL */
  45 #define SKL_ADSP_REG_HIPCCTL_DONE       BIT(1)
  46 #define SKL_ADSP_REG_HIPCCTL_BUSY       BIT(0)
  47
  48 /* HIPCT */
  49 #define SKL_ADSP_REG_HIPCT_BUSY         BIT(31)
  50
  51 /* FW base IDs */
  52 #define SKL_INSTANCE_ID                 0
  53 #define SKL_BASE_FW_MODULE_ID           0
  54
  55 /* Intel HD Audio SRAM Window 1 */
  56 #define SKL_ADSP_SRAM1_BASE             0xA000
  57
  58 #define SKL_ADSP_MMIO_LEN               0x10000
  59
  60 #define SKL_ADSP_W0_STAT_SZ             0x1000
  61
  62 #define SKL_ADSP_W0_UP_SZ               0x1000
  63
  64 #define SKL_ADSP_W1_SZ                  0x1000
  65
  66 #define SKL_FW_STS_MASK                 0xf
  67
  68 #define SKL_FW_INIT                     0x1
  69 #define SKL_FW_RFW_START                0xf
  70 #define BXT_FW_ROM_INIT_RETRY           3
  71 #define BXT_INIT_TIMEOUT                300
  72
  73 #define SKL_ADSPIC_IPC                  1
  74 #define SKL_ADSPIS_IPC                  1
  75
  76 /* Core ID of core0 */
  77 #define SKL_DSP_CORE0_ID                0
  78
  79 /* Mask for a given core index, c = 0.. number of supported cores - 1 */
  80 #define SKL_DSP_CORE_MASK(c)            BIT(c)
  81
  82 /*
  83  * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately
  84  * since Core0 is primary core and it is used often
  85  */
  86 #define SKL_DSP_CORE0_MASK              BIT(0)
  87
  88 /*
  89  * Mask for a given number of cores
  90  * nc = number of supported cores
  91  */
  92 #define SKL_DSP_CORES_MASK(nc)  GENMASK((nc - 1), 0)
  93
  94 /* ADSPCS - Audio DSP Control & Status */
  95
  96 /*
  97  * Core Reset - asserted high
  98  * CRST Mask for a given core mask pattern, cm
  99  */
 100 #define SKL_ADSPCS_CRST_SHIFT           0
 101 #define SKL_ADSPCS_CRST_MASK(cm)        ((cm) << SKL_ADSPCS_CRST_SHIFT)
 102
 103 /*
 104  * Core run/stall - when set to '1' core is stalled
 105  * CSTALL Mask for a given core mask pattern, cm
 106  */
 107 #define SKL_ADSPCS_CSTALL_SHIFT         8
 108 #define SKL_ADSPCS_CSTALL_MASK(cm)      ((cm) << SKL_ADSPCS_CSTALL_SHIFT)
 109
 110 /*
 111  * Set Power Active - when set to '1' turn cores on
 112  * SPA Mask for a given core mask pattern, cm
 113  */
 114 #define SKL_ADSPCS_SPA_SHIFT            16
 115 #define SKL_ADSPCS_SPA_MASK(cm)         ((cm) << SKL_ADSPCS_SPA_SHIFT)
 116
 117 /*
 118  * Current Power Active - power status of cores, set by hardware
 119  * CPA Mask for a given core mask pattern, cm
 120  */
 121 #define SKL_ADSPCS_CPA_SHIFT            24
 122 #define SKL_ADSPCS_CPA_MASK(cm)         ((cm) << SKL_ADSPCS_CPA_SHIFT)
 123
 124 /* DSP Core state */
 125 enum skl_dsp_states {
 126         SKL_DSP_RUNNING = 1,
 127         /* Running in D0i3 state; can be in streaming or non-streaming D0i3 */
 128         SKL_DSP_RUNNING_D0I3, /* Running in D0i3 state*/
 129         SKL_DSP_RESET,
 130 };
 131
 132 /* D0i3 substates */
 133 enum skl_dsp_d0i3_states {
 134         SKL_DSP_D0I3_NONE = -1, /* No D0i3 */
 135         SKL_DSP_D0I3_NON_STREAMING = 0,
 136         SKL_DSP_D0I3_STREAMING = 1,
 137 };
 138
 139 struct skl_dsp_fw_ops {
 140         int (*load_fw)(struct sst_dsp  *ctx);
 141         /* FW module parser/loader */
 142         int (*load_library)(struct sst_dsp *ctx,
 143                 struct skl_lib_info *linfo, int lib_count);
 144         int (*parse_fw)(struct sst_dsp *ctx);
 145         int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id);
 146         int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id);
 147         int (*set_state_D0i3)(struct sst_dsp *ctx);
 148         int (*set_state_D0i0)(struct sst_dsp *ctx);
 149         unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
 150         int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name);
 151         int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id);
 152
 153 };
 154
 155 struct skl_dsp_loader_ops {
 156         int stream_tag;
 157
 158         int (*alloc_dma_buf)(struct device *dev,
 159                 struct snd_dma_buffer *dmab, size_t size);
 160         int (*free_dma_buf)(struct device *dev,
 161                 struct snd_dma_buffer *dmab);
 162         int (*prepare)(struct device *dev, unsigned int format,
 163                                 unsigned int byte_size,
 164                                 struct snd_dma_buffer *bufp);
 165         int (*trigger)(struct device *dev, bool start, int stream_tag);
 166
 167         int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab,
 168                                  int stream_tag);
 169 };
 170
 171 #define MAX_INSTANCE_BUFF 2
 172
 173 struct uuid_module {
 174         guid_t uuid;
 175         int id;
 176         int is_loadable;
 177         int max_instance;
 178         u64 pvt_id[MAX_INSTANCE_BUFF];
 179         int *instance_id;
 180
 181         struct list_head list;
 182 };
 183
 184 struct skl_load_module_info {
 185         u16 mod_id;
 186         const struct firmware *fw;
 187 };
 188
 189 struct skl_module_table {
 190         struct skl_load_module_info *mod_info;
 191         unsigned int usage_cnt;
 192         struct list_head list;
 193 };
 194
 195 void skl_cldma_process_intr(struct sst_dsp *ctx);
 196 void skl_cldma_int_disable(struct sst_dsp *ctx);
 197 int skl_cldma_prepare(struct sst_dsp *ctx);
 198 int skl_cldma_wait_interruptible(struct sst_dsp *ctx);
 199
 200 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
 201 struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
 202                 struct sst_dsp_device *sst_dev, int irq);
 203 int skl_dsp_acquire_irq(struct sst_dsp *sst);
 204 bool is_skl_dsp_running(struct sst_dsp *ctx);
 205
 206 unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx);
 207 void skl_dsp_init_core_state(struct sst_dsp *ctx);
 208 int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask);
 209 int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask);
 210 int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask);
 211 int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask);
 212 int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx,
 213                                         unsigned int core_mask);
 214 int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask);
 215
 216 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
 217 int skl_dsp_wake(struct sst_dsp *ctx);
 218 int skl_dsp_sleep(struct sst_dsp *ctx);
 219 void skl_dsp_free(struct sst_dsp *dsp);
 220
 221 int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id);
 222 int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id);
 223
 224 int skl_dsp_boot(struct sst_dsp *ctx);
 225 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 226                 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 227                 struct skl_dev **dsp);
 228 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 229                 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 230                 struct skl_dev **dsp);
 231 int skl_sst_init_fw(struct device *dev, struct skl_dev *skl);
 232 int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl);
 233 void skl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl);
 234 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl);
 235
 236 int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw,
 237                                 unsigned int offset, int index);
 238 int skl_get_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int instance_id);
 239 int skl_put_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int *pvt_id);
 240 int skl_get_pvt_instance_id_map(struct skl_dev *skl,
 241                                 int module_id, int instance_id);
 242 void skl_freeup_uuid_list(struct skl_dev *skl);
 243
 244 int skl_dsp_strip_extended_manifest(struct firmware *fw);
 245
 246 void skl_dsp_set_astate_cfg(struct skl_dev *skl, u32 cnt, void *data);
 247
 248 int skl_sst_ctx_init(struct device *dev, int irq, const char *fw_name,
 249                 struct skl_dsp_loader_ops dsp_ops, struct skl_dev **dsp,
 250                 struct sst_dsp_device *skl_dev);
 251 int skl_prepare_lib_load(struct skl_dev *skl, struct skl_lib_info *linfo,
 252                         struct firmware *stripped_fw,
 253                         unsigned int hdr_offset, int index);
 254 void skl_release_library(struct skl_lib_info *linfo, int lib_count);
 255
 256 #endif /*__SKL_SST_DSP_H__*/