sound/soc/qcom/lpass.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
   4  *
   5  * lpass.h - Definitions for the QTi LPASS
   6  */
   7
   8 #ifndef __LPASS_H__
   9 #define __LPASS_H__
  10
  11 #include <linux/clk.h>
  12 #include <linux/compiler.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15 #include <dt-bindings/sound/sc7180-lpass.h>
  16 #include "lpass-hdmi.h"
  17
  18 #define LPASS_AHBIX_CLOCK_FREQUENCY             131072000
  19 #define LPASS_MAX_MI2S_PORTS                    (8)
  20 #define LPASS_MAX_DMA_CHANNELS                  (8)
  21 #define LPASS_MAX_HDMI_DMA_CHANNELS             (4)
  22
  23 #define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf)    \
  24         do { \
  25                 mf = devm_regmap_field_alloc(d, m, f);     \
  26                 if (IS_ERR(mf))                \
  27                         return -EINVAL;         \
  28         } while (0)
  29
  30 struct lpaif_i2sctl {
  31         struct regmap_field *loopback;
  32         struct regmap_field *spken;
  33         struct regmap_field *spkmode;
  34         struct regmap_field *spkmono;
  35         struct regmap_field *micen;
  36         struct regmap_field *micmode;
  37         struct regmap_field *micmono;
  38         struct regmap_field *wssrc;
  39         struct regmap_field *bitwidth;
  40 };
  41
  42
  43 struct lpaif_dmactl {
  44         struct regmap_field *intf;
  45         struct regmap_field *bursten;
  46         struct regmap_field *wpscnt;
  47         struct regmap_field *fifowm;
  48         struct regmap_field *enable;
  49         struct regmap_field *dyncclk;
  50         struct regmap_field *burst8;
  51         struct regmap_field *burst16;
  52         struct regmap_field *dynburst;
  53 };
  54
  55 /* Both the CPU DAI and platform drivers will access this data */
  56 struct lpass_data {
  57
  58         /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
  59         struct clk *ahbix_clk;
  60
  61         /* MI2S system clock */
  62         struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS];
  63
  64         /* MI2S bit clock (derived from system clock by a divider */
  65         struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
  66
  67         /* MI2S SD lines to use for playback/capture */
  68         unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
  69         unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
  70         int hdmi_port_enable;
  71         int bit_clk_state[LPASS_MAX_MI2S_PORTS];
  72
  73         /* low-power audio interface (LPAIF) registers */
  74         void __iomem *lpaif;
  75         void __iomem *hdmiif;
  76
  77         /* regmap backed by the low-power audio interface (LPAIF) registers */
  78         struct regmap *lpaif_map;
  79         struct regmap *hdmiif_map;
  80
  81         /* interrupts from the low-power audio interface (LPAIF) */
  82         int lpaif_irq;
  83         int hdmiif_irq;
  84         /* SOC specific variations in the LPASS IP integration */
  85         struct lpass_variant *variant;
  86
  87         /* bit map to keep track of static channel allocations */
  88         unsigned long dma_ch_bit_map;
  89         unsigned long hdmi_dma_ch_bit_map;
  90
  91         /* used it for handling interrupt per dma channel */
  92         struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
  93         struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS];
  94
  95         /* SOC specific clock list */
  96         struct clk_bulk_data *clks;
  97         int num_clks;
  98
  99         /* Regmap fields of I2SCTL & DMACTL registers bitfields */
 100         struct lpaif_i2sctl *i2sctl;
 101         struct lpaif_dmactl *rd_dmactl;
 102         struct lpaif_dmactl *wr_dmactl;
 103         struct lpaif_dmactl *hdmi_rd_dmactl;
 104         /* Regmap fields of HDMI_CTRL registers*/
 105         struct regmap_field *hdmitx_legacy_en;
 106         struct regmap_field *hdmitx_parity_calc_en;
 107         struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS];
 108         struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS];
 109         struct lpass_hdmi_tx_ctl *tx_ctl;
 110         struct lpass_vbit_ctrl *vbit_ctl;
 111         struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS];
 112         struct lpass_dp_metadata_ctl *meta_ctl;
 113         struct lpass_sstream_ctl *sstream_ctl;
 114 };
 115
 116 /* Vairant data per each SOC */
 117 struct lpass_variant {
 118         u32     irq_reg_base;
 119         u32     irq_reg_stride;
 120         u32     irq_ports;
 121         u32     rdma_reg_base;
 122         u32     rdma_reg_stride;
 123         u32     rdma_channels;
 124         u32     hdmi_rdma_reg_base;
 125         u32     hdmi_rdma_reg_stride;
 126         u32     hdmi_rdma_channels;
 127         u32     wrdma_reg_base;
 128         u32     wrdma_reg_stride;
 129         u32     wrdma_channels;
 130         u32     i2sctrl_reg_base;
 131         u32     i2sctrl_reg_stride;
 132         u32     i2s_ports;
 133
 134         /* I2SCTL Register fields */
 135         struct reg_field loopback;
 136         struct reg_field spken;
 137         struct reg_field spkmode;
 138         struct reg_field spkmono;
 139         struct reg_field micen;
 140         struct reg_field micmode;
 141         struct reg_field micmono;
 142         struct reg_field wssrc;
 143         struct reg_field bitwidth;
 144
 145         u32     hdmi_irq_reg_base;
 146         u32     hdmi_irq_reg_stride;
 147         u32     hdmi_irq_ports;
 148
 149         /* HDMI specific controls */
 150         u32     hdmi_tx_ctl_addr;
 151         u32     hdmi_legacy_addr;
 152         u32     hdmi_vbit_addr;
 153         u32     hdmi_ch_lsb_addr;
 154         u32     hdmi_ch_msb_addr;
 155         u32     ch_stride;
 156         u32     hdmi_parity_addr;
 157         u32     hdmi_dmactl_addr;
 158         u32     hdmi_dma_stride;
 159         u32     hdmi_DP_addr;
 160         u32     hdmi_sstream_addr;
 161
 162         /* HDMI SSTREAM CTRL fields  */
 163         struct reg_field sstream_en;
 164         struct reg_field dma_sel;
 165         struct reg_field auto_bbit_en;
 166         struct reg_field layout;
 167         struct reg_field layout_sp;
 168         struct reg_field set_sp_on_en;
 169         struct reg_field dp_audio;
 170         struct reg_field dp_staffing_en;
 171         struct reg_field dp_sp_b_hw_en;
 172
 173         /* HDMI DP METADATA CTL fields */
 174         struct reg_field mute;
 175         struct reg_field as_sdp_cc;
 176         struct reg_field as_sdp_ct;
 177         struct reg_field aif_db4;
 178         struct reg_field frequency;
 179         struct reg_field mst_index;
 180         struct reg_field dptx_index;
 181
 182         /* HDMI TX CTRL fields */
 183         struct reg_field soft_reset;
 184         struct reg_field force_reset;
 185
 186         /* HDMI TX DMA CTRL */
 187         struct reg_field use_hw_chs;
 188         struct reg_field use_hw_usr;
 189         struct reg_field hw_chs_sel;
 190         struct reg_field hw_usr_sel;
 191
 192         /* HDMI VBIT CTRL */
 193         struct reg_field replace_vbit;
 194         struct reg_field vbit_stream;
 195
 196         /* HDMI TX LEGACY */
 197         struct reg_field legacy_en;
 198
 199         /* HDMI TX PARITY */
 200         struct reg_field calc_en;
 201
 202         /* HDMI CH LSB */
 203         struct reg_field lsb_bits;
 204
 205         /* HDMI CH MSB */
 206         struct reg_field msb_bits;
 207
 208         struct reg_field hdmi_rdma_bursten;
 209         struct reg_field hdmi_rdma_wpscnt;
 210         struct reg_field hdmi_rdma_fifowm;
 211         struct reg_field hdmi_rdma_enable;
 212         struct reg_field hdmi_rdma_dyncclk;
 213         struct reg_field hdmi_rdma_burst8;
 214         struct reg_field hdmi_rdma_burst16;
 215         struct reg_field hdmi_rdma_dynburst;
 216
 217         /* RD_DMA Register fields */
 218         struct reg_field rdma_intf;
 219         struct reg_field rdma_bursten;
 220         struct reg_field rdma_wpscnt;
 221         struct reg_field rdma_fifowm;
 222         struct reg_field rdma_enable;
 223         struct reg_field rdma_dyncclk;
 224
 225         /* WR_DMA Register fields */
 226         struct reg_field wrdma_intf;
 227         struct reg_field wrdma_bursten;
 228         struct reg_field wrdma_wpscnt;
 229         struct reg_field wrdma_fifowm;
 230         struct reg_field wrdma_enable;
 231         struct reg_field wrdma_dyncclk;
 232
 233         /**
 234          * on SOCs like APQ8016 the channel control bits start
 235          * at different offset to ipq806x
 236          **/
 237         u32     dmactl_audif_start;
 238         u32     wrdma_channel_start;
 239         /* SOC specific initialization like clocks */
 240         int (*init)(struct platform_device *pdev);
 241         int (*exit)(struct platform_device *pdev);
 242         int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id);
 243         int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id);
 244
 245         /* SOC specific dais */
 246         struct snd_soc_dai_driver *dai_driver;
 247         int num_dai;
 248         const char * const *dai_osr_clk_names;
 249         const char * const *dai_bit_clk_names;
 250
 251         /* SOC specific clocks configuration */
 252         const char **clk_name;
 253         int num_clks;
 254 };
 255
 256 /* register the platform driver from the CPU DAI driver */
 257 int asoc_qcom_lpass_platform_register(struct platform_device *);
 258 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev);
 259 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev);
 260 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev);
 261 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai);
 262 extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops;
 263
 264 #endif /* __LPASS_H__ */