sound/soc/sof/intel/hda-loader.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 //
   3 // This file is provided under a dual BSD/GPLv2 license.  When using or
   4 // redistributing this file, you may do so under either license.
   5 //
   6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
   7 //
   8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9 //          Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
  10 //          Rander Wang <rander.wang@intel.com>
  11 //          Keyon Jie <yang.jie@linux.intel.com>
  12 //
  13
  14 /*
  15  * Hardware interface for HDA DSP code loader
  16  */
  17
  18 #include <linux/firmware.h>
  19 #include <sound/hdaudio_ext.h>
  20 #include <sound/hda_register.h>
  21 #include <sound/sof.h>
  22 #include "ext_manifest.h"
  23 #include "../ops.h"
  24 #include "hda.h"
  25
  26 #define HDA_FW_BOOT_ATTEMPTS    3
  27 #define HDA_CL_STREAM_FORMAT 0x40
  28
  29 static struct hdac_ext_stream *cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
  30                                                  unsigned int size, struct snd_dma_buffer *dmab,
  31                                                  int direction)
  32 {
  33         struct hdac_ext_stream *dsp_stream;
  34         struct hdac_stream *hstream;
  35         struct pci_dev *pci = to_pci_dev(sdev->dev);
  36         int ret;
  37
  38         dsp_stream = hda_dsp_stream_get(sdev, direction);
  39
  40         if (!dsp_stream) {
  41                 dev_err(sdev->dev, "error: no stream available\n");
  42                 return ERR_PTR(-ENODEV);
  43         }
  44         hstream = &dsp_stream->hstream;
  45         hstream->substream = NULL;
  46
  47         /* allocate DMA buffer */
  48         ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
  49         if (ret < 0) {
  50                 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
  51                 goto error;
  52         }
  53
  54         hstream->period_bytes = 0;/* initialize period_bytes */
  55         hstream->format_val = format;
  56         hstream->bufsize = size;
  57
  58         if (direction == SNDRV_PCM_STREAM_CAPTURE) {
  59                 ret = hda_dsp_iccmax_stream_hw_params(sdev, dsp_stream, dmab, NULL);
  60                 if (ret < 0) {
  61                         dev_err(sdev->dev, "error: iccmax stream prepare failed: %x\n", ret);
  62                         goto error;
  63                 }
  64         } else {
  65                 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
  66                 if (ret < 0) {
  67                         dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
  68                         goto error;
  69                 }
  70                 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
  71         }
  72
  73         return dsp_stream;
  74
  75 error:
  76         hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
  77         snd_dma_free_pages(dmab);
  78         return ERR_PTR(ret);
  79 }
  80
  81 /*
  82  * first boot sequence has some extra steps. core 0 waits for power
  83  * status on core 1, so power up core 1 also momentarily, keep it in
  84  * reset/stall and then turn it off
  85  */
  86 static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
  87 {
  88         struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
  89         const struct sof_intel_dsp_desc *chip = hda->desc;
  90         unsigned int status;
  91         u32 flags;
  92         int ret;
  93         int i;
  94
  95         /* step 1: power up corex */
  96         ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
  97         if (ret < 0) {
  98                 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
  99                         dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
 100                 goto err;
 101         }
 102
 103         /* DSP is powered up, set all SSPs to slave mode */
 104         for (i = 0; i < chip->ssp_count; i++) {
 105                 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
 106                                                  chip->ssp_base_offset
 107                                                  + i * SSP_DEV_MEM_SIZE
 108                                                  + SSP_SSC1_OFFSET,
 109                                                  SSP_SET_SLAVE,
 110                                                  SSP_SET_SLAVE);
 111         }
 112
 113         /* step 2: purge FW request */
 114         snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
 115                           chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
 116                           ((stream_tag - 1) << 9)));
 117
 118         /* step 3: unset core 0 reset state & unstall/run core 0 */
 119         ret = hda_dsp_core_run(sdev, BIT(0));
 120         if (ret < 0) {
 121                 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
 122                         dev_err(sdev->dev,
 123                                 "error: dsp core start failed %d\n", ret);
 124                 ret = -EIO;
 125                 goto err;
 126         }
 127
 128         /* step 4: wait for IPC DONE bit from ROM */
 129         ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
 130                                             chip->ipc_ack, status,
 131                                             ((status & chip->ipc_ack_mask)
 132                                                     == chip->ipc_ack_mask),
 133                                             HDA_DSP_REG_POLL_INTERVAL_US,
 134                                             HDA_DSP_INIT_TIMEOUT_US);
 135
 136         if (ret < 0) {
 137                 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
 138                         dev_err(sdev->dev,
 139                                 "error: %s: timeout for HIPCIE done\n",
 140                                 __func__);
 141                 goto err;
 142         }
 143
 144         /* set DONE bit to clear the reply IPC message */
 145         snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
 146                                        chip->ipc_ack,
 147                                        chip->ipc_ack_mask,
 148                                        chip->ipc_ack_mask);
 149
 150         /* step 5: power down corex */
 151         ret = hda_dsp_core_power_down(sdev, chip->host_managed_cores_mask & ~(BIT(0)));
 152         if (ret < 0) {
 153                 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
 154                         dev_err(sdev->dev,
 155                                 "error: dsp core x power down failed\n");
 156                 goto err;
 157         }
 158
 159         /* step 6: enable IPC interrupts */
 160         hda_dsp_ipc_int_enable(sdev);
 161
 162         /* step 7: wait for ROM init */
 163         ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
 164                                         HDA_DSP_SRAM_REG_ROM_STATUS, status,
 165                                         ((status & HDA_DSP_ROM_STS_MASK)
 166                                                 == HDA_DSP_ROM_INIT),
 167                                         HDA_DSP_REG_POLL_INTERVAL_US,
 168                                         chip->rom_init_timeout *
 169                                         USEC_PER_MSEC);
 170         if (!ret)
 171                 return 0;
 172
 173         if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
 174                 dev_err(sdev->dev,
 175                         "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
 176                         __func__);
 177
 178 err:
 179         flags = SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX;
 180
 181         /* force error log level after max boot attempts */
 182         if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
 183                 flags |= SOF_DBG_DUMP_FORCE_ERR_LEVEL;
 184
 185         hda_dsp_dump(sdev, flags);
 186         hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
 187
 188         return ret;
 189 }
 190
 191 static int cl_trigger(struct snd_sof_dev *sdev,
 192                       struct hdac_ext_stream *stream, int cmd)
 193 {
 194         struct hdac_stream *hstream = &stream->hstream;
 195         int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
 196
 197         /* code loader is special case that reuses stream ops */
 198         switch (cmd) {
 199         case SNDRV_PCM_TRIGGER_START:
 200                 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
 201                                         1 << hstream->index,
 202                                         1 << hstream->index);
 203
 204                 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
 205                                         sd_offset,
 206                                         SOF_HDA_SD_CTL_DMA_START |
 207                                         SOF_HDA_CL_DMA_SD_INT_MASK,
 208                                         SOF_HDA_SD_CTL_DMA_START |
 209                                         SOF_HDA_CL_DMA_SD_INT_MASK);
 210
 211                 hstream->running = true;
 212                 return 0;
 213         default:
 214                 return hda_dsp_stream_trigger(sdev, stream, cmd);
 215         }
 216 }
 217
 218 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
 219                       struct hdac_ext_stream *stream)
 220 {
 221         struct hdac_stream *hstream = &stream->hstream;
 222         int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
 223         int ret = 0;
 224
 225         if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
 226                 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
 227         else
 228                 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
 229                                         SOF_HDA_SD_CTL_DMA_START, 0);
 230
 231         hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag);
 232         hstream->running = 0;
 233         hstream->substream = NULL;
 234
 235         /* reset BDL address */
 236         snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
 237                           sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
 238         snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
 239                           sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
 240
 241         snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
 242         snd_dma_free_pages(dmab);
 243         dmab->area = NULL;
 244         hstream->bufsize = 0;
 245         hstream->format_val = 0;
 246
 247         return ret;
 248 }
 249
 250 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
 251 {
 252         unsigned int reg;
 253         int ret, status;
 254
 255         ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
 256         if (ret < 0) {
 257                 dev_err(sdev->dev, "error: DMA trigger start failed\n");
 258                 return ret;
 259         }
 260
 261         status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
 262                                         HDA_DSP_SRAM_REG_ROM_STATUS, reg,
 263                                         ((reg & HDA_DSP_ROM_STS_MASK)
 264                                                 == HDA_DSP_ROM_FW_ENTERED),
 265                                         HDA_DSP_REG_POLL_INTERVAL_US,
 266                                         HDA_DSP_BASEFW_TIMEOUT_US);
 267
 268         /*
 269          * even in case of errors we still need to stop the DMAs,
 270          * but we return the initial error should the DMA stop also fail
 271          */
 272
 273         if (status < 0) {
 274                 dev_err(sdev->dev,
 275                         "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
 276                         __func__);
 277         }
 278
 279         ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
 280         if (ret < 0) {
 281                 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
 282                 if (!status)
 283                         status = ret;
 284         }
 285
 286         return status;
 287 }
 288
 289 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
 290 {
 291         struct snd_sof_pdata *plat_data = sdev->pdata;
 292         struct hdac_ext_stream *iccmax_stream;
 293         struct hdac_bus *bus = sof_to_bus(sdev);
 294         struct firmware stripped_firmware;
 295         int ret, ret1;
 296         u8 original_gb;
 297
 298         /* save the original LTRP guardband value */
 299         original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK;
 300
 301         if (plat_data->fw->size <= plat_data->fw_offset) {
 302                 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
 303                 return -EINVAL;
 304         }
 305
 306         stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
 307
 308         /* prepare capture stream for ICCMAX */
 309         iccmax_stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
 310                                           &sdev->dmab_bdl, SNDRV_PCM_STREAM_CAPTURE);
 311         if (IS_ERR(iccmax_stream)) {
 312                 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
 313                 return PTR_ERR(iccmax_stream);
 314         }
 315
 316         ret = hda_dsp_cl_boot_firmware(sdev);
 317
 318         /*
 319          * Perform iccmax stream cleanup. This should be done even if firmware loading fails.
 320          * If the cleanup also fails, we return the initial error
 321          */
 322         ret1 = cl_cleanup(sdev, &sdev->dmab_bdl, iccmax_stream);
 323         if (ret1 < 0) {
 324                 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
 325
 326                 /* set return value to indicate cleanup failure */
 327                 if (!ret)
 328                         ret = ret1;
 329         }
 330
 331         /* restore the original guardband value after FW boot */
 332         snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb);
 333
 334         return ret;
 335 }
 336
 337 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
 338 {
 339         struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 340         struct snd_sof_pdata *plat_data = sdev->pdata;
 341         const struct sof_dev_desc *desc = plat_data->desc;
 342         const struct sof_intel_dsp_desc *chip_info;
 343         struct hdac_ext_stream *stream;
 344         struct firmware stripped_firmware;
 345         int ret, ret1, i;
 346
 347         chip_info = desc->chip_info;
 348
 349         if (plat_data->fw->size <= plat_data->fw_offset) {
 350                 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
 351                 return -EINVAL;
 352         }
 353
 354         stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset;
 355         stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
 356
 357         /* init for booting wait */
 358         init_waitqueue_head(&sdev->boot_wait);
 359
 360         /* prepare DMA for code loader stream */
 361         stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
 362                                    &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK);
 363         if (IS_ERR(stream)) {
 364                 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
 365                 return PTR_ERR(stream);
 366         }
 367
 368         memcpy(sdev->dmab.area, stripped_firmware.data,
 369                stripped_firmware.size);
 370
 371         /* try ROM init a few times before giving up */
 372         for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
 373                 dev_dbg(sdev->dev,
 374                         "Attempting iteration %d of Core En/ROM load...\n", i);
 375
 376                 hda->boot_iteration = i + 1;
 377                 ret = cl_dsp_init(sdev, stream->hstream.stream_tag);
 378
 379                 /* don't retry anymore if successful */
 380                 if (!ret)
 381                         break;
 382         }
 383
 384         if (i == HDA_FW_BOOT_ATTEMPTS) {
 385                 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
 386                         i, ret);
 387                 dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x\n",
 388                         snd_sof_dsp_read(sdev, HDA_DSP_BAR,
 389                                          HDA_DSP_SRAM_REG_ROM_ERROR),
 390                         snd_sof_dsp_read(sdev, HDA_DSP_BAR,
 391                                          HDA_DSP_SRAM_REG_ROM_STATUS));
 392                 goto cleanup;
 393         }
 394
 395         /*
 396          * When a SoundWire link is in clock stop state, a Slave
 397          * device may trigger in-band wakes for events such as jack
 398          * insertion or acoustic event detection. This event will lead
 399          * to a WAKEEN interrupt, handled by the PCI device and routed
 400          * to PME if the PCI device is in D3. The resume function in
 401          * audio PCI driver will be invoked by ACPI for PME event and
 402          * initialize the device and process WAKEEN interrupt.
 403          *
 404          * The WAKEEN interrupt should be processed ASAP to prevent an
 405          * interrupt flood, otherwise other interrupts, such IPC,
 406          * cannot work normally.  The WAKEEN is handled after the ROM
 407          * is initialized successfully, which ensures power rails are
 408          * enabled before accessing the SoundWire SHIM registers
 409          */
 410         if (!sdev->first_boot)
 411                 hda_sdw_process_wakeen(sdev);
 412
 413         /*
 414          * at this point DSP ROM has been initialized and
 415          * should be ready for code loading and firmware boot
 416          */
 417         ret = cl_copy_fw(sdev, stream);
 418         if (!ret) {
 419                 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
 420         } else {
 421                 hda_dsp_dump(sdev, SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX |
 422                              SOF_DBG_DUMP_FORCE_ERR_LEVEL);
 423                 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret);
 424         }
 425
 426 cleanup:
 427         /*
 428          * Perform codeloader stream cleanup.
 429          * This should be done even if firmware loading fails.
 430          * If the cleanup also fails, we return the initial error
 431          */
 432         ret1 = cl_cleanup(sdev, &sdev->dmab, stream);
 433         if (ret1 < 0) {
 434                 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
 435
 436                 /* set return value to indicate cleanup failure */
 437                 if (!ret)
 438                         ret = ret1;
 439         }
 440
 441         /*
 442          * return primary core id if both fw copy
 443          * and stream clean up are successful
 444          */
 445         if (!ret)
 446                 return chip_info->init_core_mask;
 447
 448         /* disable DSP */
 449         snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
 450                                 SOF_HDA_REG_PP_PPCTL,
 451                                 SOF_HDA_PPCTL_GPROCEN, 0);
 452         return ret;
 453 }
 454
 455 /* pre fw run operations */
 456 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
 457 {
 458         /* disable clock gating and power gating */
 459         return hda_dsp_ctrl_clock_power_gating(sdev, false);
 460 }
 461
 462 /* post fw run operations */
 463 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
 464 {
 465         int ret;
 466
 467         if (sdev->first_boot) {
 468                 ret = hda_sdw_startup(sdev);
 469                 if (ret < 0) {
 470                         dev_err(sdev->dev,
 471                                 "error: could not startup SoundWire links\n");
 472                         return ret;
 473                 }
 474         }
 475
 476         hda_sdw_int_enable(sdev, true);
 477
 478         /* re-enable clock gating and power gating */
 479         return hda_dsp_ctrl_clock_power_gating(sdev, true);
 480 }
 481
 482 /*
 483  * post fw run operations for ICL,
 484  * Core 3 will be powered up and in stall when HPRO is enabled
 485  */
 486 int hda_dsp_post_fw_run_icl(struct snd_sof_dev *sdev)
 487 {
 488         struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 489         int ret;
 490
 491         if (sdev->first_boot) {
 492                 ret = hda_sdw_startup(sdev);
 493                 if (ret < 0) {
 494                         dev_err(sdev->dev,
 495                                 "error: could not startup SoundWire links\n");
 496                         return ret;
 497                 }
 498         }
 499
 500         hda_sdw_int_enable(sdev, true);
 501
 502         /*
 503          * The recommended HW programming sequence for ICL is to
 504          * power up core 3 and keep it in stall if HPRO is enabled.
 505          * Major difference between ICL and TGL, on ICL core 3 is managed by
 506          * the host whereas on TGL it is handled by the firmware.
 507          */
 508         if (!hda->clk_config_lpro) {
 509                 ret = snd_sof_dsp_core_power_up(sdev, BIT(3));
 510                 if (ret < 0) {
 511                         dev_err(sdev->dev, "error: dsp core power up failed on core 3\n");
 512                         return ret;
 513                 }
 514
 515                 snd_sof_dsp_stall(sdev, BIT(3));
 516         }
 517
 518         /* re-enable clock gating and power gating */
 519         return hda_dsp_ctrl_clock_power_gating(sdev, true);
 520 }
 521
 522 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
 523                                          const struct sof_ext_man_elem_header *hdr)
 524 {
 525         const struct sof_ext_man_cavs_config_data *config_data =
 526                 container_of(hdr, struct sof_ext_man_cavs_config_data, hdr);
 527         struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 528         int i, elem_num;
 529
 530         /* calculate total number of config data elements */
 531         elem_num = (hdr->size - sizeof(struct sof_ext_man_elem_header))
 532                    / sizeof(struct sof_config_elem);
 533         if (elem_num <= 0) {
 534                 dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num);
 535                 return -EINVAL;
 536         }
 537
 538         for (i = 0; i < elem_num; i++)
 539                 switch (config_data->elems[i].token) {
 540                 case SOF_EXT_MAN_CAVS_CONFIG_EMPTY:
 541                         /* skip empty token */
 542                         break;
 543                 case SOF_EXT_MAN_CAVS_CONFIG_CAVS_LPRO:
 544                         hda->clk_config_lpro = config_data->elems[i].value;
 545                         dev_dbg(sdev->dev, "FW clock config: %s\n",
 546                                 hda->clk_config_lpro ? "LPRO" : "HPRO");
 547                         break;
 548                 case SOF_EXT_MAN_CAVS_CONFIG_OUTBOX_SIZE:
 549                 case SOF_EXT_MAN_CAVS_CONFIG_INBOX_SIZE:
 550                         /* These elements are defined but not being used yet. No warn is required */
 551                         break;
 552                 default:
 553                         dev_info(sdev->dev, "unsupported token type: %d\n",
 554                                  config_data->elems[i].token);
 555                 }
 556
 557         return 0;
 558 }
 559
 560 int hda_dsp_core_stall_icl(struct snd_sof_dev *sdev, unsigned int core_mask)
 561 {
 562         struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
 563         const struct sof_intel_dsp_desc *chip = hda->desc;
 564
 565         /* make sure core_mask in host managed cores */
 566         core_mask &= chip->host_managed_cores_mask;
 567         if (!core_mask) {
 568                 dev_err(sdev->dev, "error: core_mask is not in host managed cores\n");
 569                 return -EINVAL;
 570         }
 571
 572         /* stall core */
 573         snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
 574                                          HDA_DSP_REG_ADSPCS,
 575                                          HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
 576                                          HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
 577
 578         return 0;
 579 }