sound/soc/sof/intel/tgl.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 //
   3 // Copyright(c) 2020 Intel Corporation. All rights reserved.
   4 //
   5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
   6 //
   7
   8 /*
   9  * Hardware interface for audio DSP on Tigerlake.
  10  */
  11
  12 #include "../ops.h"
  13 #include "hda.h"
  14 #include "hda-ipc.h"
  15 #include "../sof-audio.h"
  16
  17 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
  18         {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
  19         {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
  20         {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
  21 };
  22
  23 /* Tigerlake ops */
  24 const struct snd_sof_dsp_ops sof_tgl_ops = {
  25         /* probe and remove */
  26         .probe          = hda_dsp_probe,
  27         .remove         = hda_dsp_remove,
  28
  29         /* Register IO */
  30         .write          = sof_io_write,
  31         .read           = sof_io_read,
  32         .write64        = sof_io_write64,
  33         .read64         = sof_io_read64,
  34
  35         /* Block IO */
  36         .block_read     = sof_block_read,
  37         .block_write    = sof_block_write,
  38
  39         /* doorbell */
  40         .irq_thread     = cnl_ipc_irq_thread,
  41
  42         /* ipc */
  43         .send_msg       = cnl_ipc_send_msg,
  44         .fw_ready       = sof_fw_ready,
  45         .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
  46         .get_window_offset = hda_dsp_ipc_get_window_offset,
  47
  48         .ipc_msg_data   = hda_ipc_msg_data,
  49         .ipc_pcm_params = hda_ipc_pcm_params,
  50
  51         /* machine driver */
  52         .machine_select = hda_machine_select,
  53         .machine_register = sof_machine_register,
  54         .machine_unregister = sof_machine_unregister,
  55         .set_mach_params = hda_set_mach_params,
  56
  57         /* debug */
  58         .debug_map      = tgl_dsp_debugfs,
  59         .debug_map_count        = ARRAY_SIZE(tgl_dsp_debugfs),
  60         .dbg_dump       = hda_dsp_dump,
  61         .ipc_dump       = cnl_ipc_dump,
  62
  63         /* stream callbacks */
  64         .pcm_open       = hda_dsp_pcm_open,
  65         .pcm_close      = hda_dsp_pcm_close,
  66         .pcm_hw_params  = hda_dsp_pcm_hw_params,
  67         .pcm_hw_free    = hda_dsp_stream_hw_free,
  68         .pcm_trigger    = hda_dsp_pcm_trigger,
  69         .pcm_pointer    = hda_dsp_pcm_pointer,
  70
  71 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
  72         /* probe callbacks */
  73         .probe_assign   = hda_probe_compr_assign,
  74         .probe_free     = hda_probe_compr_free,
  75         .probe_set_params       = hda_probe_compr_set_params,
  76         .probe_trigger  = hda_probe_compr_trigger,
  77         .probe_pointer  = hda_probe_compr_pointer,
  78 #endif
  79
  80         /* firmware loading */
  81         .load_firmware = snd_sof_load_firmware_raw,
  82
  83         /* pre/post fw run */
  84         .pre_fw_run = hda_dsp_pre_fw_run,
  85         .post_fw_run = hda_dsp_post_fw_run,
  86
  87         /* parse platform specific extended manifest */
  88         .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data,
  89
  90         /* dsp core power up/down */
  91         .core_power_up = hda_dsp_enable_core,
  92         .core_power_down = hda_dsp_core_reset_power_down,
  93
  94         /* firmware run */
  95         .run = hda_dsp_cl_boot_firmware_iccmax,
  96
  97         /* trace callback */
  98         .trace_init = hda_dsp_trace_init,
  99         .trace_release = hda_dsp_trace_release,
 100         .trace_trigger = hda_dsp_trace_trigger,
 101
 102         /* DAI drivers */
 103         .drv            = skl_dai,
 104         .num_drv        = SOF_SKL_NUM_DAIS,
 105
 106         /* PM */
 107         .suspend                = hda_dsp_suspend,
 108         .resume                 = hda_dsp_resume,
 109         .runtime_suspend        = hda_dsp_runtime_suspend,
 110         .runtime_resume         = hda_dsp_runtime_resume,
 111         .runtime_idle           = hda_dsp_runtime_idle,
 112         .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
 113         .set_power_state        = hda_dsp_set_power_state,
 114
 115         /* ALSA HW info flags */
 116         .hw_info =      SNDRV_PCM_INFO_MMAP |
 117                         SNDRV_PCM_INFO_MMAP_VALID |
 118                         SNDRV_PCM_INFO_INTERLEAVED |
 119                         SNDRV_PCM_INFO_PAUSE |
 120                         SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
 121
 122         .arch_ops = &sof_xtensa_arch_ops,
 123 };
 124 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
 125
 126 const struct sof_intel_dsp_desc tgl_chip_info = {
 127         /* Tigerlake */
 128         .cores_num = 4,
 129         .init_core_mask = 1,
 130         .host_managed_cores_mask = BIT(0),
 131         .ipc_req = CNL_DSP_REG_HIPCIDR,
 132         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 133         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 134         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 135         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 136         .rom_init_timeout       = 300,
 137         .ssp_count = ICL_SSP_COUNT,
 138         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 139 };
 140 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 141
 142 const struct sof_intel_dsp_desc tglh_chip_info = {
 143         /* Tigerlake-H */
 144         .cores_num = 2,
 145         .init_core_mask = 1,
 146         .host_managed_cores_mask = BIT(0),
 147         .ipc_req = CNL_DSP_REG_HIPCIDR,
 148         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 149         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 150         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 151         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 152         .rom_init_timeout       = 300,
 153         .ssp_count = ICL_SSP_COUNT,
 154         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 155 };
 156 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 157
 158 const struct sof_intel_dsp_desc adls_chip_info = {
 159         /* Alderlake-S */
 160         .cores_num = 2,
 161         .init_core_mask = BIT(0),
 162         .host_managed_cores_mask = BIT(0),
 163         .ipc_req = CNL_DSP_REG_HIPCIDR,
 164         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 165         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 166         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 167         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 168         .rom_init_timeout       = 300,
 169         .ssp_count = ICL_SSP_COUNT,
 170         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 171 };
 172 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);