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Merge tag 'powerpc-5.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[linux/fpc-iii.git] / tools / perf / util / intel-pt.c
blob60214de42f31bd380269940068d5bfd7be0fadae
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_pt.c: Intel Processor Trace support
4 * Copyright (c) 2013-2015, Intel Corporation.
5 */
6
7 #include <inttypes.h>
8 #include <stdio.h>
9 #include <stdbool.h>
10 #include <errno.h>
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/types.h>
14 #include <linux/zalloc.h>
15
16 #include "session.h"
17 #include "machine.h"
18 #include "memswap.h"
19 #include "sort.h"
20 #include "tool.h"
21 #include "event.h"
22 #include "evlist.h"
23 #include "evsel.h"
24 #include "map.h"
25 #include "color.h"
26 #include "thread.h"
27 #include "thread-stack.h"
28 #include "symbol.h"
29 #include "callchain.h"
30 #include "dso.h"
31 #include "debug.h"
32 #include "auxtrace.h"
33 #include "tsc.h"
34 #include "intel-pt.h"
35 #include "config.h"
36 #include "util/perf_api_probe.h"
37 #include "util/synthetic-events.h"
38 #include "time-utils.h"
39
40 #include "../arch/x86/include/uapi/asm/perf_regs.h"
41
42 #include "intel-pt-decoder/intel-pt-log.h"
43 #include "intel-pt-decoder/intel-pt-decoder.h"
44 #include "intel-pt-decoder/intel-pt-insn-decoder.h"
45 #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
46
47 #define MAX_TIMESTAMP (~0ULL)
48
49 struct range {
50 u64 start;
51 u64 end;
52 };
53
54 struct intel_pt {
55 struct auxtrace auxtrace;
56 struct auxtrace_queues queues;
57 struct auxtrace_heap heap;
58 u32 auxtrace_type;
59 struct perf_session *session;
60 struct machine *machine;
61 struct evsel *switch_evsel;
62 struct thread *unknown_thread;
63 bool timeless_decoding;
64 bool sampling_mode;
65 bool snapshot_mode;
66 bool per_cpu_mmaps;
67 bool have_tsc;
68 bool data_queued;
69 bool est_tsc;
70 bool sync_switch;
71 bool mispred_all;
72 bool use_thread_stack;
73 bool callstack;
74 unsigned int br_stack_sz;
75 unsigned int br_stack_sz_plus;
76 int have_sched_switch;
77 u32 pmu_type;
78 u64 kernel_start;
79 u64 switch_ip;
80 u64 ptss_ip;
81
82 struct perf_tsc_conversion tc;
83 bool cap_user_time_zero;
84
85 struct itrace_synth_opts synth_opts;
86
87 bool sample_instructions;
88 u64 instructions_sample_type;
89 u64 instructions_id;
90
91 bool sample_branches;
92 u32 branches_filter;
93 u64 branches_sample_type;
94 u64 branches_id;
95
96 bool sample_transactions;
97 u64 transactions_sample_type;
98 u64 transactions_id;
99
100 bool sample_ptwrites;
101 u64 ptwrites_sample_type;
102 u64 ptwrites_id;
103
104 bool sample_pwr_events;
105 u64 pwr_events_sample_type;
106 u64 mwait_id;
107 u64 pwre_id;
108 u64 exstop_id;
109 u64 pwrx_id;
110 u64 cbr_id;
111
112 bool sample_pebs;
113 struct evsel *pebs_evsel;
114
115 u64 tsc_bit;
116 u64 mtc_bit;
117 u64 mtc_freq_bits;
118 u32 tsc_ctc_ratio_n;
119 u32 tsc_ctc_ratio_d;
120 u64 cyc_bit;
121 u64 noretcomp_bit;
122 unsigned max_non_turbo_ratio;
123 unsigned cbr2khz;
124
125 unsigned long num_events;
126
127 char *filter;
128 struct addr_filters filts;
129
130 struct range *time_ranges;
131 unsigned int range_cnt;
132
133 struct ip_callchain *chain;
134 struct branch_stack *br_stack;
135 };
136
137 enum switch_state {
138 INTEL_PT_SS_NOT_TRACING,
139 INTEL_PT_SS_UNKNOWN,
140 INTEL_PT_SS_TRACING,
141 INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
142 INTEL_PT_SS_EXPECTING_SWITCH_IP,
143 };
144
145 struct intel_pt_queue {
146 struct intel_pt *pt;
147 unsigned int queue_nr;
148 struct auxtrace_buffer *buffer;
149 struct auxtrace_buffer *old_buffer;
150 void *decoder;
151 const struct intel_pt_state *state;
152 struct ip_callchain *chain;
153 struct branch_stack *last_branch;
154 union perf_event *event_buf;
155 bool on_heap;
156 bool stop;
157 bool step_through_buffers;
158 bool use_buffer_pid_tid;
159 bool sync_switch;
160 pid_t pid, tid;
161 int cpu;
162 int switch_state;
163 pid_t next_tid;
164 struct thread *thread;
165 bool exclude_kernel;
166 bool have_sample;
167 u64 time;
168 u64 timestamp;
169 u64 sel_timestamp;
170 bool sel_start;
171 unsigned int sel_idx;
172 u32 flags;
173 u16 insn_len;
174 u64 last_insn_cnt;
175 u64 ipc_insn_cnt;
176 u64 ipc_cyc_cnt;
177 u64 last_in_insn_cnt;
178 u64 last_in_cyc_cnt;
179 u64 last_br_insn_cnt;
180 u64 last_br_cyc_cnt;
181 unsigned int cbr_seen;
182 char insn[INTEL_PT_INSN_BUF_SZ];
183 };
184
185 static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
186 unsigned char *buf, size_t len)
187 {
188 struct intel_pt_pkt packet;
189 size_t pos = 0;
190 int ret, pkt_len, i;
191 char desc[INTEL_PT_PKT_DESC_MAX];
192 const char *color = PERF_COLOR_BLUE;
193 enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX;
194
195 color_fprintf(stdout, color,
196 ". ... Intel Processor Trace data: size %zu bytes\n",
197 len);
198
199 while (len) {
200 ret = intel_pt_get_packet(buf, len, &packet, &ctx);
201 if (ret > 0)
202 pkt_len = ret;
203 else
204 pkt_len = 1;
205 printf(".");
206 color_fprintf(stdout, color, " %08x: ", pos);
207 for (i = 0; i < pkt_len; i++)
208 color_fprintf(stdout, color, " %02x", buf[i]);
209 for (; i < 16; i++)
210 color_fprintf(stdout, color, " ");
211 if (ret > 0) {
212 ret = intel_pt_pkt_desc(&packet, desc,
213 INTEL_PT_PKT_DESC_MAX);
214 if (ret > 0)
215 color_fprintf(stdout, color, " %s\n", desc);
216 } else {
217 color_fprintf(stdout, color, " Bad packet!\n");
218 }
219 pos += pkt_len;
220 buf += pkt_len;
221 len -= pkt_len;
222 }
223 }
224
225 static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
226 size_t len)
227 {
228 printf(".\n");
229 intel_pt_dump(pt, buf, len);
230 }
231
232 static void intel_pt_log_event(union perf_event *event)
233 {
234 FILE *f = intel_pt_log_fp();
235
236 if (!intel_pt_enable_logging || !f)
237 return;
238
239 perf_event__fprintf(event, NULL, f);
240 }
241
242 static void intel_pt_dump_sample(struct perf_session *session,
243 struct perf_sample *sample)
244 {
245 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
246 auxtrace);
247
248 printf("\n");
249 intel_pt_dump(pt, sample->aux_sample.data, sample->aux_sample.size);
250 }
251
252 static bool intel_pt_log_events(struct intel_pt *pt, u64 tm)
253 {
254 struct perf_time_interval *range = pt->synth_opts.ptime_range;
255 int n = pt->synth_opts.range_num;
256
257 if (pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS)
258 return true;
259
260 if (pt->synth_opts.log_minus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS)
261 return false;
262
263 /* perf_time__ranges_skip_sample does not work if time is zero */
264 if (!tm)
265 tm = 1;
266
267 return !n || !perf_time__ranges_skip_sample(range, n, tm);
268 }
269
270 static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
271 struct auxtrace_buffer *b)
272 {
273 bool consecutive = false;
274 void *start;
275
276 start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
277 pt->have_tsc, &consecutive);
278 if (!start)
279 return -EINVAL;
280 b->use_size = b->data + b->size - start;
281 b->use_data = start;
282 if (b->use_size && consecutive)
283 b->consecutive = true;
284 return 0;
285 }
286
287 static int intel_pt_get_buffer(struct intel_pt_queue *ptq,
288 struct auxtrace_buffer *buffer,
289 struct auxtrace_buffer *old_buffer,
290 struct intel_pt_buffer *b)
291 {
292 bool might_overlap;
293
294 if (!buffer->data) {
295 int fd = perf_data__fd(ptq->pt->session->data);
296
297 buffer->data = auxtrace_buffer__get_data(buffer, fd);
298 if (!buffer->data)
299 return -ENOMEM;
300 }
301
302 might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
303 if (might_overlap && !buffer->consecutive && old_buffer &&
304 intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
305 return -ENOMEM;
306
307 if (buffer->use_data) {
308 b->len = buffer->use_size;
309 b->buf = buffer->use_data;
310 } else {
311 b->len = buffer->size;
312 b->buf = buffer->data;
313 }
314 b->ref_timestamp = buffer->reference;
315
316 if (!old_buffer || (might_overlap && !buffer->consecutive)) {
317 b->consecutive = false;
318 b->trace_nr = buffer->buffer_nr + 1;
319 } else {
320 b->consecutive = true;
321 }
322
323 return 0;
324 }
325
326 /* Do not drop buffers with references - refer intel_pt_get_trace() */
327 static void intel_pt_lookahead_drop_buffer(struct intel_pt_queue *ptq,
328 struct auxtrace_buffer *buffer)
329 {
330 if (!buffer || buffer == ptq->buffer || buffer == ptq->old_buffer)
331 return;
332
333 auxtrace_buffer__drop_data(buffer);
334 }
335
336 /* Must be serialized with respect to intel_pt_get_trace() */
337 static int intel_pt_lookahead(void *data, intel_pt_lookahead_cb_t cb,
338 void *cb_data)
339 {
340 struct intel_pt_queue *ptq = data;
341 struct auxtrace_buffer *buffer = ptq->buffer;
342 struct auxtrace_buffer *old_buffer = ptq->old_buffer;
343 struct auxtrace_queue *queue;
344 int err = 0;
345
346 queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
347
348 while (1) {
349 struct intel_pt_buffer b = { .len = 0 };
350
351 buffer = auxtrace_buffer__next(queue, buffer);
352 if (!buffer)
353 break;
354
355 err = intel_pt_get_buffer(ptq, buffer, old_buffer, &b);
356 if (err)
357 break;
358
359 if (b.len) {
360 intel_pt_lookahead_drop_buffer(ptq, old_buffer);
361 old_buffer = buffer;
362 } else {
363 intel_pt_lookahead_drop_buffer(ptq, buffer);
364 continue;
365 }
366
367 err = cb(&b, cb_data);
368 if (err)
369 break;
370 }
371
372 if (buffer != old_buffer)
373 intel_pt_lookahead_drop_buffer(ptq, buffer);
374 intel_pt_lookahead_drop_buffer(ptq, old_buffer);
375
376 return err;
377 }
378
379 /*
380 * This function assumes data is processed sequentially only.
381 * Must be serialized with respect to intel_pt_lookahead()
382 */
383 static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
384 {
385 struct intel_pt_queue *ptq = data;
386 struct auxtrace_buffer *buffer = ptq->buffer;
387 struct auxtrace_buffer *old_buffer = ptq->old_buffer;
388 struct auxtrace_queue *queue;
389 int err;
390
391 if (ptq->stop) {
392 b->len = 0;
393 return 0;
394 }
395
396 queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
397
398 buffer = auxtrace_buffer__next(queue, buffer);
399 if (!buffer) {
400 if (old_buffer)
401 auxtrace_buffer__drop_data(old_buffer);
402 b->len = 0;
403 return 0;
404 }
405
406 ptq->buffer = buffer;
407
408 err = intel_pt_get_buffer(ptq, buffer, old_buffer, b);
409 if (err)
410 return err;
411
412 if (ptq->step_through_buffers)
413 ptq->stop = true;
414
415 if (b->len) {
416 if (old_buffer)
417 auxtrace_buffer__drop_data(old_buffer);
418 ptq->old_buffer = buffer;
419 } else {
420 auxtrace_buffer__drop_data(buffer);
421 return intel_pt_get_trace(b, data);
422 }
423
424 return 0;
425 }
426
427 struct intel_pt_cache_entry {
428 struct auxtrace_cache_entry entry;
429 u64 insn_cnt;
430 u64 byte_cnt;
431 enum intel_pt_insn_op op;
432 enum intel_pt_insn_branch branch;
433 int length;
434 int32_t rel;
435 char insn[INTEL_PT_INSN_BUF_SZ];
436 };
437
438 static int intel_pt_config_div(const char *var, const char *value, void *data)
439 {
440 int *d = data;
441 long val;
442
443 if (!strcmp(var, "intel-pt.cache-divisor")) {
444 val = strtol(value, NULL, 0);
445 if (val > 0 && val <= INT_MAX)
446 *d = val;
447 }
448
449 return 0;
450 }
451
452 static int intel_pt_cache_divisor(void)
453 {
454 static int d;
455
456 if (d)
457 return d;
458
459 perf_config(intel_pt_config_div, &d);
460
461 if (!d)
462 d = 64;
463
464 return d;
465 }
466
467 static unsigned int intel_pt_cache_size(struct dso *dso,
468 struct machine *machine)
469 {
470 off_t size;
471
472 size = dso__data_size(dso, machine);
473 size /= intel_pt_cache_divisor();
474 if (size < 1000)
475 return 10;
476 if (size > (1 << 21))
477 return 21;
478 return 32 - __builtin_clz(size);
479 }
480
481 static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
482 struct machine *machine)
483 {
484 struct auxtrace_cache *c;
485 unsigned int bits;
486
487 if (dso->auxtrace_cache)
488 return dso->auxtrace_cache;
489
490 bits = intel_pt_cache_size(dso, machine);
491
492 /* Ignoring cache creation failure */
493 c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
494
495 dso->auxtrace_cache = c;
496
497 return c;
498 }
499
500 static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
501 u64 offset, u64 insn_cnt, u64 byte_cnt,
502 struct intel_pt_insn *intel_pt_insn)
503 {
504 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
505 struct intel_pt_cache_entry *e;
506 int err;
507
508 if (!c)
509 return -ENOMEM;
510
511 e = auxtrace_cache__alloc_entry(c);
512 if (!e)
513 return -ENOMEM;
514
515 e->insn_cnt = insn_cnt;
516 e->byte_cnt = byte_cnt;
517 e->op = intel_pt_insn->op;
518 e->branch = intel_pt_insn->branch;
519 e->length = intel_pt_insn->length;
520 e->rel = intel_pt_insn->rel;
521 memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
522
523 err = auxtrace_cache__add(c, offset, &e->entry);
524 if (err)
525 auxtrace_cache__free_entry(c, e);
526
527 return err;
528 }
529
530 static struct intel_pt_cache_entry *
531 intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
532 {
533 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
534
535 if (!c)
536 return NULL;
537
538 return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
539 }
540
541 static void intel_pt_cache_invalidate(struct dso *dso, struct machine *machine,
542 u64 offset)
543 {
544 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
545
546 if (!c)
547 return;
548
549 auxtrace_cache__remove(dso->auxtrace_cache, offset);
550 }
551
552 static inline u8 intel_pt_cpumode(struct intel_pt *pt, uint64_t ip)
553 {
554 return ip >= pt->kernel_start ?
555 PERF_RECORD_MISC_KERNEL :
556 PERF_RECORD_MISC_USER;
557 }
558
559 static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
560 uint64_t *insn_cnt_ptr, uint64_t *ip,
561 uint64_t to_ip, uint64_t max_insn_cnt,
562 void *data)
563 {
564 struct intel_pt_queue *ptq = data;
565 struct machine *machine = ptq->pt->machine;
566 struct thread *thread;
567 struct addr_location al;
568 unsigned char buf[INTEL_PT_INSN_BUF_SZ];
569 ssize_t len;
570 int x86_64;
571 u8 cpumode;
572 u64 offset, start_offset, start_ip;
573 u64 insn_cnt = 0;
574 bool one_map = true;
575
576 intel_pt_insn->length = 0;
577
578 if (to_ip && *ip == to_ip)
579 goto out_no_cache;
580
581 cpumode = intel_pt_cpumode(ptq->pt, *ip);
582
583 thread = ptq->thread;
584 if (!thread) {
585 if (cpumode != PERF_RECORD_MISC_KERNEL)
586 return -EINVAL;
587 thread = ptq->pt->unknown_thread;
588 }
589
590 while (1) {
591 if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso)
592 return -EINVAL;
593
594 if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
595 dso__data_status_seen(al.map->dso,
596 DSO_DATA_STATUS_SEEN_ITRACE))
597 return -ENOENT;
598
599 offset = al.map->map_ip(al.map, *ip);
600
601 if (!to_ip && one_map) {
602 struct intel_pt_cache_entry *e;
603
604 e = intel_pt_cache_lookup(al.map->dso, machine, offset);
605 if (e &&
606 (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
607 *insn_cnt_ptr = e->insn_cnt;
608 *ip += e->byte_cnt;
609 intel_pt_insn->op = e->op;
610 intel_pt_insn->branch = e->branch;
611 intel_pt_insn->length = e->length;
612 intel_pt_insn->rel = e->rel;
613 memcpy(intel_pt_insn->buf, e->insn,
614 INTEL_PT_INSN_BUF_SZ);
615 intel_pt_log_insn_no_data(intel_pt_insn, *ip);
616 return 0;
617 }
618 }
619
620 start_offset = offset;
621 start_ip = *ip;
622
623 /* Load maps to ensure dso->is_64_bit has been updated */
624 map__load(al.map);
625
626 x86_64 = al.map->dso->is_64_bit;
627
628 while (1) {
629 len = dso__data_read_offset(al.map->dso, machine,
630 offset, buf,
631 INTEL_PT_INSN_BUF_SZ);
632 if (len <= 0)
633 return -EINVAL;
634
635 if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
636 return -EINVAL;
637
638 intel_pt_log_insn(intel_pt_insn, *ip);
639
640 insn_cnt += 1;
641
642 if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
643 goto out;
644
645 if (max_insn_cnt && insn_cnt >= max_insn_cnt)
646 goto out_no_cache;
647
648 *ip += intel_pt_insn->length;
649
650 if (to_ip && *ip == to_ip)
651 goto out_no_cache;
652
653 if (*ip >= al.map->end)
654 break;
655
656 offset += intel_pt_insn->length;
657 }
658 one_map = false;
659 }
660 out:
661 *insn_cnt_ptr = insn_cnt;
662
663 if (!one_map)
664 goto out_no_cache;
665
666 /*
667 * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
668 * entries.
669 */
670 if (to_ip) {
671 struct intel_pt_cache_entry *e;
672
673 e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
674 if (e)
675 return 0;
676 }
677
678 /* Ignore cache errors */
679 intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
680 *ip - start_ip, intel_pt_insn);
681
682 return 0;
683
684 out_no_cache:
685 *insn_cnt_ptr = insn_cnt;
686 return 0;
687 }
688
689 static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
690 uint64_t offset, const char *filename)
691 {
692 struct addr_filter *filt;
693 bool have_filter = false;
694 bool hit_tracestop = false;
695 bool hit_filter = false;
696
697 list_for_each_entry(filt, &pt->filts.head, list) {
698 if (filt->start)
699 have_filter = true;
700
701 if ((filename && !filt->filename) ||
702 (!filename && filt->filename) ||
703 (filename && strcmp(filename, filt->filename)))
704 continue;
705
706 if (!(offset >= filt->addr && offset < filt->addr + filt->size))
707 continue;
708
709 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
710 ip, offset, filename ? filename : "[kernel]",
711 filt->start ? "filter" : "stop",
712 filt->addr, filt->size);
713
714 if (filt->start)
715 hit_filter = true;
716 else
717 hit_tracestop = true;
718 }
719
720 if (!hit_tracestop && !hit_filter)
721 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
722 ip, offset, filename ? filename : "[kernel]");
723
724 return hit_tracestop || (have_filter && !hit_filter);
725 }
726
727 static int __intel_pt_pgd_ip(uint64_t ip, void *data)
728 {
729 struct intel_pt_queue *ptq = data;
730 struct thread *thread;
731 struct addr_location al;
732 u8 cpumode;
733 u64 offset;
734
735 if (ip >= ptq->pt->kernel_start)
736 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
737
738 cpumode = PERF_RECORD_MISC_USER;
739
740 thread = ptq->thread;
741 if (!thread)
742 return -EINVAL;
743
744 if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
745 return -EINVAL;
746
747 offset = al.map->map_ip(al.map, ip);
748
749 return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
750 al.map->dso->long_name);
751 }
752
753 static bool intel_pt_pgd_ip(uint64_t ip, void *data)
754 {
755 return __intel_pt_pgd_ip(ip, data) > 0;
756 }
757
758 static bool intel_pt_get_config(struct intel_pt *pt,
759 struct perf_event_attr *attr, u64 *config)
760 {
761 if (attr->type == pt->pmu_type) {
762 if (config)
763 *config = attr->config;
764 return true;
765 }
766
767 return false;
768 }
769
770 static bool intel_pt_exclude_kernel(struct intel_pt *pt)
771 {
772 struct evsel *evsel;
773
774 evlist__for_each_entry(pt->session->evlist, evsel) {
775 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
776 !evsel->core.attr.exclude_kernel)
777 return false;
778 }
779 return true;
780 }
781
782 static bool intel_pt_return_compression(struct intel_pt *pt)
783 {
784 struct evsel *evsel;
785 u64 config;
786
787 if (!pt->noretcomp_bit)
788 return true;
789
790 evlist__for_each_entry(pt->session->evlist, evsel) {
791 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
792 (config & pt->noretcomp_bit))
793 return false;
794 }
795 return true;
796 }
797
798 static bool intel_pt_branch_enable(struct intel_pt *pt)
799 {
800 struct evsel *evsel;
801 u64 config;
802
803 evlist__for_each_entry(pt->session->evlist, evsel) {
804 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
805 (config & 1) && !(config & 0x2000))
806 return false;
807 }
808 return true;
809 }
810
811 static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
812 {
813 struct evsel *evsel;
814 unsigned int shift;
815 u64 config;
816
817 if (!pt->mtc_freq_bits)
818 return 0;
819
820 for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
821 config >>= 1;
822
823 evlist__for_each_entry(pt->session->evlist, evsel) {
824 if (intel_pt_get_config(pt, &evsel->core.attr, &config))
825 return (config & pt->mtc_freq_bits) >> shift;
826 }
827 return 0;
828 }
829
830 static bool intel_pt_timeless_decoding(struct intel_pt *pt)
831 {
832 struct evsel *evsel;
833 bool timeless_decoding = true;
834 u64 config;
835
836 if (!pt->tsc_bit || !pt->cap_user_time_zero)
837 return true;
838
839 evlist__for_each_entry(pt->session->evlist, evsel) {
840 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_TIME))
841 return true;
842 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
843 if (config & pt->tsc_bit)
844 timeless_decoding = false;
845 else
846 return true;
847 }
848 }
849 return timeless_decoding;
850 }
851
852 static bool intel_pt_tracing_kernel(struct intel_pt *pt)
853 {
854 struct evsel *evsel;
855
856 evlist__for_each_entry(pt->session->evlist, evsel) {
857 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
858 !evsel->core.attr.exclude_kernel)
859 return true;
860 }
861 return false;
862 }
863
864 static bool intel_pt_have_tsc(struct intel_pt *pt)
865 {
866 struct evsel *evsel;
867 bool have_tsc = false;
868 u64 config;
869
870 if (!pt->tsc_bit)
871 return false;
872
873 evlist__for_each_entry(pt->session->evlist, evsel) {
874 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
875 if (config & pt->tsc_bit)
876 have_tsc = true;
877 else
878 return false;
879 }
880 }
881 return have_tsc;
882 }
883
884 static bool intel_pt_sampling_mode(struct intel_pt *pt)
885 {
886 struct evsel *evsel;
887
888 evlist__for_each_entry(pt->session->evlist, evsel) {
889 if ((evsel->core.attr.sample_type & PERF_SAMPLE_AUX) &&
890 evsel->core.attr.aux_sample_size)
891 return true;
892 }
893 return false;
894 }
895
896 static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
897 {
898 u64 quot, rem;
899
900 quot = ns / pt->tc.time_mult;
901 rem = ns % pt->tc.time_mult;
902 return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
903 pt->tc.time_mult;
904 }
905
906 static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt)
907 {
908 size_t sz = sizeof(struct ip_callchain);
909
910 /* Add 1 to callchain_sz for callchain context */
911 sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64);
912 return zalloc(sz);
913 }
914
915 static int intel_pt_callchain_init(struct intel_pt *pt)
916 {
917 struct evsel *evsel;
918
919 evlist__for_each_entry(pt->session->evlist, evsel) {
920 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_CALLCHAIN))
921 evsel->synth_sample_type |= PERF_SAMPLE_CALLCHAIN;
922 }
923
924 pt->chain = intel_pt_alloc_chain(pt);
925 if (!pt->chain)
926 return -ENOMEM;
927
928 return 0;
929 }
930
931 static void intel_pt_add_callchain(struct intel_pt *pt,
932 struct perf_sample *sample)
933 {
934 struct thread *thread = machine__findnew_thread(pt->machine,
935 sample->pid,
936 sample->tid);
937
938 thread_stack__sample_late(thread, sample->cpu, pt->chain,
939 pt->synth_opts.callchain_sz + 1, sample->ip,
940 pt->kernel_start);
941
942 sample->callchain = pt->chain;
943 }
944
945 static struct branch_stack *intel_pt_alloc_br_stack(unsigned int entry_cnt)
946 {
947 size_t sz = sizeof(struct branch_stack);
948
949 sz += entry_cnt * sizeof(struct branch_entry);
950 return zalloc(sz);
951 }
952
953 static int intel_pt_br_stack_init(struct intel_pt *pt)
954 {
955 struct evsel *evsel;
956
957 evlist__for_each_entry(pt->session->evlist, evsel) {
958 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_BRANCH_STACK))
959 evsel->synth_sample_type |= PERF_SAMPLE_BRANCH_STACK;
960 }
961
962 pt->br_stack = intel_pt_alloc_br_stack(pt->br_stack_sz);
963 if (!pt->br_stack)
964 return -ENOMEM;
965
966 return 0;
967 }
968
969 static void intel_pt_add_br_stack(struct intel_pt *pt,
970 struct perf_sample *sample)
971 {
972 struct thread *thread = machine__findnew_thread(pt->machine,
973 sample->pid,
974 sample->tid);
975
976 thread_stack__br_sample_late(thread, sample->cpu, pt->br_stack,
977 pt->br_stack_sz, sample->ip,
978 pt->kernel_start);
979
980 sample->branch_stack = pt->br_stack;
981 }
982
983 /* INTEL_PT_LBR_0, INTEL_PT_LBR_1 and INTEL_PT_LBR_2 */
984 #define LBRS_MAX (INTEL_PT_BLK_ITEM_ID_CNT * 3U)
985
986 static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
987 unsigned int queue_nr)
988 {
989 struct intel_pt_params params = { .get_trace = 0, };
990 struct perf_env *env = pt->machine->env;
991 struct intel_pt_queue *ptq;
992
993 ptq = zalloc(sizeof(struct intel_pt_queue));
994 if (!ptq)
995 return NULL;
996
997 if (pt->synth_opts.callchain) {
998 ptq->chain = intel_pt_alloc_chain(pt);
999 if (!ptq->chain)
1000 goto out_free;
1001 }
1002
1003 if (pt->synth_opts.last_branch || pt->synth_opts.other_events) {
1004 unsigned int entry_cnt = max(LBRS_MAX, pt->br_stack_sz);
1005
1006 ptq->last_branch = intel_pt_alloc_br_stack(entry_cnt);
1007 if (!ptq->last_branch)
1008 goto out_free;
1009 }
1010
1011 ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
1012 if (!ptq->event_buf)
1013 goto out_free;
1014
1015 ptq->pt = pt;
1016 ptq->queue_nr = queue_nr;
1017 ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
1018 ptq->pid = -1;
1019 ptq->tid = -1;
1020 ptq->cpu = -1;
1021 ptq->next_tid = -1;
1022
1023 params.get_trace = intel_pt_get_trace;
1024 params.walk_insn = intel_pt_walk_next_insn;
1025 params.lookahead = intel_pt_lookahead;
1026 params.data = ptq;
1027 params.return_compression = intel_pt_return_compression(pt);
1028 params.branch_enable = intel_pt_branch_enable(pt);
1029 params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
1030 params.mtc_period = intel_pt_mtc_period(pt);
1031 params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
1032 params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
1033 params.quick = pt->synth_opts.quick;
1034
1035 if (pt->filts.cnt > 0)
1036 params.pgd_ip = intel_pt_pgd_ip;
1037
1038 if (pt->synth_opts.instructions) {
1039 if (pt->synth_opts.period) {
1040 switch (pt->synth_opts.period_type) {
1041 case PERF_ITRACE_PERIOD_INSTRUCTIONS:
1042 params.period_type =
1043 INTEL_PT_PERIOD_INSTRUCTIONS;
1044 params.period = pt->synth_opts.period;
1045 break;
1046 case PERF_ITRACE_PERIOD_TICKS:
1047 params.period_type = INTEL_PT_PERIOD_TICKS;
1048 params.period = pt->synth_opts.period;
1049 break;
1050 case PERF_ITRACE_PERIOD_NANOSECS:
1051 params.period_type = INTEL_PT_PERIOD_TICKS;
1052 params.period = intel_pt_ns_to_ticks(pt,
1053 pt->synth_opts.period);
1054 break;
1055 default:
1056 break;
1057 }
1058 }
1059
1060 if (!params.period) {
1061 params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
1062 params.period = 1;
1063 }
1064 }
1065
1066 if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
1067 params.flags |= INTEL_PT_FUP_WITH_NLIP;
1068
1069 ptq->decoder = intel_pt_decoder_new(&params);
1070 if (!ptq->decoder)
1071 goto out_free;
1072
1073 return ptq;
1074
1075 out_free:
1076 zfree(&ptq->event_buf);
1077 zfree(&ptq->last_branch);
1078 zfree(&ptq->chain);
1079 free(ptq);
1080 return NULL;
1081 }
1082
1083 static void intel_pt_free_queue(void *priv)
1084 {
1085 struct intel_pt_queue *ptq = priv;
1086
1087 if (!ptq)
1088 return;
1089 thread__zput(ptq->thread);
1090 intel_pt_decoder_free(ptq->decoder);
1091 zfree(&ptq->event_buf);
1092 zfree(&ptq->last_branch);
1093 zfree(&ptq->chain);
1094 free(ptq);
1095 }
1096
1097 static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
1098 struct auxtrace_queue *queue)
1099 {
1100 struct intel_pt_queue *ptq = queue->priv;
1101
1102 if (queue->tid == -1 || pt->have_sched_switch) {
1103 ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
1104 if (ptq->tid == -1)
1105 ptq->pid = -1;
1106 thread__zput(ptq->thread);
1107 }
1108
1109 if (!ptq->thread && ptq->tid != -1)
1110 ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
1111
1112 if (ptq->thread) {
1113 ptq->pid = ptq->thread->pid_;
1114 if (queue->cpu == -1)
1115 ptq->cpu = ptq->thread->cpu;
1116 }
1117 }
1118
1119 static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
1120 {
1121 if (ptq->state->flags & INTEL_PT_ABORT_TX) {
1122 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
1123 } else if (ptq->state->flags & INTEL_PT_ASYNC) {
1124 if (ptq->state->to_ip)
1125 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
1126 PERF_IP_FLAG_ASYNC |
1127 PERF_IP_FLAG_INTERRUPT;
1128 else
1129 ptq->flags = PERF_IP_FLAG_BRANCH |
1130 PERF_IP_FLAG_TRACE_END;
1131 ptq->insn_len = 0;
1132 } else {
1133 if (ptq->state->from_ip)
1134 ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
1135 else
1136 ptq->flags = PERF_IP_FLAG_BRANCH |
1137 PERF_IP_FLAG_TRACE_BEGIN;
1138 if (ptq->state->flags & INTEL_PT_IN_TX)
1139 ptq->flags |= PERF_IP_FLAG_IN_TX;
1140 ptq->insn_len = ptq->state->insn_len;
1141 memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
1142 }
1143
1144 if (ptq->state->type & INTEL_PT_TRACE_BEGIN)
1145 ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN;
1146 if (ptq->state->type & INTEL_PT_TRACE_END)
1147 ptq->flags |= PERF_IP_FLAG_TRACE_END;
1148 }
1149
1150 static void intel_pt_setup_time_range(struct intel_pt *pt,
1151 struct intel_pt_queue *ptq)
1152 {
1153 if (!pt->range_cnt)
1154 return;
1155
1156 ptq->sel_timestamp = pt->time_ranges[0].start;
1157 ptq->sel_idx = 0;
1158
1159 if (ptq->sel_timestamp) {
1160 ptq->sel_start = true;
1161 } else {
1162 ptq->sel_timestamp = pt->time_ranges[0].end;
1163 ptq->sel_start = false;
1164 }
1165 }
1166
1167 static int intel_pt_setup_queue(struct intel_pt *pt,
1168 struct auxtrace_queue *queue,
1169 unsigned int queue_nr)
1170 {
1171 struct intel_pt_queue *ptq = queue->priv;
1172
1173 if (list_empty(&queue->head))
1174 return 0;
1175
1176 if (!ptq) {
1177 ptq = intel_pt_alloc_queue(pt, queue_nr);
1178 if (!ptq)
1179 return -ENOMEM;
1180 queue->priv = ptq;
1181
1182 if (queue->cpu != -1)
1183 ptq->cpu = queue->cpu;
1184 ptq->tid = queue->tid;
1185
1186 ptq->cbr_seen = UINT_MAX;
1187
1188 if (pt->sampling_mode && !pt->snapshot_mode &&
1189 pt->timeless_decoding)
1190 ptq->step_through_buffers = true;
1191
1192 ptq->sync_switch = pt->sync_switch;
1193
1194 intel_pt_setup_time_range(pt, ptq);
1195 }
1196
1197 if (!ptq->on_heap &&
1198 (!ptq->sync_switch ||
1199 ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
1200 const struct intel_pt_state *state;
1201 int ret;
1202
1203 if (pt->timeless_decoding)
1204 return 0;
1205
1206 intel_pt_log("queue %u getting timestamp\n", queue_nr);
1207 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
1208 queue_nr, ptq->cpu, ptq->pid, ptq->tid);
1209
1210 if (ptq->sel_start && ptq->sel_timestamp) {
1211 ret = intel_pt_fast_forward(ptq->decoder,
1212 ptq->sel_timestamp);
1213 if (ret)
1214 return ret;
1215 }
1216
1217 while (1) {
1218 state = intel_pt_decode(ptq->decoder);
1219 if (state->err) {
1220 if (state->err == INTEL_PT_ERR_NODATA) {
1221 intel_pt_log("queue %u has no timestamp\n",
1222 queue_nr);
1223 return 0;
1224 }
1225 continue;
1226 }
1227 if (state->timestamp)
1228 break;
1229 }
1230
1231 ptq->timestamp = state->timestamp;
1232 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
1233 queue_nr, ptq->timestamp);
1234 ptq->state = state;
1235 ptq->have_sample = true;
1236 if (ptq->sel_start && ptq->sel_timestamp &&
1237 ptq->timestamp < ptq->sel_timestamp)
1238 ptq->have_sample = false;
1239 intel_pt_sample_flags(ptq);
1240 ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
1241 if (ret)
1242 return ret;
1243 ptq->on_heap = true;
1244 }
1245
1246 return 0;
1247 }
1248
1249 static int intel_pt_setup_queues(struct intel_pt *pt)
1250 {
1251 unsigned int i;
1252 int ret;
1253
1254 for (i = 0; i < pt->queues.nr_queues; i++) {
1255 ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
1256 if (ret)
1257 return ret;
1258 }
1259 return 0;
1260 }
1261
1262 static inline bool intel_pt_skip_event(struct intel_pt *pt)
1263 {
1264 return pt->synth_opts.initial_skip &&
1265 pt->num_events++ < pt->synth_opts.initial_skip;
1266 }
1267
1268 /*
1269 * Cannot count CBR as skipped because it won't go away until cbr == cbr_seen.
1270 * Also ensure CBR is first non-skipped event by allowing for 4 more samples
1271 * from this decoder state.
1272 */
1273 static inline bool intel_pt_skip_cbr_event(struct intel_pt *pt)
1274 {
1275 return pt->synth_opts.initial_skip &&
1276 pt->num_events + 4 < pt->synth_opts.initial_skip;
1277 }
1278
1279 static void intel_pt_prep_a_sample(struct intel_pt_queue *ptq,
1280 union perf_event *event,
1281 struct perf_sample *sample)
1282 {
1283 event->sample.header.type = PERF_RECORD_SAMPLE;
1284 event->sample.header.size = sizeof(struct perf_event_header);
1285
1286 sample->pid = ptq->pid;
1287 sample->tid = ptq->tid;
1288 sample->cpu = ptq->cpu;
1289 sample->insn_len = ptq->insn_len;
1290 memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
1291 }
1292
1293 static void intel_pt_prep_b_sample(struct intel_pt *pt,
1294 struct intel_pt_queue *ptq,
1295 union perf_event *event,
1296 struct perf_sample *sample)
1297 {
1298 intel_pt_prep_a_sample(ptq, event, sample);
1299
1300 if (!pt->timeless_decoding)
1301 sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
1302
1303 sample->ip = ptq->state->from_ip;
1304 sample->cpumode = intel_pt_cpumode(pt, sample->ip);
1305 sample->addr = ptq->state->to_ip;
1306 sample->period = 1;
1307 sample->flags = ptq->flags;
1308
1309 event->sample.header.misc = sample->cpumode;
1310 }
1311
1312 static int intel_pt_inject_event(union perf_event *event,
1313 struct perf_sample *sample, u64 type)
1314 {
1315 event->header.size = perf_event__sample_event_size(sample, type, 0);
1316 return perf_event__synthesize_sample(event, type, 0, sample);
1317 }
1318
1319 static inline int intel_pt_opt_inject(struct intel_pt *pt,
1320 union perf_event *event,
1321 struct perf_sample *sample, u64 type)
1322 {
1323 if (!pt->synth_opts.inject)
1324 return 0;
1325
1326 return intel_pt_inject_event(event, sample, type);
1327 }
1328
1329 static int intel_pt_deliver_synth_event(struct intel_pt *pt,
1330 union perf_event *event,
1331 struct perf_sample *sample, u64 type)
1332 {
1333 int ret;
1334
1335 ret = intel_pt_opt_inject(pt, event, sample, type);
1336 if (ret)
1337 return ret;
1338
1339 ret = perf_session__deliver_synth_event(pt->session, event, sample);
1340 if (ret)
1341 pr_err("Intel PT: failed to deliver event, error %d\n", ret);
1342
1343 return ret;
1344 }
1345
1346 static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
1347 {
1348 struct intel_pt *pt = ptq->pt;
1349 union perf_event *event = ptq->event_buf;
1350 struct perf_sample sample = { .ip = 0, };
1351 struct dummy_branch_stack {
1352 u64 nr;
1353 u64 hw_idx;
1354 struct branch_entry entries;
1355 } dummy_bs;
1356
1357 if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
1358 return 0;
1359
1360 if (intel_pt_skip_event(pt))
1361 return 0;
1362
1363 intel_pt_prep_b_sample(pt, ptq, event, &sample);
1364
1365 sample.id = ptq->pt->branches_id;
1366 sample.stream_id = ptq->pt->branches_id;
1367
1368 /*
1369 * perf report cannot handle events without a branch stack when using
1370 * SORT_MODE__BRANCH so make a dummy one.
1371 */
1372 if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
1373 dummy_bs = (struct dummy_branch_stack){
1374 .nr = 1,
1375 .hw_idx = -1ULL,
1376 .entries = {
1377 .from = sample.ip,
1378 .to = sample.addr,
1379 },
1380 };
1381 sample.branch_stack = (struct branch_stack *)&dummy_bs;
1382 }
1383
1384 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_br_cyc_cnt;
1385 if (sample.cyc_cnt) {
1386 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_br_insn_cnt;
1387 ptq->last_br_insn_cnt = ptq->ipc_insn_cnt;
1388 ptq->last_br_cyc_cnt = ptq->ipc_cyc_cnt;
1389 }
1390
1391 return intel_pt_deliver_synth_event(pt, event, &sample,
1392 pt->branches_sample_type);
1393 }
1394
1395 static void intel_pt_prep_sample(struct intel_pt *pt,
1396 struct intel_pt_queue *ptq,
1397 union perf_event *event,
1398 struct perf_sample *sample)
1399 {
1400 intel_pt_prep_b_sample(pt, ptq, event, sample);
1401
1402 if (pt->synth_opts.callchain) {
1403 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
1404 pt->synth_opts.callchain_sz + 1,
1405 sample->ip, pt->kernel_start);
1406 sample->callchain = ptq->chain;
1407 }
1408
1409 if (pt->synth_opts.last_branch) {
1410 thread_stack__br_sample(ptq->thread, ptq->cpu, ptq->last_branch,
1411 pt->br_stack_sz);
1412 sample->branch_stack = ptq->last_branch;
1413 }
1414 }
1415
1416 static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
1417 {
1418 struct intel_pt *pt = ptq->pt;
1419 union perf_event *event = ptq->event_buf;
1420 struct perf_sample sample = { .ip = 0, };
1421
1422 if (intel_pt_skip_event(pt))
1423 return 0;
1424
1425 intel_pt_prep_sample(pt, ptq, event, &sample);
1426
1427 sample.id = ptq->pt->instructions_id;
1428 sample.stream_id = ptq->pt->instructions_id;
1429 if (pt->synth_opts.quick)
1430 sample.period = 1;
1431 else
1432 sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
1433
1434 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_in_cyc_cnt;
1435 if (sample.cyc_cnt) {
1436 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_in_insn_cnt;
1437 ptq->last_in_insn_cnt = ptq->ipc_insn_cnt;
1438 ptq->last_in_cyc_cnt = ptq->ipc_cyc_cnt;
1439 }
1440
1441 ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
1442
1443 return intel_pt_deliver_synth_event(pt, event, &sample,
1444 pt->instructions_sample_type);
1445 }
1446
1447 static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
1448 {
1449 struct intel_pt *pt = ptq->pt;
1450 union perf_event *event = ptq->event_buf;
1451 struct perf_sample sample = { .ip = 0, };
1452
1453 if (intel_pt_skip_event(pt))
1454 return 0;
1455
1456 intel_pt_prep_sample(pt, ptq, event, &sample);
1457
1458 sample.id = ptq->pt->transactions_id;
1459 sample.stream_id = ptq->pt->transactions_id;
1460
1461 return intel_pt_deliver_synth_event(pt, event, &sample,
1462 pt->transactions_sample_type);
1463 }
1464
1465 static void intel_pt_prep_p_sample(struct intel_pt *pt,
1466 struct intel_pt_queue *ptq,
1467 union perf_event *event,
1468 struct perf_sample *sample)
1469 {
1470 intel_pt_prep_sample(pt, ptq, event, sample);
1471
1472 /*
1473 * Zero IP is used to mean "trace start" but that is not the case for
1474 * power or PTWRITE events with no IP, so clear the flags.
1475 */
1476 if (!sample->ip)
1477 sample->flags = 0;
1478 }
1479
1480 static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
1481 {
1482 struct intel_pt *pt = ptq->pt;
1483 union perf_event *event = ptq->event_buf;
1484 struct perf_sample sample = { .ip = 0, };
1485 struct perf_synth_intel_ptwrite raw;
1486
1487 if (intel_pt_skip_event(pt))
1488 return 0;
1489
1490 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1491
1492 sample.id = ptq->pt->ptwrites_id;
1493 sample.stream_id = ptq->pt->ptwrites_id;
1494
1495 raw.flags = 0;
1496 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
1497 raw.payload = cpu_to_le64(ptq->state->ptw_payload);
1498
1499 sample.raw_size = perf_synth__raw_size(raw);
1500 sample.raw_data = perf_synth__raw_data(&raw);
1501
1502 return intel_pt_deliver_synth_event(pt, event, &sample,
1503 pt->ptwrites_sample_type);
1504 }
1505
1506 static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
1507 {
1508 struct intel_pt *pt = ptq->pt;
1509 union perf_event *event = ptq->event_buf;
1510 struct perf_sample sample = { .ip = 0, };
1511 struct perf_synth_intel_cbr raw;
1512 u32 flags;
1513
1514 if (intel_pt_skip_cbr_event(pt))
1515 return 0;
1516
1517 ptq->cbr_seen = ptq->state->cbr;
1518
1519 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1520
1521 sample.id = ptq->pt->cbr_id;
1522 sample.stream_id = ptq->pt->cbr_id;
1523
1524 flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
1525 raw.flags = cpu_to_le32(flags);
1526 raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
1527 raw.reserved3 = 0;
1528
1529 sample.raw_size = perf_synth__raw_size(raw);
1530 sample.raw_data = perf_synth__raw_data(&raw);
1531
1532 return intel_pt_deliver_synth_event(pt, event, &sample,
1533 pt->pwr_events_sample_type);
1534 }
1535
1536 static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
1537 {
1538 struct intel_pt *pt = ptq->pt;
1539 union perf_event *event = ptq->event_buf;
1540 struct perf_sample sample = { .ip = 0, };
1541 struct perf_synth_intel_mwait raw;
1542
1543 if (intel_pt_skip_event(pt))
1544 return 0;
1545
1546 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1547
1548 sample.id = ptq->pt->mwait_id;
1549 sample.stream_id = ptq->pt->mwait_id;
1550
1551 raw.reserved = 0;
1552 raw.payload = cpu_to_le64(ptq->state->mwait_payload);
1553
1554 sample.raw_size = perf_synth__raw_size(raw);
1555 sample.raw_data = perf_synth__raw_data(&raw);
1556
1557 return intel_pt_deliver_synth_event(pt, event, &sample,
1558 pt->pwr_events_sample_type);
1559 }
1560
1561 static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
1562 {
1563 struct intel_pt *pt = ptq->pt;
1564 union perf_event *event = ptq->event_buf;
1565 struct perf_sample sample = { .ip = 0, };
1566 struct perf_synth_intel_pwre raw;
1567
1568 if (intel_pt_skip_event(pt))
1569 return 0;
1570
1571 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1572
1573 sample.id = ptq->pt->pwre_id;
1574 sample.stream_id = ptq->pt->pwre_id;
1575
1576 raw.reserved = 0;
1577 raw.payload = cpu_to_le64(ptq->state->pwre_payload);
1578
1579 sample.raw_size = perf_synth__raw_size(raw);
1580 sample.raw_data = perf_synth__raw_data(&raw);
1581
1582 return intel_pt_deliver_synth_event(pt, event, &sample,
1583 pt->pwr_events_sample_type);
1584 }
1585
1586 static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
1587 {
1588 struct intel_pt *pt = ptq->pt;
1589 union perf_event *event = ptq->event_buf;
1590 struct perf_sample sample = { .ip = 0, };
1591 struct perf_synth_intel_exstop raw;
1592
1593 if (intel_pt_skip_event(pt))
1594 return 0;
1595
1596 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1597
1598 sample.id = ptq->pt->exstop_id;
1599 sample.stream_id = ptq->pt->exstop_id;
1600
1601 raw.flags = 0;
1602 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
1603
1604 sample.raw_size = perf_synth__raw_size(raw);
1605 sample.raw_data = perf_synth__raw_data(&raw);
1606
1607 return intel_pt_deliver_synth_event(pt, event, &sample,
1608 pt->pwr_events_sample_type);
1609 }
1610
1611 static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
1612 {
1613 struct intel_pt *pt = ptq->pt;
1614 union perf_event *event = ptq->event_buf;
1615 struct perf_sample sample = { .ip = 0, };
1616 struct perf_synth_intel_pwrx raw;
1617
1618 if (intel_pt_skip_event(pt))
1619 return 0;
1620
1621 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1622
1623 sample.id = ptq->pt->pwrx_id;
1624 sample.stream_id = ptq->pt->pwrx_id;
1625
1626 raw.reserved = 0;
1627 raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
1628
1629 sample.raw_size = perf_synth__raw_size(raw);
1630 sample.raw_data = perf_synth__raw_data(&raw);
1631
1632 return intel_pt_deliver_synth_event(pt, event, &sample,
1633 pt->pwr_events_sample_type);
1634 }
1635
1636 /*
1637 * PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer
1638 * intel_pt_add_gp_regs().
1639 */
1640 static const int pebs_gp_regs[] = {
1641 [PERF_REG_X86_FLAGS] = 1,
1642 [PERF_REG_X86_IP] = 2,
1643 [PERF_REG_X86_AX] = 3,
1644 [PERF_REG_X86_CX] = 4,
1645 [PERF_REG_X86_DX] = 5,
1646 [PERF_REG_X86_BX] = 6,
1647 [PERF_REG_X86_SP] = 7,
1648 [PERF_REG_X86_BP] = 8,
1649 [PERF_REG_X86_SI] = 9,
1650 [PERF_REG_X86_DI] = 10,
1651 [PERF_REG_X86_R8] = 11,
1652 [PERF_REG_X86_R9] = 12,
1653 [PERF_REG_X86_R10] = 13,
1654 [PERF_REG_X86_R11] = 14,
1655 [PERF_REG_X86_R12] = 15,
1656 [PERF_REG_X86_R13] = 16,
1657 [PERF_REG_X86_R14] = 17,
1658 [PERF_REG_X86_R15] = 18,
1659 };
1660
1661 static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos,
1662 const struct intel_pt_blk_items *items,
1663 u64 regs_mask)
1664 {
1665 const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS];
1666 u32 mask = items->mask[INTEL_PT_GP_REGS_POS];
1667 u32 bit;
1668 int i;
1669
1670 for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) {
1671 /* Get the PEBS gp_regs array index */
1672 int n = pebs_gp_regs[i] - 1;
1673
1674 if (n < 0)
1675 continue;
1676 /*
1677 * Add only registers that were requested (i.e. 'regs_mask') and
1678 * that were provided (i.e. 'mask'), and update the resulting
1679 * mask (i.e. 'intr_regs->mask') accordingly.
1680 */
1681 if (mask & 1 << n && regs_mask & bit) {
1682 intr_regs->mask |= bit;
1683 *pos++ = gp_regs[n];
1684 }
1685 }
1686
1687 return pos;
1688 }
1689
1690 #ifndef PERF_REG_X86_XMM0
1691 #define PERF_REG_X86_XMM0 32
1692 #endif
1693
1694 static void intel_pt_add_xmm(struct regs_dump *intr_regs, u64 *pos,
1695 const struct intel_pt_blk_items *items,
1696 u64 regs_mask)
1697 {
1698 u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0);
1699 const u64 *xmm = items->xmm;
1700
1701 /*
1702 * If there are any XMM registers, then there should be all of them.
1703 * Nevertheless, follow the logic to add only registers that were
1704 * requested (i.e. 'regs_mask') and that were provided (i.e. 'mask'),
1705 * and update the resulting mask (i.e. 'intr_regs->mask') accordingly.
1706 */
1707 intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0;
1708
1709 for (; mask; mask >>= 1, xmm++) {
1710 if (mask & 1)
1711 *pos++ = *xmm;
1712 }
1713 }
1714
1715 #define LBR_INFO_MISPRED (1ULL << 63)
1716 #define LBR_INFO_IN_TX (1ULL << 62)
1717 #define LBR_INFO_ABORT (1ULL << 61)
1718 #define LBR_INFO_CYCLES 0xffff
1719
1720 /* Refer kernel's intel_pmu_store_pebs_lbrs() */
1721 static u64 intel_pt_lbr_flags(u64 info)
1722 {
1723 union {
1724 struct branch_flags flags;
1725 u64 result;
1726 } u;
1727
1728 u.result = 0;
1729 u.flags.mispred = !!(info & LBR_INFO_MISPRED);
1730 u.flags.predicted = !(info & LBR_INFO_MISPRED);
1731 u.flags.in_tx = !!(info & LBR_INFO_IN_TX);
1732 u.flags.abort = !!(info & LBR_INFO_ABORT);
1733 u.flags.cycles = info & LBR_INFO_CYCLES;
1734
1735 return u.result;
1736 }
1737
1738 static void intel_pt_add_lbrs(struct branch_stack *br_stack,
1739 const struct intel_pt_blk_items *items)
1740 {
1741 u64 *to;
1742 int i;
1743
1744 br_stack->nr = 0;
1745
1746 to = &br_stack->entries[0].from;
1747
1748 for (i = INTEL_PT_LBR_0_POS; i <= INTEL_PT_LBR_2_POS; i++) {
1749 u32 mask = items->mask[i];
1750 const u64 *from = items->val[i];
1751
1752 for (; mask; mask >>= 3, from += 3) {
1753 if ((mask & 7) == 7) {
1754 *to++ = from[0];
1755 *to++ = from[1];
1756 *to++ = intel_pt_lbr_flags(from[2]);
1757 br_stack->nr += 1;
1758 }
1759 }
1760 }
1761 }
1762
1763 static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq)
1764 {
1765 const struct intel_pt_blk_items *items = &ptq->state->items;
1766 struct perf_sample sample = { .ip = 0, };
1767 union perf_event *event = ptq->event_buf;
1768 struct intel_pt *pt = ptq->pt;
1769 struct evsel *evsel = pt->pebs_evsel;
1770 u64 sample_type = evsel->core.attr.sample_type;
1771 u64 id = evsel->core.id[0];
1772 u8 cpumode;
1773 u64 regs[8 * sizeof(sample.intr_regs.mask)];
1774
1775 if (intel_pt_skip_event(pt))
1776 return 0;
1777
1778 intel_pt_prep_a_sample(ptq, event, &sample);
1779
1780 sample.id = id;
1781 sample.stream_id = id;
1782
1783 if (!evsel->core.attr.freq)
1784 sample.period = evsel->core.attr.sample_period;
1785
1786 /* No support for non-zero CS base */
1787 if (items->has_ip)
1788 sample.ip = items->ip;
1789 else if (items->has_rip)
1790 sample.ip = items->rip;
1791 else
1792 sample.ip = ptq->state->from_ip;
1793
1794 /* No support for guest mode at this time */
1795 cpumode = sample.ip < ptq->pt->kernel_start ?
1796 PERF_RECORD_MISC_USER :
1797 PERF_RECORD_MISC_KERNEL;
1798
1799 event->sample.header.misc = cpumode | PERF_RECORD_MISC_EXACT_IP;
1800
1801 sample.cpumode = cpumode;
1802
1803 if (sample_type & PERF_SAMPLE_TIME) {
1804 u64 timestamp = 0;
1805
1806 if (items->has_timestamp)
1807 timestamp = items->timestamp;
1808 else if (!pt->timeless_decoding)
1809 timestamp = ptq->timestamp;
1810 if (timestamp)
1811 sample.time = tsc_to_perf_time(timestamp, &pt->tc);
1812 }
1813
1814 if (sample_type & PERF_SAMPLE_CALLCHAIN &&
1815 pt->synth_opts.callchain) {
1816 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
1817 pt->synth_opts.callchain_sz, sample.ip,
1818 pt->kernel_start);
1819 sample.callchain = ptq->chain;
1820 }
1821
1822 if (sample_type & PERF_SAMPLE_REGS_INTR &&
1823 (items->mask[INTEL_PT_GP_REGS_POS] ||
1824 items->mask[INTEL_PT_XMM_POS])) {
1825 u64 regs_mask = evsel->core.attr.sample_regs_intr;
1826 u64 *pos;
1827
1828 sample.intr_regs.abi = items->is_32_bit ?
1829 PERF_SAMPLE_REGS_ABI_32 :
1830 PERF_SAMPLE_REGS_ABI_64;
1831 sample.intr_regs.regs = regs;
1832
1833 pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask);
1834
1835 intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask);
1836 }
1837
1838 if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1839 if (items->mask[INTEL_PT_LBR_0_POS] ||
1840 items->mask[INTEL_PT_LBR_1_POS] ||
1841 items->mask[INTEL_PT_LBR_2_POS]) {
1842 intel_pt_add_lbrs(ptq->last_branch, items);
1843 } else if (pt->synth_opts.last_branch) {
1844 thread_stack__br_sample(ptq->thread, ptq->cpu,
1845 ptq->last_branch,
1846 pt->br_stack_sz);
1847 } else {
1848 ptq->last_branch->nr = 0;
1849 }
1850 sample.branch_stack = ptq->last_branch;
1851 }
1852
1853 if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address)
1854 sample.addr = items->mem_access_address;
1855
1856 if (sample_type & PERF_SAMPLE_WEIGHT) {
1857 /*
1858 * Refer kernel's setup_pebs_adaptive_sample_data() and
1859 * intel_hsw_weight().
1860 */
1861 if (items->has_mem_access_latency)
1862 sample.weight = items->mem_access_latency;
1863 if (!sample.weight && items->has_tsx_aux_info) {
1864 /* Cycles last block */
1865 sample.weight = (u32)items->tsx_aux_info;
1866 }
1867 }
1868
1869 if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) {
1870 u64 ax = items->has_rax ? items->rax : 0;
1871 /* Refer kernel's intel_hsw_transaction() */
1872 u64 txn = (u8)(items->tsx_aux_info >> 32);
1873
1874 /* For RTM XABORTs also log the abort code from AX */
1875 if (txn & PERF_TXN_TRANSACTION && ax & 1)
1876 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1877 sample.transaction = txn;
1878 }
1879
1880 return intel_pt_deliver_synth_event(pt, event, &sample, sample_type);
1881 }
1882
1883 static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
1884 pid_t pid, pid_t tid, u64 ip, u64 timestamp)
1885 {
1886 union perf_event event;
1887 char msg[MAX_AUXTRACE_ERROR_MSG];
1888 int err;
1889
1890 if (pt->synth_opts.error_minus_flags) {
1891 if (code == INTEL_PT_ERR_OVR &&
1892 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_OVERFLOW)
1893 return 0;
1894 if (code == INTEL_PT_ERR_LOST &&
1895 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_DATA_LOST)
1896 return 0;
1897 }
1898
1899 intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
1900
1901 auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
1902 code, cpu, pid, tid, ip, msg, timestamp);
1903
1904 err = perf_session__deliver_synth_event(pt->session, &event, NULL);
1905 if (err)
1906 pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
1907 err);
1908
1909 return err;
1910 }
1911
1912 static int intel_ptq_synth_error(struct intel_pt_queue *ptq,
1913 const struct intel_pt_state *state)
1914 {
1915 struct intel_pt *pt = ptq->pt;
1916 u64 tm = ptq->timestamp;
1917
1918 tm = pt->timeless_decoding ? 0 : tsc_to_perf_time(tm, &pt->tc);
1919
1920 return intel_pt_synth_error(pt, state->err, ptq->cpu, ptq->pid,
1921 ptq->tid, state->from_ip, tm);
1922 }
1923
1924 static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
1925 {
1926 struct auxtrace_queue *queue;
1927 pid_t tid = ptq->next_tid;
1928 int err;
1929
1930 if (tid == -1)
1931 return 0;
1932
1933 intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
1934
1935 err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
1936
1937 queue = &pt->queues.queue_array[ptq->queue_nr];
1938 intel_pt_set_pid_tid_cpu(pt, queue);
1939
1940 ptq->next_tid = -1;
1941
1942 return err;
1943 }
1944
1945 static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
1946 {
1947 struct intel_pt *pt = ptq->pt;
1948
1949 return ip == pt->switch_ip &&
1950 (ptq->flags & PERF_IP_FLAG_BRANCH) &&
1951 !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
1952 PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
1953 }
1954
1955 #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
1956 INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT)
1957
1958 static int intel_pt_sample(struct intel_pt_queue *ptq)
1959 {
1960 const struct intel_pt_state *state = ptq->state;
1961 struct intel_pt *pt = ptq->pt;
1962 int err;
1963
1964 if (!ptq->have_sample)
1965 return 0;
1966
1967 ptq->have_sample = false;
1968
1969 if (ptq->state->tot_cyc_cnt > ptq->ipc_cyc_cnt) {
1970 /*
1971 * Cycle count and instruction count only go together to create
1972 * a valid IPC ratio when the cycle count changes.
1973 */
1974 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt;
1975 ptq->ipc_cyc_cnt = ptq->state->tot_cyc_cnt;
1976 }
1977
1978 /*
1979 * Do PEBS first to allow for the possibility that the PEBS timestamp
1980 * precedes the current timestamp.
1981 */
1982 if (pt->sample_pebs && state->type & INTEL_PT_BLK_ITEMS) {
1983 err = intel_pt_synth_pebs_sample(ptq);
1984 if (err)
1985 return err;
1986 }
1987
1988 if (pt->sample_pwr_events) {
1989 if (ptq->state->cbr != ptq->cbr_seen) {
1990 err = intel_pt_synth_cbr_sample(ptq);
1991 if (err)
1992 return err;
1993 }
1994 if (state->type & INTEL_PT_PWR_EVT) {
1995 if (state->type & INTEL_PT_MWAIT_OP) {
1996 err = intel_pt_synth_mwait_sample(ptq);
1997 if (err)
1998 return err;
1999 }
2000 if (state->type & INTEL_PT_PWR_ENTRY) {
2001 err = intel_pt_synth_pwre_sample(ptq);
2002 if (err)
2003 return err;
2004 }
2005 if (state->type & INTEL_PT_EX_STOP) {
2006 err = intel_pt_synth_exstop_sample(ptq);
2007 if (err)
2008 return err;
2009 }
2010 if (state->type & INTEL_PT_PWR_EXIT) {
2011 err = intel_pt_synth_pwrx_sample(ptq);
2012 if (err)
2013 return err;
2014 }
2015 }
2016 }
2017
2018 if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
2019 err = intel_pt_synth_instruction_sample(ptq);
2020 if (err)
2021 return err;
2022 }
2023
2024 if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
2025 err = intel_pt_synth_transaction_sample(ptq);
2026 if (err)
2027 return err;
2028 }
2029
2030 if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
2031 err = intel_pt_synth_ptwrite_sample(ptq);
2032 if (err)
2033 return err;
2034 }
2035
2036 if (!(state->type & INTEL_PT_BRANCH))
2037 return 0;
2038
2039 if (pt->use_thread_stack) {
2040 thread_stack__event(ptq->thread, ptq->cpu, ptq->flags,
2041 state->from_ip, state->to_ip, ptq->insn_len,
2042 state->trace_nr, pt->callstack,
2043 pt->br_stack_sz_plus,
2044 pt->mispred_all);
2045 } else {
2046 thread_stack__set_trace_nr(ptq->thread, ptq->cpu, state->trace_nr);
2047 }
2048
2049 if (pt->sample_branches) {
2050 err = intel_pt_synth_branch_sample(ptq);
2051 if (err)
2052 return err;
2053 }
2054
2055 if (!ptq->sync_switch)
2056 return 0;
2057
2058 if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
2059 switch (ptq->switch_state) {
2060 case INTEL_PT_SS_NOT_TRACING:
2061 case INTEL_PT_SS_UNKNOWN:
2062 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2063 err = intel_pt_next_tid(pt, ptq);
2064 if (err)
2065 return err;
2066 ptq->switch_state = INTEL_PT_SS_TRACING;
2067 break;
2068 default:
2069 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
2070 return 1;
2071 }
2072 } else if (!state->to_ip) {
2073 ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
2074 } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
2075 ptq->switch_state = INTEL_PT_SS_UNKNOWN;
2076 } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
2077 state->to_ip == pt->ptss_ip &&
2078 (ptq->flags & PERF_IP_FLAG_CALL)) {
2079 ptq->switch_state = INTEL_PT_SS_TRACING;
2080 }
2081
2082 return 0;
2083 }
2084
2085 static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
2086 {
2087 struct machine *machine = pt->machine;
2088 struct map *map;
2089 struct symbol *sym, *start;
2090 u64 ip, switch_ip = 0;
2091 const char *ptss;
2092
2093 if (ptss_ip)
2094 *ptss_ip = 0;
2095
2096 map = machine__kernel_map(machine);
2097 if (!map)
2098 return 0;
2099
2100 if (map__load(map))
2101 return 0;
2102
2103 start = dso__first_symbol(map->dso);
2104
2105 for (sym = start; sym; sym = dso__next_symbol(sym)) {
2106 if (sym->binding == STB_GLOBAL &&
2107 !strcmp(sym->name, "__switch_to")) {
2108 ip = map->unmap_ip(map, sym->start);
2109 if (ip >= map->start && ip < map->end) {
2110 switch_ip = ip;
2111 break;
2112 }
2113 }
2114 }
2115
2116 if (!switch_ip || !ptss_ip)
2117 return 0;
2118
2119 if (pt->have_sched_switch == 1)
2120 ptss = "perf_trace_sched_switch";
2121 else
2122 ptss = "__perf_event_task_sched_out";
2123
2124 for (sym = start; sym; sym = dso__next_symbol(sym)) {
2125 if (!strcmp(sym->name, ptss)) {
2126 ip = map->unmap_ip(map, sym->start);
2127 if (ip >= map->start && ip < map->end) {
2128 *ptss_ip = ip;
2129 break;
2130 }
2131 }
2132 }
2133
2134 return switch_ip;
2135 }
2136
2137 static void intel_pt_enable_sync_switch(struct intel_pt *pt)
2138 {
2139 unsigned int i;
2140
2141 pt->sync_switch = true;
2142
2143 for (i = 0; i < pt->queues.nr_queues; i++) {
2144 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
2145 struct intel_pt_queue *ptq = queue->priv;
2146
2147 if (ptq)
2148 ptq->sync_switch = true;
2149 }
2150 }
2151
2152 /*
2153 * To filter against time ranges, it is only necessary to look at the next start
2154 * or end time.
2155 */
2156 static bool intel_pt_next_time(struct intel_pt_queue *ptq)
2157 {
2158 struct intel_pt *pt = ptq->pt;
2159
2160 if (ptq->sel_start) {
2161 /* Next time is an end time */
2162 ptq->sel_start = false;
2163 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].end;
2164 return true;
2165 } else if (ptq->sel_idx + 1 < pt->range_cnt) {
2166 /* Next time is a start time */
2167 ptq->sel_start = true;
2168 ptq->sel_idx += 1;
2169 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].start;
2170 return true;
2171 }
2172
2173 /* No next time */
2174 return false;
2175 }
2176
2177 static int intel_pt_time_filter(struct intel_pt_queue *ptq, u64 *ff_timestamp)
2178 {
2179 int err;
2180
2181 while (1) {
2182 if (ptq->sel_start) {
2183 if (ptq->timestamp >= ptq->sel_timestamp) {
2184 /* After start time, so consider next time */
2185 intel_pt_next_time(ptq);
2186 if (!ptq->sel_timestamp) {
2187 /* No end time */
2188 return 0;
2189 }
2190 /* Check against end time */
2191 continue;
2192 }
2193 /* Before start time, so fast forward */
2194 ptq->have_sample = false;
2195 if (ptq->sel_timestamp > *ff_timestamp) {
2196 if (ptq->sync_switch) {
2197 intel_pt_next_tid(ptq->pt, ptq);
2198 ptq->switch_state = INTEL_PT_SS_UNKNOWN;
2199 }
2200 *ff_timestamp = ptq->sel_timestamp;
2201 err = intel_pt_fast_forward(ptq->decoder,
2202 ptq->sel_timestamp);
2203 if (err)
2204 return err;
2205 }
2206 return 0;
2207 } else if (ptq->timestamp > ptq->sel_timestamp) {
2208 /* After end time, so consider next time */
2209 if (!intel_pt_next_time(ptq)) {
2210 /* No next time range, so stop decoding */
2211 ptq->have_sample = false;
2212 ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
2213 return 1;
2214 }
2215 /* Check against next start time */
2216 continue;
2217 } else {
2218 /* Before end time */
2219 return 0;
2220 }
2221 }
2222 }
2223
2224 static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
2225 {
2226 const struct intel_pt_state *state = ptq->state;
2227 struct intel_pt *pt = ptq->pt;
2228 u64 ff_timestamp = 0;
2229 int err;
2230
2231 if (!pt->kernel_start) {
2232 pt->kernel_start = machine__kernel_start(pt->machine);
2233 if (pt->per_cpu_mmaps &&
2234 (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
2235 !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
2236 !pt->sampling_mode) {
2237 pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
2238 if (pt->switch_ip) {
2239 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
2240 pt->switch_ip, pt->ptss_ip);
2241 intel_pt_enable_sync_switch(pt);
2242 }
2243 }
2244 }
2245
2246 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
2247 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
2248 while (1) {
2249 err = intel_pt_sample(ptq);
2250 if (err)
2251 return err;
2252
2253 state = intel_pt_decode(ptq->decoder);
2254 if (state->err) {
2255 if (state->err == INTEL_PT_ERR_NODATA)
2256 return 1;
2257 if (ptq->sync_switch &&
2258 state->from_ip >= pt->kernel_start) {
2259 ptq->sync_switch = false;
2260 intel_pt_next_tid(pt, ptq);
2261 }
2262 if (pt->synth_opts.errors) {
2263 err = intel_ptq_synth_error(ptq, state);
2264 if (err)
2265 return err;
2266 }
2267 continue;
2268 }
2269
2270 ptq->state = state;
2271 ptq->have_sample = true;
2272 intel_pt_sample_flags(ptq);
2273
2274 /* Use estimated TSC upon return to user space */
2275 if (pt->est_tsc &&
2276 (state->from_ip >= pt->kernel_start || !state->from_ip) &&
2277 state->to_ip && state->to_ip < pt->kernel_start) {
2278 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
2279 state->timestamp, state->est_timestamp);
2280 ptq->timestamp = state->est_timestamp;
2281 /* Use estimated TSC in unknown switch state */
2282 } else if (ptq->sync_switch &&
2283 ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
2284 intel_pt_is_switch_ip(ptq, state->to_ip) &&
2285 ptq->next_tid == -1) {
2286 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
2287 state->timestamp, state->est_timestamp);
2288 ptq->timestamp = state->est_timestamp;
2289 } else if (state->timestamp > ptq->timestamp) {
2290 ptq->timestamp = state->timestamp;
2291 }
2292
2293 if (ptq->sel_timestamp) {
2294 err = intel_pt_time_filter(ptq, &ff_timestamp);
2295 if (err)
2296 return err;
2297 }
2298
2299 if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
2300 *timestamp = ptq->timestamp;
2301 return 0;
2302 }
2303 }
2304 return 0;
2305 }
2306
2307 static inline int intel_pt_update_queues(struct intel_pt *pt)
2308 {
2309 if (pt->queues.new_data) {
2310 pt->queues.new_data = false;
2311 return intel_pt_setup_queues(pt);
2312 }
2313 return 0;
2314 }
2315
2316 static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
2317 {
2318 unsigned int queue_nr;
2319 u64 ts;
2320 int ret;
2321
2322 while (1) {
2323 struct auxtrace_queue *queue;
2324 struct intel_pt_queue *ptq;
2325
2326 if (!pt->heap.heap_cnt)
2327 return 0;
2328
2329 if (pt->heap.heap_array[0].ordinal >= timestamp)
2330 return 0;
2331
2332 queue_nr = pt->heap.heap_array[0].queue_nr;
2333 queue = &pt->queues.queue_array[queue_nr];
2334 ptq = queue->priv;
2335
2336 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
2337 queue_nr, pt->heap.heap_array[0].ordinal,
2338 timestamp);
2339
2340 auxtrace_heap__pop(&pt->heap);
2341
2342 if (pt->heap.heap_cnt) {
2343 ts = pt->heap.heap_array[0].ordinal + 1;
2344 if (ts > timestamp)
2345 ts = timestamp;
2346 } else {
2347 ts = timestamp;
2348 }
2349
2350 intel_pt_set_pid_tid_cpu(pt, queue);
2351
2352 ret = intel_pt_run_decoder(ptq, &ts);
2353
2354 if (ret < 0) {
2355 auxtrace_heap__add(&pt->heap, queue_nr, ts);
2356 return ret;
2357 }
2358
2359 if (!ret) {
2360 ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
2361 if (ret < 0)
2362 return ret;
2363 } else {
2364 ptq->on_heap = false;
2365 }
2366 }
2367
2368 return 0;
2369 }
2370
2371 static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
2372 u64 time_)
2373 {
2374 struct auxtrace_queues *queues = &pt->queues;
2375 unsigned int i;
2376 u64 ts = 0;
2377
2378 for (i = 0; i < queues->nr_queues; i++) {
2379 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
2380 struct intel_pt_queue *ptq = queue->priv;
2381
2382 if (ptq && (tid == -1 || ptq->tid == tid)) {
2383 ptq->time = time_;
2384 intel_pt_set_pid_tid_cpu(pt, queue);
2385 intel_pt_run_decoder(ptq, &ts);
2386 }
2387 }
2388 return 0;
2389 }
2390
2391 static void intel_pt_sample_set_pid_tid_cpu(struct intel_pt_queue *ptq,
2392 struct auxtrace_queue *queue,
2393 struct perf_sample *sample)
2394 {
2395 struct machine *m = ptq->pt->machine;
2396
2397 ptq->pid = sample->pid;
2398 ptq->tid = sample->tid;
2399 ptq->cpu = queue->cpu;
2400
2401 intel_pt_log("queue %u cpu %d pid %d tid %d\n",
2402 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
2403
2404 thread__zput(ptq->thread);
2405
2406 if (ptq->tid == -1)
2407 return;
2408
2409 if (ptq->pid == -1) {
2410 ptq->thread = machine__find_thread(m, -1, ptq->tid);
2411 if (ptq->thread)
2412 ptq->pid = ptq->thread->pid_;
2413 return;
2414 }
2415
2416 ptq->thread = machine__findnew_thread(m, ptq->pid, ptq->tid);
2417 }
2418
2419 static int intel_pt_process_timeless_sample(struct intel_pt *pt,
2420 struct perf_sample *sample)
2421 {
2422 struct auxtrace_queue *queue;
2423 struct intel_pt_queue *ptq;
2424 u64 ts = 0;
2425
2426 queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session);
2427 if (!queue)
2428 return -EINVAL;
2429
2430 ptq = queue->priv;
2431 if (!ptq)
2432 return 0;
2433
2434 ptq->stop = false;
2435 ptq->time = sample->time;
2436 intel_pt_sample_set_pid_tid_cpu(ptq, queue, sample);
2437 intel_pt_run_decoder(ptq, &ts);
2438 return 0;
2439 }
2440
2441 static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
2442 {
2443 return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
2444 sample->pid, sample->tid, 0, sample->time);
2445 }
2446
2447 static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
2448 {
2449 unsigned i, j;
2450
2451 if (cpu < 0 || !pt->queues.nr_queues)
2452 return NULL;
2453
2454 if ((unsigned)cpu >= pt->queues.nr_queues)
2455 i = pt->queues.nr_queues - 1;
2456 else
2457 i = cpu;
2458
2459 if (pt->queues.queue_array[i].cpu == cpu)
2460 return pt->queues.queue_array[i].priv;
2461
2462 for (j = 0; i > 0; j++) {
2463 if (pt->queues.queue_array[--i].cpu == cpu)
2464 return pt->queues.queue_array[i].priv;
2465 }
2466
2467 for (; j < pt->queues.nr_queues; j++) {
2468 if (pt->queues.queue_array[j].cpu == cpu)
2469 return pt->queues.queue_array[j].priv;
2470 }
2471
2472 return NULL;
2473 }
2474
2475 static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
2476 u64 timestamp)
2477 {
2478 struct intel_pt_queue *ptq;
2479 int err;
2480
2481 if (!pt->sync_switch)
2482 return 1;
2483
2484 ptq = intel_pt_cpu_to_ptq(pt, cpu);
2485 if (!ptq || !ptq->sync_switch)
2486 return 1;
2487
2488 switch (ptq->switch_state) {
2489 case INTEL_PT_SS_NOT_TRACING:
2490 break;
2491 case INTEL_PT_SS_UNKNOWN:
2492 case INTEL_PT_SS_TRACING:
2493 ptq->next_tid = tid;
2494 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
2495 return 0;
2496 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
2497 if (!ptq->on_heap) {
2498 ptq->timestamp = perf_time_to_tsc(timestamp,
2499 &pt->tc);
2500 err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
2501 ptq->timestamp);
2502 if (err)
2503 return err;
2504 ptq->on_heap = true;
2505 }
2506 ptq->switch_state = INTEL_PT_SS_TRACING;
2507 break;
2508 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2509 intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
2510 break;
2511 default:
2512 break;
2513 }
2514
2515 ptq->next_tid = -1;
2516
2517 return 1;
2518 }
2519
2520 static int intel_pt_process_switch(struct intel_pt *pt,
2521 struct perf_sample *sample)
2522 {
2523 pid_t tid;
2524 int cpu, ret;
2525 struct evsel *evsel = evlist__id2evsel(pt->session->evlist, sample->id);
2526
2527 if (evsel != pt->switch_evsel)
2528 return 0;
2529
2530 tid = evsel__intval(evsel, sample, "next_pid");
2531 cpu = sample->cpu;
2532
2533 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
2534 cpu, tid, sample->time, perf_time_to_tsc(sample->time,
2535 &pt->tc));
2536
2537 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
2538 if (ret <= 0)
2539 return ret;
2540
2541 return machine__set_current_tid(pt->machine, cpu, -1, tid);
2542 }
2543
2544 static int intel_pt_context_switch_in(struct intel_pt *pt,
2545 struct perf_sample *sample)
2546 {
2547 pid_t pid = sample->pid;
2548 pid_t tid = sample->tid;
2549 int cpu = sample->cpu;
2550
2551 if (pt->sync_switch) {
2552 struct intel_pt_queue *ptq;
2553
2554 ptq = intel_pt_cpu_to_ptq(pt, cpu);
2555 if (ptq && ptq->sync_switch) {
2556 ptq->next_tid = -1;
2557 switch (ptq->switch_state) {
2558 case INTEL_PT_SS_NOT_TRACING:
2559 case INTEL_PT_SS_UNKNOWN:
2560 case INTEL_PT_SS_TRACING:
2561 break;
2562 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
2563 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2564 ptq->switch_state = INTEL_PT_SS_TRACING;
2565 break;
2566 default:
2567 break;
2568 }
2569 }
2570 }
2571
2572 /*
2573 * If the current tid has not been updated yet, ensure it is now that
2574 * a "switch in" event has occurred.
2575 */
2576 if (machine__get_current_tid(pt->machine, cpu) == tid)
2577 return 0;
2578
2579 return machine__set_current_tid(pt->machine, cpu, pid, tid);
2580 }
2581
2582 static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
2583 struct perf_sample *sample)
2584 {
2585 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
2586 pid_t pid, tid;
2587 int cpu, ret;
2588
2589 cpu = sample->cpu;
2590
2591 if (pt->have_sched_switch == 3) {
2592 if (!out)
2593 return intel_pt_context_switch_in(pt, sample);
2594 if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
2595 pr_err("Expecting CPU-wide context switch event\n");
2596 return -EINVAL;
2597 }
2598 pid = event->context_switch.next_prev_pid;
2599 tid = event->context_switch.next_prev_tid;
2600 } else {
2601 if (out)
2602 return 0;
2603 pid = sample->pid;
2604 tid = sample->tid;
2605 }
2606
2607 if (tid == -1)
2608 intel_pt_log("context_switch event has no tid\n");
2609
2610 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
2611 if (ret <= 0)
2612 return ret;
2613
2614 return machine__set_current_tid(pt->machine, cpu, pid, tid);
2615 }
2616
2617 static int intel_pt_process_itrace_start(struct intel_pt *pt,
2618 union perf_event *event,
2619 struct perf_sample *sample)
2620 {
2621 if (!pt->per_cpu_mmaps)
2622 return 0;
2623
2624 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
2625 sample->cpu, event->itrace_start.pid,
2626 event->itrace_start.tid, sample->time,
2627 perf_time_to_tsc(sample->time, &pt->tc));
2628
2629 return machine__set_current_tid(pt->machine, sample->cpu,
2630 event->itrace_start.pid,
2631 event->itrace_start.tid);
2632 }
2633
2634 static int intel_pt_find_map(struct thread *thread, u8 cpumode, u64 addr,
2635 struct addr_location *al)
2636 {
2637 if (!al->map || addr < al->map->start || addr >= al->map->end) {
2638 if (!thread__find_map(thread, cpumode, addr, al))
2639 return -1;
2640 }
2641
2642 return 0;
2643 }
2644
2645 /* Invalidate all instruction cache entries that overlap the text poke */
2646 static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event)
2647 {
2648 u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK;
2649 u64 addr = event->text_poke.addr + event->text_poke.new_len - 1;
2650 /* Assume text poke begins in a basic block no more than 4096 bytes */
2651 int cnt = 4096 + event->text_poke.new_len;
2652 struct thread *thread = pt->unknown_thread;
2653 struct addr_location al = { .map = NULL };
2654 struct machine *machine = pt->machine;
2655 struct intel_pt_cache_entry *e;
2656 u64 offset;
2657
2658 if (!event->text_poke.new_len)
2659 return 0;
2660
2661 for (; cnt; cnt--, addr--) {
2662 if (intel_pt_find_map(thread, cpumode, addr, &al)) {
2663 if (addr < event->text_poke.addr)
2664 return 0;
2665 continue;
2666 }
2667
2668 if (!al.map->dso || !al.map->dso->auxtrace_cache)
2669 continue;
2670
2671 offset = al.map->map_ip(al.map, addr);
2672
2673 e = intel_pt_cache_lookup(al.map->dso, machine, offset);
2674 if (!e)
2675 continue;
2676
2677 if (addr + e->byte_cnt + e->length <= event->text_poke.addr) {
2678 /*
2679 * No overlap. Working backwards there cannot be another
2680 * basic block that overlaps the text poke if there is a
2681 * branch instruction before the text poke address.
2682 */
2683 if (e->branch != INTEL_PT_BR_NO_BRANCH)
2684 return 0;
2685 } else {
2686 intel_pt_cache_invalidate(al.map->dso, machine, offset);
2687 intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n",
2688 al.map->dso->long_name, addr);
2689 }
2690 }
2691
2692 return 0;
2693 }
2694
2695 static int intel_pt_process_event(struct perf_session *session,
2696 union perf_event *event,
2697 struct perf_sample *sample,
2698 struct perf_tool *tool)
2699 {
2700 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2701 auxtrace);
2702 u64 timestamp;
2703 int err = 0;
2704
2705 if (dump_trace)
2706 return 0;
2707
2708 if (!tool->ordered_events) {
2709 pr_err("Intel Processor Trace requires ordered events\n");
2710 return -EINVAL;
2711 }
2712
2713 if (sample->time && sample->time != (u64)-1)
2714 timestamp = perf_time_to_tsc(sample->time, &pt->tc);
2715 else
2716 timestamp = 0;
2717
2718 if (timestamp || pt->timeless_decoding) {
2719 err = intel_pt_update_queues(pt);
2720 if (err)
2721 return err;
2722 }
2723
2724 if (pt->timeless_decoding) {
2725 if (pt->sampling_mode) {
2726 if (sample->aux_sample.size)
2727 err = intel_pt_process_timeless_sample(pt,
2728 sample);
2729 } else if (event->header.type == PERF_RECORD_EXIT) {
2730 err = intel_pt_process_timeless_queues(pt,
2731 event->fork.tid,
2732 sample->time);
2733 }
2734 } else if (timestamp) {
2735 err = intel_pt_process_queues(pt, timestamp);
2736 }
2737 if (err)
2738 return err;
2739
2740 if (event->header.type == PERF_RECORD_SAMPLE) {
2741 if (pt->synth_opts.add_callchain && !sample->callchain)
2742 intel_pt_add_callchain(pt, sample);
2743 if (pt->synth_opts.add_last_branch && !sample->branch_stack)
2744 intel_pt_add_br_stack(pt, sample);
2745 }
2746
2747 if (event->header.type == PERF_RECORD_AUX &&
2748 (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
2749 pt->synth_opts.errors) {
2750 err = intel_pt_lost(pt, sample);
2751 if (err)
2752 return err;
2753 }
2754
2755 if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
2756 err = intel_pt_process_switch(pt, sample);
2757 else if (event->header.type == PERF_RECORD_ITRACE_START)
2758 err = intel_pt_process_itrace_start(pt, event, sample);
2759 else if (event->header.type == PERF_RECORD_SWITCH ||
2760 event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
2761 err = intel_pt_context_switch(pt, event, sample);
2762
2763 if (!err && event->header.type == PERF_RECORD_TEXT_POKE)
2764 err = intel_pt_text_poke(pt, event);
2765
2766 if (intel_pt_enable_logging && intel_pt_log_events(pt, sample->time)) {
2767 intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ",
2768 event->header.type, sample->cpu, sample->time, timestamp);
2769 intel_pt_log_event(event);
2770 }
2771
2772 return err;
2773 }
2774
2775 static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
2776 {
2777 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2778 auxtrace);
2779 int ret;
2780
2781 if (dump_trace)
2782 return 0;
2783
2784 if (!tool->ordered_events)
2785 return -EINVAL;
2786
2787 ret = intel_pt_update_queues(pt);
2788 if (ret < 0)
2789 return ret;
2790
2791 if (pt->timeless_decoding)
2792 return intel_pt_process_timeless_queues(pt, -1,
2793 MAX_TIMESTAMP - 1);
2794
2795 return intel_pt_process_queues(pt, MAX_TIMESTAMP);
2796 }
2797
2798 static void intel_pt_free_events(struct perf_session *session)
2799 {
2800 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2801 auxtrace);
2802 struct auxtrace_queues *queues = &pt->queues;
2803 unsigned int i;
2804
2805 for (i = 0; i < queues->nr_queues; i++) {
2806 intel_pt_free_queue(queues->queue_array[i].priv);
2807 queues->queue_array[i].priv = NULL;
2808 }
2809 intel_pt_log_disable();
2810 auxtrace_queues__free(queues);
2811 }
2812
2813 static void intel_pt_free(struct perf_session *session)
2814 {
2815 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2816 auxtrace);
2817
2818 auxtrace_heap__free(&pt->heap);
2819 intel_pt_free_events(session);
2820 session->auxtrace = NULL;
2821 thread__put(pt->unknown_thread);
2822 addr_filters__exit(&pt->filts);
2823 zfree(&pt->chain);
2824 zfree(&pt->filter);
2825 zfree(&pt->time_ranges);
2826 free(pt);
2827 }
2828
2829 static bool intel_pt_evsel_is_auxtrace(struct perf_session *session,
2830 struct evsel *evsel)
2831 {
2832 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2833 auxtrace);
2834
2835 return evsel->core.attr.type == pt->pmu_type;
2836 }
2837
2838 static int intel_pt_process_auxtrace_event(struct perf_session *session,
2839 union perf_event *event,
2840 struct perf_tool *tool __maybe_unused)
2841 {
2842 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2843 auxtrace);
2844
2845 if (!pt->data_queued) {
2846 struct auxtrace_buffer *buffer;
2847 off_t data_offset;
2848 int fd = perf_data__fd(session->data);
2849 int err;
2850
2851 if (perf_data__is_pipe(session->data)) {
2852 data_offset = 0;
2853 } else {
2854 data_offset = lseek(fd, 0, SEEK_CUR);
2855 if (data_offset == -1)
2856 return -errno;
2857 }
2858
2859 err = auxtrace_queues__add_event(&pt->queues, session, event,
2860 data_offset, &buffer);
2861 if (err)
2862 return err;
2863
2864 /* Dump here now we have copied a piped trace out of the pipe */
2865 if (dump_trace) {
2866 if (auxtrace_buffer__get_data(buffer, fd)) {
2867 intel_pt_dump_event(pt, buffer->data,
2868 buffer->size);
2869 auxtrace_buffer__put_data(buffer);
2870 }
2871 }
2872 }
2873
2874 return 0;
2875 }
2876
2877 static int intel_pt_queue_data(struct perf_session *session,
2878 struct perf_sample *sample,
2879 union perf_event *event, u64 data_offset)
2880 {
2881 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2882 auxtrace);
2883 u64 timestamp;
2884
2885 if (event) {
2886 return auxtrace_queues__add_event(&pt->queues, session, event,
2887 data_offset, NULL);
2888 }
2889
2890 if (sample->time && sample->time != (u64)-1)
2891 timestamp = perf_time_to_tsc(sample->time, &pt->tc);
2892 else
2893 timestamp = 0;
2894
2895 return auxtrace_queues__add_sample(&pt->queues, session, sample,
2896 data_offset, timestamp);
2897 }
2898
2899 struct intel_pt_synth {
2900 struct perf_tool dummy_tool;
2901 struct perf_session *session;
2902 };
2903
2904 static int intel_pt_event_synth(struct perf_tool *tool,
2905 union perf_event *event,
2906 struct perf_sample *sample __maybe_unused,
2907 struct machine *machine __maybe_unused)
2908 {
2909 struct intel_pt_synth *intel_pt_synth =
2910 container_of(tool, struct intel_pt_synth, dummy_tool);
2911
2912 return perf_session__deliver_synth_event(intel_pt_synth->session, event,
2913 NULL);
2914 }
2915
2916 static int intel_pt_synth_event(struct perf_session *session, const char *name,
2917 struct perf_event_attr *attr, u64 id)
2918 {
2919 struct intel_pt_synth intel_pt_synth;
2920 int err;
2921
2922 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
2923 name, id, (u64)attr->sample_type);
2924
2925 memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
2926 intel_pt_synth.session = session;
2927
2928 err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
2929 &id, intel_pt_event_synth);
2930 if (err)
2931 pr_err("%s: failed to synthesize '%s' event type\n",
2932 __func__, name);
2933
2934 return err;
2935 }
2936
2937 static void intel_pt_set_event_name(struct evlist *evlist, u64 id,
2938 const char *name)
2939 {
2940 struct evsel *evsel;
2941
2942 evlist__for_each_entry(evlist, evsel) {
2943 if (evsel->core.id && evsel->core.id[0] == id) {
2944 if (evsel->name)
2945 zfree(&evsel->name);
2946 evsel->name = strdup(name);
2947 break;
2948 }
2949 }
2950 }
2951
2952 static struct evsel *intel_pt_evsel(struct intel_pt *pt,
2953 struct evlist *evlist)
2954 {
2955 struct evsel *evsel;
2956
2957 evlist__for_each_entry(evlist, evsel) {
2958 if (evsel->core.attr.type == pt->pmu_type && evsel->core.ids)
2959 return evsel;
2960 }
2961
2962 return NULL;
2963 }
2964
2965 static int intel_pt_synth_events(struct intel_pt *pt,
2966 struct perf_session *session)
2967 {
2968 struct evlist *evlist = session->evlist;
2969 struct evsel *evsel = intel_pt_evsel(pt, evlist);
2970 struct perf_event_attr attr;
2971 u64 id;
2972 int err;
2973
2974 if (!evsel) {
2975 pr_debug("There are no selected events with Intel Processor Trace data\n");
2976 return 0;
2977 }
2978
2979 memset(&attr, 0, sizeof(struct perf_event_attr));
2980 attr.size = sizeof(struct perf_event_attr);
2981 attr.type = PERF_TYPE_HARDWARE;
2982 attr.sample_type = evsel->core.attr.sample_type & PERF_SAMPLE_MASK;
2983 attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
2984 PERF_SAMPLE_PERIOD;
2985 if (pt->timeless_decoding)
2986 attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
2987 else
2988 attr.sample_type |= PERF_SAMPLE_TIME;
2989 if (!pt->per_cpu_mmaps)
2990 attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
2991 attr.exclude_user = evsel->core.attr.exclude_user;
2992 attr.exclude_kernel = evsel->core.attr.exclude_kernel;
2993 attr.exclude_hv = evsel->core.attr.exclude_hv;
2994 attr.exclude_host = evsel->core.attr.exclude_host;
2995 attr.exclude_guest = evsel->core.attr.exclude_guest;
2996 attr.sample_id_all = evsel->core.attr.sample_id_all;
2997 attr.read_format = evsel->core.attr.read_format;
2998
2999 id = evsel->core.id[0] + 1000000000;
3000 if (!id)
3001 id = 1;
3002
3003 if (pt->synth_opts.branches) {
3004 attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
3005 attr.sample_period = 1;
3006 attr.sample_type |= PERF_SAMPLE_ADDR;
3007 err = intel_pt_synth_event(session, "branches", &attr, id);
3008 if (err)
3009 return err;
3010 pt->sample_branches = true;
3011 pt->branches_sample_type = attr.sample_type;
3012 pt->branches_id = id;
3013 id += 1;
3014 attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
3015 }
3016
3017 if (pt->synth_opts.callchain)
3018 attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
3019 if (pt->synth_opts.last_branch) {
3020 attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
3021 /*
3022 * We don't use the hardware index, but the sample generation
3023 * code uses the new format branch_stack with this field,
3024 * so the event attributes must indicate that it's present.
3025 */
3026 attr.branch_sample_type |= PERF_SAMPLE_BRANCH_HW_INDEX;
3027 }
3028
3029 if (pt->synth_opts.instructions) {
3030 attr.config = PERF_COUNT_HW_INSTRUCTIONS;
3031 if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
3032 attr.sample_period =
3033 intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
3034 else
3035 attr.sample_period = pt->synth_opts.period;
3036 err = intel_pt_synth_event(session, "instructions", &attr, id);
3037 if (err)
3038 return err;
3039 pt->sample_instructions = true;
3040 pt->instructions_sample_type = attr.sample_type;
3041 pt->instructions_id = id;
3042 id += 1;
3043 }
3044
3045 attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
3046 attr.sample_period = 1;
3047
3048 if (pt->synth_opts.transactions) {
3049 attr.config = PERF_COUNT_HW_INSTRUCTIONS;
3050 err = intel_pt_synth_event(session, "transactions", &attr, id);
3051 if (err)
3052 return err;
3053 pt->sample_transactions = true;
3054 pt->transactions_sample_type = attr.sample_type;
3055 pt->transactions_id = id;
3056 intel_pt_set_event_name(evlist, id, "transactions");
3057 id += 1;
3058 }
3059
3060 attr.type = PERF_TYPE_SYNTH;
3061 attr.sample_type |= PERF_SAMPLE_RAW;
3062
3063 if (pt->synth_opts.ptwrites) {
3064 attr.config = PERF_SYNTH_INTEL_PTWRITE;
3065 err = intel_pt_synth_event(session, "ptwrite", &attr, id);
3066 if (err)
3067 return err;
3068 pt->sample_ptwrites = true;
3069 pt->ptwrites_sample_type = attr.sample_type;
3070 pt->ptwrites_id = id;
3071 intel_pt_set_event_name(evlist, id, "ptwrite");
3072 id += 1;
3073 }
3074
3075 if (pt->synth_opts.pwr_events) {
3076 pt->sample_pwr_events = true;
3077 pt->pwr_events_sample_type = attr.sample_type;
3078
3079 attr.config = PERF_SYNTH_INTEL_CBR;
3080 err = intel_pt_synth_event(session, "cbr", &attr, id);
3081 if (err)
3082 return err;
3083 pt->cbr_id = id;
3084 intel_pt_set_event_name(evlist, id, "cbr");
3085 id += 1;
3086 }
3087
3088 if (pt->synth_opts.pwr_events && (evsel->core.attr.config & 0x10)) {
3089 attr.config = PERF_SYNTH_INTEL_MWAIT;
3090 err = intel_pt_synth_event(session, "mwait", &attr, id);
3091 if (err)
3092 return err;
3093 pt->mwait_id = id;
3094 intel_pt_set_event_name(evlist, id, "mwait");
3095 id += 1;
3096
3097 attr.config = PERF_SYNTH_INTEL_PWRE;
3098 err = intel_pt_synth_event(session, "pwre", &attr, id);
3099 if (err)
3100 return err;
3101 pt->pwre_id = id;
3102 intel_pt_set_event_name(evlist, id, "pwre");
3103 id += 1;
3104
3105 attr.config = PERF_SYNTH_INTEL_EXSTOP;
3106 err = intel_pt_synth_event(session, "exstop", &attr, id);
3107 if (err)
3108 return err;
3109 pt->exstop_id = id;
3110 intel_pt_set_event_name(evlist, id, "exstop");
3111 id += 1;
3112
3113 attr.config = PERF_SYNTH_INTEL_PWRX;
3114 err = intel_pt_synth_event(session, "pwrx", &attr, id);
3115 if (err)
3116 return err;
3117 pt->pwrx_id = id;
3118 intel_pt_set_event_name(evlist, id, "pwrx");
3119 id += 1;
3120 }
3121
3122 return 0;
3123 }
3124
3125 static void intel_pt_setup_pebs_events(struct intel_pt *pt)
3126 {
3127 struct evsel *evsel;
3128
3129 if (!pt->synth_opts.other_events)
3130 return;
3131
3132 evlist__for_each_entry(pt->session->evlist, evsel) {
3133 if (evsel->core.attr.aux_output && evsel->core.id) {
3134 pt->sample_pebs = true;
3135 pt->pebs_evsel = evsel;
3136 return;
3137 }
3138 }
3139 }
3140
3141 static struct evsel *intel_pt_find_sched_switch(struct evlist *evlist)
3142 {
3143 struct evsel *evsel;
3144
3145 evlist__for_each_entry_reverse(evlist, evsel) {
3146 const char *name = evsel__name(evsel);
3147
3148 if (!strcmp(name, "sched:sched_switch"))
3149 return evsel;
3150 }
3151
3152 return NULL;
3153 }
3154
3155 static bool intel_pt_find_switch(struct evlist *evlist)
3156 {
3157 struct evsel *evsel;
3158
3159 evlist__for_each_entry(evlist, evsel) {
3160 if (evsel->core.attr.context_switch)
3161 return true;
3162 }
3163
3164 return false;
3165 }
3166
3167 static int intel_pt_perf_config(const char *var, const char *value, void *data)
3168 {
3169 struct intel_pt *pt = data;
3170
3171 if (!strcmp(var, "intel-pt.mispred-all"))
3172 pt->mispred_all = perf_config_bool(var, value);
3173
3174 return 0;
3175 }
3176
3177 /* Find least TSC which converts to ns or later */
3178 static u64 intel_pt_tsc_start(u64 ns, struct intel_pt *pt)
3179 {
3180 u64 tsc, tm;
3181
3182 tsc = perf_time_to_tsc(ns, &pt->tc);
3183
3184 while (1) {
3185 tm = tsc_to_perf_time(tsc, &pt->tc);
3186 if (tm < ns)
3187 break;
3188 tsc -= 1;
3189 }
3190
3191 while (tm < ns)
3192 tm = tsc_to_perf_time(++tsc, &pt->tc);
3193
3194 return tsc;
3195 }
3196
3197 /* Find greatest TSC which converts to ns or earlier */
3198 static u64 intel_pt_tsc_end(u64 ns, struct intel_pt *pt)
3199 {
3200 u64 tsc, tm;
3201
3202 tsc = perf_time_to_tsc(ns, &pt->tc);
3203
3204 while (1) {
3205 tm = tsc_to_perf_time(tsc, &pt->tc);
3206 if (tm > ns)
3207 break;
3208 tsc += 1;
3209 }
3210
3211 while (tm > ns)
3212 tm = tsc_to_perf_time(--tsc, &pt->tc);
3213
3214 return tsc;
3215 }
3216
3217 static int intel_pt_setup_time_ranges(struct intel_pt *pt,
3218 struct itrace_synth_opts *opts)
3219 {
3220 struct perf_time_interval *p = opts->ptime_range;
3221 int n = opts->range_num;
3222 int i;
3223
3224 if (!n || !p || pt->timeless_decoding)
3225 return 0;
3226
3227 pt->time_ranges = calloc(n, sizeof(struct range));
3228 if (!pt->time_ranges)
3229 return -ENOMEM;
3230
3231 pt->range_cnt = n;
3232
3233 intel_pt_log("%s: %u range(s)\n", __func__, n);
3234
3235 for (i = 0; i < n; i++) {
3236 struct range *r = &pt->time_ranges[i];
3237 u64 ts = p[i].start;
3238 u64 te = p[i].end;
3239
3240 /*
3241 * Take care to ensure the TSC range matches the perf-time range
3242 * when converted back to perf-time.
3243 */
3244 r->start = ts ? intel_pt_tsc_start(ts, pt) : 0;
3245 r->end = te ? intel_pt_tsc_end(te, pt) : 0;
3246
3247 intel_pt_log("range %d: perf time interval: %"PRIu64" to %"PRIu64"\n",
3248 i, ts, te);
3249 intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n",
3250 i, r->start, r->end);
3251 }
3252
3253 return 0;
3254 }
3255
3256 static const char * const intel_pt_info_fmts[] = {
3257 [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
3258 [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
3259 [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
3260 [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
3261 [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
3262 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
3263 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
3264 [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
3265 [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
3266 [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
3267 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
3268 [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
3269 [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
3270 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
3271 [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
3272 [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
3273 };
3274
3275 static void intel_pt_print_info(__u64 *arr, int start, int finish)
3276 {
3277 int i;
3278
3279 if (!dump_trace)
3280 return;
3281
3282 for (i = start; i <= finish; i++)
3283 fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
3284 }
3285
3286 static void intel_pt_print_info_str(const char *name, const char *str)
3287 {
3288 if (!dump_trace)
3289 return;
3290
3291 fprintf(stdout, " %-20s%s\n", name, str ? str : "");
3292 }
3293
3294 static bool intel_pt_has(struct perf_record_auxtrace_info *auxtrace_info, int pos)
3295 {
3296 return auxtrace_info->header.size >=
3297 sizeof(struct perf_record_auxtrace_info) + (sizeof(u64) * (pos + 1));
3298 }
3299
3300 int intel_pt_process_auxtrace_info(union perf_event *event,
3301 struct perf_session *session)
3302 {
3303 struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info;
3304 size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
3305 struct intel_pt *pt;
3306 void *info_end;
3307 __u64 *info;
3308 int err;
3309
3310 if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info) +
3311 min_sz)
3312 return -EINVAL;
3313
3314 pt = zalloc(sizeof(struct intel_pt));
3315 if (!pt)
3316 return -ENOMEM;
3317
3318 addr_filters__init(&pt->filts);
3319
3320 err = perf_config(intel_pt_perf_config, pt);
3321 if (err)
3322 goto err_free;
3323
3324 err = auxtrace_queues__init(&pt->queues);
3325 if (err)
3326 goto err_free;
3327
3328 intel_pt_log_set_name(INTEL_PT_PMU_NAME);
3329
3330 pt->session = session;
3331 pt->machine = &session->machines.host; /* No kvm support */
3332 pt->auxtrace_type = auxtrace_info->type;
3333 pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
3334 pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
3335 pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
3336 pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
3337 pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
3338 pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
3339 pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
3340 pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
3341 pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
3342 pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
3343 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
3344 INTEL_PT_PER_CPU_MMAPS);
3345
3346 if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
3347 pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
3348 pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
3349 pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
3350 pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
3351 pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
3352 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
3353 INTEL_PT_CYC_BIT);
3354 }
3355
3356 if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
3357 pt->max_non_turbo_ratio =
3358 auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
3359 intel_pt_print_info(&auxtrace_info->priv[0],
3360 INTEL_PT_MAX_NONTURBO_RATIO,
3361 INTEL_PT_MAX_NONTURBO_RATIO);
3362 }
3363
3364 info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
3365 info_end = (void *)info + auxtrace_info->header.size;
3366
3367 if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
3368 size_t len;
3369
3370 len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
3371 intel_pt_print_info(&auxtrace_info->priv[0],
3372 INTEL_PT_FILTER_STR_LEN,
3373 INTEL_PT_FILTER_STR_LEN);
3374 if (len) {
3375 const char *filter = (const char *)info;
3376
3377 len = roundup(len + 1, 8);
3378 info += len >> 3;
3379 if ((void *)info > info_end) {
3380 pr_err("%s: bad filter string length\n", __func__);
3381 err = -EINVAL;
3382 goto err_free_queues;
3383 }
3384 pt->filter = memdup(filter, len);
3385 if (!pt->filter) {
3386 err = -ENOMEM;
3387 goto err_free_queues;
3388 }
3389 if (session->header.needs_swap)
3390 mem_bswap_64(pt->filter, len);
3391 if (pt->filter[len - 1]) {
3392 pr_err("%s: filter string not null terminated\n", __func__);
3393 err = -EINVAL;
3394 goto err_free_queues;
3395 }
3396 err = addr_filters__parse_bare_filter(&pt->filts,
3397 filter);
3398 if (err)
3399 goto err_free_queues;
3400 }
3401 intel_pt_print_info_str("Filter string", pt->filter);
3402 }
3403
3404 pt->timeless_decoding = intel_pt_timeless_decoding(pt);
3405 if (pt->timeless_decoding && !pt->tc.time_mult)
3406 pt->tc.time_mult = 1;
3407 pt->have_tsc = intel_pt_have_tsc(pt);
3408 pt->sampling_mode = intel_pt_sampling_mode(pt);
3409 pt->est_tsc = !pt->timeless_decoding;
3410
3411 pt->unknown_thread = thread__new(999999999, 999999999);
3412 if (!pt->unknown_thread) {
3413 err = -ENOMEM;
3414 goto err_free_queues;
3415 }
3416
3417 /*
3418 * Since this thread will not be kept in any rbtree not in a
3419 * list, initialize its list node so that at thread__put() the
3420 * current thread lifetime assuption is kept and we don't segfault
3421 * at list_del_init().
3422 */
3423 INIT_LIST_HEAD(&pt->unknown_thread->node);
3424
3425 err = thread__set_comm(pt->unknown_thread, "unknown", 0);
3426 if (err)
3427 goto err_delete_thread;
3428 if (thread__init_maps(pt->unknown_thread, pt->machine)) {
3429 err = -ENOMEM;
3430 goto err_delete_thread;
3431 }
3432
3433 pt->auxtrace.process_event = intel_pt_process_event;
3434 pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
3435 pt->auxtrace.queue_data = intel_pt_queue_data;
3436 pt->auxtrace.dump_auxtrace_sample = intel_pt_dump_sample;
3437 pt->auxtrace.flush_events = intel_pt_flush;
3438 pt->auxtrace.free_events = intel_pt_free_events;
3439 pt->auxtrace.free = intel_pt_free;
3440 pt->auxtrace.evsel_is_auxtrace = intel_pt_evsel_is_auxtrace;
3441 session->auxtrace = &pt->auxtrace;
3442
3443 if (dump_trace)
3444 return 0;
3445
3446 if (pt->have_sched_switch == 1) {
3447 pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
3448 if (!pt->switch_evsel) {
3449 pr_err("%s: missing sched_switch event\n", __func__);
3450 err = -EINVAL;
3451 goto err_delete_thread;
3452 }
3453 } else if (pt->have_sched_switch == 2 &&
3454 !intel_pt_find_switch(session->evlist)) {
3455 pr_err("%s: missing context_switch attribute flag\n", __func__);
3456 err = -EINVAL;
3457 goto err_delete_thread;
3458 }
3459
3460 if (session->itrace_synth_opts->set) {
3461 pt->synth_opts = *session->itrace_synth_opts;
3462 } else {
3463 itrace_synth_opts__set_default(&pt->synth_opts,
3464 session->itrace_synth_opts->default_no_sample);
3465 if (!session->itrace_synth_opts->default_no_sample &&
3466 !session->itrace_synth_opts->inject) {
3467 pt->synth_opts.branches = false;
3468 pt->synth_opts.callchain = true;
3469 pt->synth_opts.add_callchain = true;
3470 }
3471 pt->synth_opts.thread_stack =
3472 session->itrace_synth_opts->thread_stack;
3473 }
3474
3475 if (pt->synth_opts.log)
3476 intel_pt_log_enable();
3477
3478 /* Maximum non-turbo ratio is TSC freq / 100 MHz */
3479 if (pt->tc.time_mult) {
3480 u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
3481
3482 if (!pt->max_non_turbo_ratio)
3483 pt->max_non_turbo_ratio =
3484 (tsc_freq + 50000000) / 100000000;
3485 intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
3486 intel_pt_log("Maximum non-turbo ratio %u\n",
3487 pt->max_non_turbo_ratio);
3488 pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
3489 }
3490
3491 err = intel_pt_setup_time_ranges(pt, session->itrace_synth_opts);
3492 if (err)
3493 goto err_delete_thread;
3494
3495 if (pt->synth_opts.calls)
3496 pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
3497 PERF_IP_FLAG_TRACE_END;
3498 if (pt->synth_opts.returns)
3499 pt->branches_filter |= PERF_IP_FLAG_RETURN |
3500 PERF_IP_FLAG_TRACE_BEGIN;
3501
3502 if ((pt->synth_opts.callchain || pt->synth_opts.add_callchain) &&
3503 !symbol_conf.use_callchain) {
3504 symbol_conf.use_callchain = true;
3505 if (callchain_register_param(&callchain_param) < 0) {
3506 symbol_conf.use_callchain = false;
3507 pt->synth_opts.callchain = false;
3508 pt->synth_opts.add_callchain = false;
3509 }
3510 }
3511
3512 if (pt->synth_opts.add_callchain) {
3513 err = intel_pt_callchain_init(pt);
3514 if (err)
3515 goto err_delete_thread;
3516 }
3517
3518 if (pt->synth_opts.last_branch || pt->synth_opts.add_last_branch) {
3519 pt->br_stack_sz = pt->synth_opts.last_branch_sz;
3520 pt->br_stack_sz_plus = pt->br_stack_sz;
3521 }
3522
3523 if (pt->synth_opts.add_last_branch) {
3524 err = intel_pt_br_stack_init(pt);
3525 if (err)
3526 goto err_delete_thread;
3527 /*
3528 * Additional branch stack size to cater for tracing from the
3529 * actual sample ip to where the sample time is recorded.
3530 * Measured at about 200 branches, but generously set to 1024.
3531 * If kernel space is not being traced, then add just 1 for the
3532 * branch to kernel space.
3533 */
3534 if (intel_pt_tracing_kernel(pt))
3535 pt->br_stack_sz_plus += 1024;
3536 else
3537 pt->br_stack_sz_plus += 1;
3538 }
3539
3540 pt->use_thread_stack = pt->synth_opts.callchain ||
3541 pt->synth_opts.add_callchain ||
3542 pt->synth_opts.thread_stack ||
3543 pt->synth_opts.last_branch ||
3544 pt->synth_opts.add_last_branch;
3545
3546 pt->callstack = pt->synth_opts.callchain ||
3547 pt->synth_opts.add_callchain ||
3548 pt->synth_opts.thread_stack;
3549
3550 err = intel_pt_synth_events(pt, session);
3551 if (err)
3552 goto err_delete_thread;
3553
3554 intel_pt_setup_pebs_events(pt);
3555
3556 if (pt->sampling_mode || list_empty(&session->auxtrace_index))
3557 err = auxtrace_queue_data(session, true, true);
3558 else
3559 err = auxtrace_queues__process_index(&pt->queues, session);
3560 if (err)
3561 goto err_delete_thread;
3562
3563 if (pt->queues.populated)
3564 pt->data_queued = true;
3565
3566 if (pt->timeless_decoding)
3567 pr_debug2("Intel PT decoding without timestamps\n");
3568
3569 return 0;
3570
3571 err_delete_thread:
3572 zfree(&pt->chain);
3573 thread__zput(pt->unknown_thread);
3574 err_free_queues:
3575 intel_pt_log_disable();
3576 auxtrace_queues__free(&pt->queues);
3577 session->auxtrace = NULL;
3578 err_free:
3579 addr_filters__exit(&pt->filts);
3580 zfree(&pt->filter);
3581 zfree(&pt->time_ranges);
3582 free(pt);
3583 return err;
3584 }
Linux with added FPC-III support