include/asm-arm/arch-clps711x/syspld.h

   1 /*
   2  *  linux/include/asm-arm/arch-clps711x/syspld.h
   3  *
   4  *  System Control PLD register definitions.
   5  *
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 #ifndef __ASM_ARCH_SYSPLD_H
  23 #define __ASM_ARCH_SYSPLD_H
  24
  25 #define SYSPLD_PHYS_BASE        (0x10000000)
  26
  27 #ifndef __ASSEMBLY__
  28 #include <asm/types.h>
  29
  30 #define SYSPLD_REG(type,off)    (*(volatile type *)(SYSPLD_BASE + off))
  31 #else
  32 #define SYSPLD_REG(type,off)    (off)
  33 #endif
  34
  35 #define PLD_INT         SYSPLD_REG(u32, 0x000000)
  36 #define PLD_INT_PENIRQ          (1 << 5)
  37 #define PLD_INT_UCB_IRQ         (1 << 1)
  38 #define PLD_INT_KBD_ATN         (1 << 0)        /* EINT1 */
  39
  40 #define PLD_PWR         SYSPLD_REG(u32, 0x000004)
  41 #define PLD_PWR_EXT             (1 << 5)
  42 #define PLD_PWR_MODE            (1 << 4)        /* 1 = PWM, 0 = PFM */
  43 #define PLD_S4_ON               (1 << 3)        /* LCD bias voltage enable */
  44 #define PLD_S3_ON               (1 << 2)        /* LCD backlight enable */
  45 #define PLD_S2_ON               (1 << 1)        /* LCD 3V3 supply enable */
  46 #define PLD_S1_ON               (1 << 0)        /* LCD 3V supply enable */
  47
  48 #define PLD_KBD         SYSPLD_REG(u32, 0x000008)
  49 #define PLD_KBD_WAKE            (1 << 1)
  50 #define PLD_KBD_EN              (1 << 0)
  51
  52 #define PLD_SPI         SYSPLD_REG(u32, 0x00000c)
  53 #define PLD_SPI_EN              (1 << 0)
  54
  55 #define PLD_IO          SYSPLD_REG(u32, 0x000010)
  56 #define PLD_IO_BOOTSEL          (1 << 6)        /* boot sel switch */
  57 #define PLD_IO_USER             (1 << 5)        /* user defined switch */
  58 #define PLD_IO_LED3             (1 << 4)
  59 #define PLD_IO_LED2             (1 << 3)
  60 #define PLD_IO_LED1             (1 << 2)
  61 #define PLD_IO_LED0             (1 << 1)
  62 #define PLD_IO_LEDEN            (1 << 0)
  63
  64 #define PLD_IRDA        SYSPLD_REG(u32, 0x000014)
  65 #define PLD_IRDA_EN             (1 << 0)
  66
  67 #define PLD_COM2        SYSPLD_REG(u32, 0x000018)
  68 #define PLD_COM2_EN             (1 << 0)
  69
  70 #define PLD_COM1        SYSPLD_REG(u32, 0x00001c)
  71 #define PLD_COM1_EN             (1 << 0)
  72
  73 #define PLD_AUD         SYSPLD_REG(u32, 0x000020)
  74 #define PLD_AUD_DIV1            (1 << 6)
  75 #define PLD_AUD_DIV0            (1 << 5)
  76 #define PLD_AUD_CLK_SEL1        (1 << 4)
  77 #define PLD_AUD_CLK_SEL0        (1 << 3)
  78 #define PLD_AUD_MIC_PWR         (1 << 2)
  79 #define PLD_AUD_MIC_GAIN        (1 << 1)
  80 #define PLD_AUD_CODEC_EN        (1 << 0)
  81
  82 #define PLD_CF          SYSPLD_REG(u32, 0x000024)
  83 #define PLD_CF2_SLEEP           (1 << 5)
  84 #define PLD_CF1_SLEEP           (1 << 4)
  85 #define PLD_CF2_nPDREQ          (1 << 3)
  86 #define PLD_CF1_nPDREQ          (1 << 2)
  87 #define PLD_CF2_nIRQ            (1 << 1)
  88 #define PLD_CF1_nIRQ            (1 << 0)
  89
  90 #define PLD_SDC         SYSPLD_REG(u32, 0x000028)
  91 #define PLD_SDC_INT_EN          (1 << 2)
  92 #define PLD_SDC_WP              (1 << 1)
  93 #define PLD_SDC_CD              (1 << 0)
  94
  95 #define PLD_FPGA        SYSPLD_REG(u32, 0x00002c)
  96
  97 #define PLD_CODEC       SYSPLD_REG(u32, 0x400000)
  98 #define PLD_CODEC_IRQ3          (1 << 4)
  99 #define PLD_CODEC_IRQ2          (1 << 3)
 100 #define PLD_CODEC_IRQ1          (1 << 2)
 101 #define PLD_CODEC_EN            (1 << 0)
 102
 103 #define PLD_BRITE       SYSPLD_REG(u32, 0x400004)
 104 #define PLD_BRITE_UP            (1 << 1)
 105 #define PLD_BRITE_DN            (1 << 0)
 106
 107 #define PLD_LCDEN       SYSPLD_REG(u32, 0x400008)
 108 #define PLD_LCDEN_EN            (1 << 0)
 109
 110 #define PLD_ID          SYSPLD_REG(u32, 0x40000c)
 111
 112 #define PLD_TCH         SYSPLD_REG(u32, 0x400010)
 113 #define PLD_TCH_PENIRQ          (1 << 1)
 114 #define PLD_TCH_EN              (1 << 0)
 115
 116 #define PLD_GPIO        SYSPLD_REG(u32, 0x400014)
 117 #define PLD_GPIO2               (1 << 2)
 118 #define PLD_GPIO1               (1 << 1)
 119 #define PLD_GPIO0               (1 << 0)
 120
 121 #endif