include/asm-arm/io.h

   1 /*
   2  *  linux/include/asm-arm/io.h
   3  *
   4  *  Copyright (C) 1996-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Modifications:
  11  *  16-Sep-1996 RMK     Inlined the inx/outx functions & optimised for both
  12  *                      constant addresses and variable addresses.
  13  *  04-Dec-1997 RMK     Moved a lot of this stuff to the new architecture
  14  *                      specific IO header files.
  15  *  27-Mar-1999 PJB     Second parameter of memcpy_toio is const..
  16  *  04-Apr-1999 PJB     Added check_signature.
  17  *  12-Dec-1999 RMK     More cleanups
  18  *  18-Jun-2000 RMK     Removed virt_to_* and friends definitions
  19  *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
  20  */
  21 #ifndef __ASM_ARM_IO_H
  22 #define __ASM_ARM_IO_H
  23
  24 #ifdef __KERNEL__
  25
  26 #include <linux/types.h>
  27 #include <asm/byteorder.h>
  28 #include <asm/memory.h>
  29
  30 /*
  31  * ISA I/O bus memory addresses are 1:1 with the physical address.
  32  */
  33 #define isa_virt_to_bus virt_to_phys
  34 #define isa_page_to_bus page_to_phys
  35 #define isa_bus_to_virt phys_to_virt
  36
  37 /*
  38  * Generic IO read/write.  These perform native-endian accesses.  Note
  39  * that some architectures will want to re-define __raw_{read,write}w.
  40  */
  41 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
  42 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
  43 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
  44
  45 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
  46 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
  47 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
  48
  49 #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v))
  50 #define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
  51 #define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v))
  52
  53 #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
  54 #define __raw_readw(a)          (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
  55 #define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
  56
  57 /*
  58  * Architecture ioremap implementation.
  59  *
  60  * __ioremap takes CPU physical address.
  61  *
  62  * __ioremap_pfn takes a Page Frame Number and an offset into that page
  63  */
  64 extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long);
  65 extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
  66 extern void __iounmap(volatile void __iomem *addr);
  67
  68 /*
  69  * Bad read/write accesses...
  70  */
  71 extern void __readwrite_bug(const char *fn);
  72
  73 /*
  74  * Now, pick up the machine-defined IO definitions
  75  */
  76 #include <asm/arch/io.h>
  77
  78 /*
  79  *  IO port access primitives
  80  *  -------------------------
  81  *
  82  * The ARM doesn't have special IO access instructions; all IO is memory
  83  * mapped.  Note that these are defined to perform little endian accesses
  84  * only.  Their primary purpose is to access PCI and ISA peripherals.
  85  *
  86  * Note that for a big endian machine, this implies that the following
  87  * big endian mode connectivity is in place, as described by numerous
  88  * ARM documents:
  89  *
  90  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
  91  *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
  92  *
  93  * The machine specific io.h include defines __io to translate an "IO"
  94  * address to a memory address.
  95  *
  96  * Note that we prevent GCC re-ordering or caching values in expressions
  97  * by introducing sequence points into the in*() definitions.  Note that
  98  * __raw_* do not guarantee this behaviour.
  99  *
 100  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 101  */
 102 #ifdef __io
 103 #define outb(v,p)               __raw_writeb(v,__io(p))
 104 #define outw(v,p)               __raw_writew((__force __u16) \
 105                                         cpu_to_le16(v),__io(p))
 106 #define outl(v,p)               __raw_writel((__force __u32) \
 107                                         cpu_to_le32(v),__io(p))
 108
 109 #define inb(p)  ({ __u8 __v = __raw_readb(__io(p)); __v; })
 110 #define inw(p)  ({ __u16 __v = le16_to_cpu((__force __le16) \
 111                         __raw_readw(__io(p))); __v; })
 112 #define inl(p)  ({ __u32 __v = le32_to_cpu((__force __le32) \
 113                         __raw_readl(__io(p))); __v; })
 114
 115 #define outsb(p,d,l)            __raw_writesb(__io(p),d,l)
 116 #define outsw(p,d,l)            __raw_writesw(__io(p),d,l)
 117 #define outsl(p,d,l)            __raw_writesl(__io(p),d,l)
 118
 119 #define insb(p,d,l)             __raw_readsb(__io(p),d,l)
 120 #define insw(p,d,l)             __raw_readsw(__io(p),d,l)
 121 #define insl(p,d,l)             __raw_readsl(__io(p),d,l)
 122 #endif
 123
 124 #define outb_p(val,port)        outb((val),(port))
 125 #define outw_p(val,port)        outw((val),(port))
 126 #define outl_p(val,port)        outl((val),(port))
 127 #define inb_p(port)             inb((port))
 128 #define inw_p(port)             inw((port))
 129 #define inl_p(port)             inl((port))
 130
 131 #define outsb_p(port,from,len)  outsb(port,from,len)
 132 #define outsw_p(port,from,len)  outsw(port,from,len)
 133 #define outsl_p(port,from,len)  outsl(port,from,len)
 134 #define insb_p(port,to,len)     insb(port,to,len)
 135 #define insw_p(port,to,len)     insw(port,to,len)
 136 #define insl_p(port,to,len)     insl(port,to,len)
 137
 138 /*
 139  * String version of IO memory access ops:
 140  */
 141 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
 142 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
 143 extern void _memset_io(volatile void __iomem *, int, size_t);
 144
 145 #define mmiowb()
 146
 147 /*
 148  *  Memory access primitives
 149  *  ------------------------
 150  *
 151  * These perform PCI memory accesses via an ioremap region.  They don't
 152  * take an address as such, but a cookie.
 153  *
 154  * Again, this are defined to perform little endian accesses.  See the
 155  * IO port primitives for more information.
 156  */
 157 #ifdef __mem_pci
 158 #define readb(c) ({ __u8  __v = __raw_readb(__mem_pci(c)); __v; })
 159 #define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \
 160                                         __raw_readw(__mem_pci(c))); __v; })
 161 #define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \
 162                                         __raw_readl(__mem_pci(c))); __v; })
 163 #define readb_relaxed(addr) readb(addr)
 164 #define readw_relaxed(addr) readw(addr)
 165 #define readl_relaxed(addr) readl(addr)
 166
 167 #define readsb(p,d,l)           __raw_readsb(__mem_pci(p),d,l)
 168 #define readsw(p,d,l)           __raw_readsw(__mem_pci(p),d,l)
 169 #define readsl(p,d,l)           __raw_readsl(__mem_pci(p),d,l)
 170
 171 #define writeb(v,c)             __raw_writeb(v,__mem_pci(c))
 172 #define writew(v,c)             __raw_writew((__force __u16) \
 173                                         cpu_to_le16(v),__mem_pci(c))
 174 #define writel(v,c)             __raw_writel((__force __u32) \
 175                                         cpu_to_le32(v),__mem_pci(c))
 176
 177 #define writesb(p,d,l)          __raw_writesb(__mem_pci(p),d,l)
 178 #define writesw(p,d,l)          __raw_writesw(__mem_pci(p),d,l)
 179 #define writesl(p,d,l)          __raw_writesl(__mem_pci(p),d,l)
 180
 181 #define memset_io(c,v,l)        _memset_io(__mem_pci(c),(v),(l))
 182 #define memcpy_fromio(a,c,l)    _memcpy_fromio((a),__mem_pci(c),(l))
 183 #define memcpy_toio(c,a,l)      _memcpy_toio(__mem_pci(c),(a),(l))
 184
 185 #define eth_io_copy_and_sum(s,c,l,b) \
 186                                 eth_copy_and_sum((s),__mem_pci(c),(l),(b))
 187
 188 #elif !defined(readb)
 189
 190 #define readb(c)                        (__readwrite_bug("readb"),0)
 191 #define readw(c)                        (__readwrite_bug("readw"),0)
 192 #define readl(c)                        (__readwrite_bug("readl"),0)
 193 #define writeb(v,c)                     __readwrite_bug("writeb")
 194 #define writew(v,c)                     __readwrite_bug("writew")
 195 #define writel(v,c)                     __readwrite_bug("writel")
 196
 197 #define eth_io_copy_and_sum(s,c,l,b)    __readwrite_bug("eth_io_copy_and_sum")
 198
 199 #define check_signature(io,sig,len)     (0)
 200
 201 #endif  /* __mem_pci */
 202
 203 /*
 204  * ioremap and friends.
 205  *
 206  * ioremap takes a PCI memory address, as specified in
 207  * Documentation/IO-mapping.txt.
 208  *
 209  */
 210 #ifndef __arch_ioremap
 211 #define ioremap(cookie,size)            __ioremap(cookie,size,0)
 212 #define ioremap_nocache(cookie,size)    __ioremap(cookie,size,0)
 213 #define ioremap_cached(cookie,size)     __ioremap(cookie,size,L_PTE_CACHEABLE)
 214 #define iounmap(cookie)                 __iounmap(cookie)
 215 #else
 216 #define ioremap(cookie,size)            __arch_ioremap((cookie),(size),0)
 217 #define ioremap_nocache(cookie,size)    __arch_ioremap((cookie),(size),0)
 218 #define ioremap_cached(cookie,size)     __arch_ioremap((cookie),(size),L_PTE_CACHEABLE)
 219 #define iounmap(cookie)                 __arch_iounmap(cookie)
 220 #endif
 221
 222 /*
 223  * io{read,write}{8,16,32} macros
 224  */
 225 #ifndef ioread8
 226 #define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __v; })
 227 #define ioread16(p)     ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
 228 #define ioread32(p)     ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
 229
 230 #define iowrite8(v,p)   __raw_writeb(v, p)
 231 #define iowrite16(v,p)  __raw_writew(cpu_to_le16(v), p)
 232 #define iowrite32(v,p)  __raw_writel(cpu_to_le32(v), p)
 233
 234 #define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
 235 #define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
 236 #define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
 237
 238 #define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
 239 #define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
 240 #define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
 241
 242 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 243 extern void ioport_unmap(void __iomem *addr);
 244 #endif
 245
 246 struct pci_dev;
 247
 248 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
 249 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 250
 251 /*
 252  * can the hardware map this into one segment or not, given no other
 253  * constraints.
 254  */
 255 #define BIOVEC_MERGEABLE(vec1, vec2)    \
 256         ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
 257
 258 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 259 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 260 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 261
 262 /*
 263  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 264  * access
 265  */
 266 #define xlate_dev_mem_ptr(p)    __va(p)
 267
 268 /*
 269  * Convert a virtual cached pointer to an uncached pointer
 270  */
 271 #define xlate_dev_kmem_ptr(p)   p
 272
 273 /*
 274  * Register ISA memory and port locations for glibc iopl/inb/outb
 275  * emulation.
 276  */
 277 extern void register_isa_ports(unsigned int mmio, unsigned int io,
 278                                unsigned int io_shift);
 279
 280 #endif  /* __KERNEL__ */
 281 #endif  /* __ASM_ARM_IO_H */