?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
JBD: round commit timer up to avoid uncommitted transaction
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / r600_cp.c
blob20f17908b036d6c59b8435e354787a42295fa0d8
1 /*
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_drm.h"
32 #include "radeon_drv.h"
33
34 #include "r600_microcode.h"
35
36 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
37 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
38
39 #define R600_PTE_VALID (1 << 0)
40 #define R600_PTE_SYSTEM (1 << 1)
41 #define R600_PTE_SNOOPED (1 << 2)
42 #define R600_PTE_READABLE (1 << 5)
43 #define R600_PTE_WRITEABLE (1 << 6)
44
45 /* MAX values used for gfx init */
46 #define R6XX_MAX_SH_GPRS 256
47 #define R6XX_MAX_TEMP_GPRS 16
48 #define R6XX_MAX_SH_THREADS 256
49 #define R6XX_MAX_SH_STACK_ENTRIES 4096
50 #define R6XX_MAX_BACKENDS 8
51 #define R6XX_MAX_BACKENDS_MASK 0xff
52 #define R6XX_MAX_SIMDS 8
53 #define R6XX_MAX_SIMDS_MASK 0xff
54 #define R6XX_MAX_PIPES 8
55 #define R6XX_MAX_PIPES_MASK 0xff
56
57 #define R7XX_MAX_SH_GPRS 256
58 #define R7XX_MAX_TEMP_GPRS 16
59 #define R7XX_MAX_SH_THREADS 256
60 #define R7XX_MAX_SH_STACK_ENTRIES 4096
61 #define R7XX_MAX_BACKENDS 8
62 #define R7XX_MAX_BACKENDS_MASK 0xff
63 #define R7XX_MAX_SIMDS 16
64 #define R7XX_MAX_SIMDS_MASK 0xffff
65 #define R7XX_MAX_PIPES 8
66 #define R7XX_MAX_PIPES_MASK 0xff
67
68 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
69 {
70 int i;
71
72 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
73
74 for (i = 0; i < dev_priv->usec_timeout; i++) {
75 int slots;
76 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
77 slots = (RADEON_READ(R600_GRBM_STATUS)
78 & R700_CMDFIFO_AVAIL_MASK);
79 else
80 slots = (RADEON_READ(R600_GRBM_STATUS)
81 & R600_CMDFIFO_AVAIL_MASK);
82 if (slots >= entries)
83 return 0;
84 DRM_UDELAY(1);
85 }
86 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
87 RADEON_READ(R600_GRBM_STATUS),
88 RADEON_READ(R600_GRBM_STATUS2));
89
90 return -EBUSY;
91 }
92
93 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
94 {
95 int i, ret;
96
97 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
98
99 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
100 ret = r600_do_wait_for_fifo(dev_priv, 8);
101 else
102 ret = r600_do_wait_for_fifo(dev_priv, 16);
103 if (ret)
104 return ret;
105 for (i = 0; i < dev_priv->usec_timeout; i++) {
106 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
107 return 0;
108 DRM_UDELAY(1);
109 }
110 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
111 RADEON_READ(R600_GRBM_STATUS),
112 RADEON_READ(R600_GRBM_STATUS2));
113
114 return -EBUSY;
115 }
116
117 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
118 {
119 struct drm_sg_mem *entry = dev->sg;
120 int max_pages;
121 int pages;
122 int i;
123
124 if (!entry)
125 return;
126
127 if (gart_info->bus_addr) {
128 max_pages = (gart_info->table_size / sizeof(u64));
129 pages = (entry->pages <= max_pages)
130 ? entry->pages : max_pages;
131
132 for (i = 0; i < pages; i++) {
133 if (!entry->busaddr[i])
134 break;
135 pci_unmap_page(dev->pdev, entry->busaddr[i],
136 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
137 }
138 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
139 gart_info->bus_addr = 0;
140 }
141 }
142
143 /* R600 has page table setup */
144 int r600_page_table_init(struct drm_device *dev)
145 {
146 drm_radeon_private_t *dev_priv = dev->dev_private;
147 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
148 struct drm_local_map *map = &gart_info->mapping;
149 struct drm_sg_mem *entry = dev->sg;
150 int ret = 0;
151 int i, j;
152 int pages;
153 u64 page_base;
154 dma_addr_t entry_addr;
155 int max_ati_pages, max_real_pages, gart_idx;
156
157 /* okay page table is available - lets rock */
158 max_ati_pages = (gart_info->table_size / sizeof(u64));
159 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
160
161 pages = (entry->pages <= max_real_pages) ?
162 entry->pages : max_real_pages;
163
164 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
165
166 gart_idx = 0;
167 for (i = 0; i < pages; i++) {
168 entry->busaddr[i] = pci_map_page(dev->pdev,
169 entry->pagelist[i], 0,
170 PAGE_SIZE,
171 PCI_DMA_BIDIRECTIONAL);
172 if (entry->busaddr[i] == 0) {
173 DRM_ERROR("unable to map PCIGART pages!\n");
174 r600_page_table_cleanup(dev, gart_info);
175 goto done;
176 }
177 entry_addr = entry->busaddr[i];
178 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
179 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
180 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
181 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
182
183 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
184
185 gart_idx++;
186
187 if ((i % 128) == 0)
188 DRM_DEBUG("page entry %d: 0x%016llx\n",
189 i, (unsigned long long)page_base);
190 entry_addr += ATI_PCIGART_PAGE_SIZE;
191 }
192 }
193 ret = 1;
194 done:
195 return ret;
196 }
197
198 static void r600_vm_flush_gart_range(struct drm_device *dev)
199 {
200 drm_radeon_private_t *dev_priv = dev->dev_private;
201 u32 resp, countdown = 1000;
202 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
203 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
204 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
205
206 do {
207 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
208 countdown--;
209 DRM_UDELAY(1);
210 } while (((resp & 0xf0) == 0) && countdown);
211 }
212
213 static void r600_vm_init(struct drm_device *dev)
214 {
215 drm_radeon_private_t *dev_priv = dev->dev_private;
216 /* initialise the VM to use the page table we constructed up there */
217 u32 vm_c0, i;
218 u32 mc_rd_a;
219 u32 vm_l2_cntl, vm_l2_cntl3;
220 /* okay set up the PCIE aperture type thingo */
221 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
222 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
223 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
224
225 /* setup MC RD a */
226 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
227 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
228 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
229
230 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
231 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
232
233 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
234 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
235
236 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
237 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
238
239 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
240 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
241
242 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
243 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
244
245 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
246 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
247
248 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
249 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
250
251 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
252 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
253 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
254
255 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
256 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
257 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
258 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
259 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
260
261 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
262
263 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
264
265 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
266
267 /* disable all other contexts */
268 for (i = 1; i < 8; i++)
269 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
270
271 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
272 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
273 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
274
275 r600_vm_flush_gart_range(dev);
276 }
277
278 /* load r600 microcode */
279 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
280 {
281 int i;
282
283 r600_do_cp_stop(dev_priv);
284
285 RADEON_WRITE(R600_CP_RB_CNTL,
286 R600_RB_NO_UPDATE |
287 R600_RB_BLKSZ(15) |
288 R600_RB_BUFSZ(3));
289
290 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
291 RADEON_READ(R600_GRBM_SOFT_RESET);
292 DRM_UDELAY(15000);
293 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
294
295 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
296
297 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) {
298 DRM_INFO("Loading R600 CP Microcode\n");
299 for (i = 0; i < PM4_UCODE_SIZE; i++) {
300 RADEON_WRITE(R600_CP_ME_RAM_DATA,
301 R600_cp_microcode[i][0]);
302 RADEON_WRITE(R600_CP_ME_RAM_DATA,
303 R600_cp_microcode[i][1]);
304 RADEON_WRITE(R600_CP_ME_RAM_DATA,
305 R600_cp_microcode[i][2]);
306 }
307
308 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
309 DRM_INFO("Loading R600 PFP Microcode\n");
310 for (i = 0; i < PFP_UCODE_SIZE; i++)
311 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]);
312 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) {
313 DRM_INFO("Loading RV610 CP Microcode\n");
314 for (i = 0; i < PM4_UCODE_SIZE; i++) {
315 RADEON_WRITE(R600_CP_ME_RAM_DATA,
316 RV610_cp_microcode[i][0]);
317 RADEON_WRITE(R600_CP_ME_RAM_DATA,
318 RV610_cp_microcode[i][1]);
319 RADEON_WRITE(R600_CP_ME_RAM_DATA,
320 RV610_cp_microcode[i][2]);
321 }
322
323 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
324 DRM_INFO("Loading RV610 PFP Microcode\n");
325 for (i = 0; i < PFP_UCODE_SIZE; i++)
326 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]);
327 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
328 DRM_INFO("Loading RV630 CP Microcode\n");
329 for (i = 0; i < PM4_UCODE_SIZE; i++) {
330 RADEON_WRITE(R600_CP_ME_RAM_DATA,
331 RV630_cp_microcode[i][0]);
332 RADEON_WRITE(R600_CP_ME_RAM_DATA,
333 RV630_cp_microcode[i][1]);
334 RADEON_WRITE(R600_CP_ME_RAM_DATA,
335 RV630_cp_microcode[i][2]);
336 }
337
338 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
339 DRM_INFO("Loading RV630 PFP Microcode\n");
340 for (i = 0; i < PFP_UCODE_SIZE; i++)
341 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]);
342 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) {
343 DRM_INFO("Loading RV620 CP Microcode\n");
344 for (i = 0; i < PM4_UCODE_SIZE; i++) {
345 RADEON_WRITE(R600_CP_ME_RAM_DATA,
346 RV620_cp_microcode[i][0]);
347 RADEON_WRITE(R600_CP_ME_RAM_DATA,
348 RV620_cp_microcode[i][1]);
349 RADEON_WRITE(R600_CP_ME_RAM_DATA,
350 RV620_cp_microcode[i][2]);
351 }
352
353 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
354 DRM_INFO("Loading RV620 PFP Microcode\n");
355 for (i = 0; i < PFP_UCODE_SIZE; i++)
356 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]);
357 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
358 DRM_INFO("Loading RV635 CP Microcode\n");
359 for (i = 0; i < PM4_UCODE_SIZE; i++) {
360 RADEON_WRITE(R600_CP_ME_RAM_DATA,
361 RV635_cp_microcode[i][0]);
362 RADEON_WRITE(R600_CP_ME_RAM_DATA,
363 RV635_cp_microcode[i][1]);
364 RADEON_WRITE(R600_CP_ME_RAM_DATA,
365 RV635_cp_microcode[i][2]);
366 }
367
368 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
369 DRM_INFO("Loading RV635 PFP Microcode\n");
370 for (i = 0; i < PFP_UCODE_SIZE; i++)
371 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]);
372 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) {
373 DRM_INFO("Loading RV670 CP Microcode\n");
374 for (i = 0; i < PM4_UCODE_SIZE; i++) {
375 RADEON_WRITE(R600_CP_ME_RAM_DATA,
376 RV670_cp_microcode[i][0]);
377 RADEON_WRITE(R600_CP_ME_RAM_DATA,
378 RV670_cp_microcode[i][1]);
379 RADEON_WRITE(R600_CP_ME_RAM_DATA,
380 RV670_cp_microcode[i][2]);
381 }
382
383 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
384 DRM_INFO("Loading RV670 PFP Microcode\n");
385 for (i = 0; i < PFP_UCODE_SIZE; i++)
386 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
387 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
389 DRM_INFO("Loading RS780/RS880 CP Microcode\n");
390 for (i = 0; i < PM4_UCODE_SIZE; i++) {
391 RADEON_WRITE(R600_CP_ME_RAM_DATA,
392 RS780_cp_microcode[i][0]);
393 RADEON_WRITE(R600_CP_ME_RAM_DATA,
394 RS780_cp_microcode[i][1]);
395 RADEON_WRITE(R600_CP_ME_RAM_DATA,
396 RS780_cp_microcode[i][2]);
397 }
398
399 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
400 DRM_INFO("Loading RS780/RS880 PFP Microcode\n");
401 for (i = 0; i < PFP_UCODE_SIZE; i++)
402 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
403 }
404 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
405 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
406 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
407
408 }
409
410 static void r700_vm_init(struct drm_device *dev)
411 {
412 drm_radeon_private_t *dev_priv = dev->dev_private;
413 /* initialise the VM to use the page table we constructed up there */
414 u32 vm_c0, i;
415 u32 mc_vm_md_l1;
416 u32 vm_l2_cntl, vm_l2_cntl3;
417 /* okay set up the PCIE aperture type thingo */
418 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
419 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
420 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
421
422 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
423 R700_ENABLE_L1_FRAGMENT_PROCESSING |
424 R700_SYSTEM_ACCESS_MODE_IN_SYS |
425 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
426 R700_EFFECTIVE_L1_TLB_SIZE(5) |
427 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
428
429 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
430 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
431 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
432 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
433 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
434 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
435 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
436
437 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
438 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
439 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
440
441 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
442 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
443 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
444
445 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
446
447 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
448
449 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
450
451 /* disable all other contexts */
452 for (i = 1; i < 8; i++)
453 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
454
455 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
456 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
457 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
458
459 r600_vm_flush_gart_range(dev);
460 }
461
462 /* load r600 microcode */
463 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
464 {
465 int i;
466
467 r600_do_cp_stop(dev_priv);
468
469 RADEON_WRITE(R600_CP_RB_CNTL,
470 R600_RB_NO_UPDATE |
471 (15 << 8) |
472 (3 << 0));
473
474 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
475 RADEON_READ(R600_GRBM_SOFT_RESET);
476 DRM_UDELAY(15000);
477 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
478
479
480 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) {
481 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
482 DRM_INFO("Loading RV770/RV790 PFP Microcode\n");
483 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
484 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]);
485 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
486
487 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
488 DRM_INFO("Loading RV770/RV790 CP Microcode\n");
489 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
490 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
491 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
492
493 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) ||
494 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) {
495 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
496 DRM_INFO("Loading RV730/RV740 PFP Microcode\n");
497 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
498 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
499 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
500
501 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
502 DRM_INFO("Loading RV730/RV740 CP Microcode\n");
503 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
504 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
505 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
506
507 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) {
508 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
509 DRM_INFO("Loading RV710 PFP Microcode\n");
510 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
511 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]);
512 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
513
514 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
515 DRM_INFO("Loading RV710 CP Microcode\n");
516 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
517 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]);
518 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
519
520 }
521 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
522 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
523 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
524
525 }
526
527 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
528 {
529 u32 tmp;
530
531 /* Start with assuming that writeback doesn't work */
532 dev_priv->writeback_works = 0;
533
534 /* Writeback doesn't seem to work everywhere, test it here and possibly
535 * enable it if it appears to work
536 */
537 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
538
539 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
540
541 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
542 u32 val;
543
544 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
545 if (val == 0xdeadbeef)
546 break;
547 DRM_UDELAY(1);
548 }
549
550 if (tmp < dev_priv->usec_timeout) {
551 dev_priv->writeback_works = 1;
552 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
553 } else {
554 dev_priv->writeback_works = 0;
555 DRM_INFO("writeback test failed\n");
556 }
557 if (radeon_no_wb == 1) {
558 dev_priv->writeback_works = 0;
559 DRM_INFO("writeback forced off\n");
560 }
561
562 if (!dev_priv->writeback_works) {
563 /* Disable writeback to avoid unnecessary bus master transfer */
564 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
565 RADEON_RB_NO_UPDATE);
566 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
567 }
568 }
569
570 int r600_do_engine_reset(struct drm_device *dev)
571 {
572 drm_radeon_private_t *dev_priv = dev->dev_private;
573 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
574
575 DRM_INFO("Resetting GPU\n");
576
577 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
578 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
579 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
580
581 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
582 RADEON_READ(R600_GRBM_SOFT_RESET);
583 DRM_UDELAY(50);
584 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
585 RADEON_READ(R600_GRBM_SOFT_RESET);
586
587 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
588 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
589 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
590
591 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
592 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
593 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
594 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
595
596 /* Reset the CP ring */
597 r600_do_cp_reset(dev_priv);
598
599 /* The CP is no longer running after an engine reset */
600 dev_priv->cp_running = 0;
601
602 /* Reset any pending vertex, indirect buffers */
603 radeon_freelist_reset(dev);
604
605 return 0;
606
607 }
608
609 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
610 u32 num_backends,
611 u32 backend_disable_mask)
612 {
613 u32 backend_map = 0;
614 u32 enabled_backends_mask;
615 u32 enabled_backends_count;
616 u32 cur_pipe;
617 u32 swizzle_pipe[R6XX_MAX_PIPES];
618 u32 cur_backend;
619 u32 i;
620
621 if (num_tile_pipes > R6XX_MAX_PIPES)
622 num_tile_pipes = R6XX_MAX_PIPES;
623 if (num_tile_pipes < 1)
624 num_tile_pipes = 1;
625 if (num_backends > R6XX_MAX_BACKENDS)
626 num_backends = R6XX_MAX_BACKENDS;
627 if (num_backends < 1)
628 num_backends = 1;
629
630 enabled_backends_mask = 0;
631 enabled_backends_count = 0;
632 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
633 if (((backend_disable_mask >> i) & 1) == 0) {
634 enabled_backends_mask |= (1 << i);
635 ++enabled_backends_count;
636 }
637 if (enabled_backends_count == num_backends)
638 break;
639 }
640
641 if (enabled_backends_count == 0) {
642 enabled_backends_mask = 1;
643 enabled_backends_count = 1;
644 }
645
646 if (enabled_backends_count != num_backends)
647 num_backends = enabled_backends_count;
648
649 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
650 switch (num_tile_pipes) {
651 case 1:
652 swizzle_pipe[0] = 0;
653 break;
654 case 2:
655 swizzle_pipe[0] = 0;
656 swizzle_pipe[1] = 1;
657 break;
658 case 3:
659 swizzle_pipe[0] = 0;
660 swizzle_pipe[1] = 1;
661 swizzle_pipe[2] = 2;
662 break;
663 case 4:
664 swizzle_pipe[0] = 0;
665 swizzle_pipe[1] = 1;
666 swizzle_pipe[2] = 2;
667 swizzle_pipe[3] = 3;
668 break;
669 case 5:
670 swizzle_pipe[0] = 0;
671 swizzle_pipe[1] = 1;
672 swizzle_pipe[2] = 2;
673 swizzle_pipe[3] = 3;
674 swizzle_pipe[4] = 4;
675 break;
676 case 6:
677 swizzle_pipe[0] = 0;
678 swizzle_pipe[1] = 2;
679 swizzle_pipe[2] = 4;
680 swizzle_pipe[3] = 5;
681 swizzle_pipe[4] = 1;
682 swizzle_pipe[5] = 3;
683 break;
684 case 7:
685 swizzle_pipe[0] = 0;
686 swizzle_pipe[1] = 2;
687 swizzle_pipe[2] = 4;
688 swizzle_pipe[3] = 6;
689 swizzle_pipe[4] = 1;
690 swizzle_pipe[5] = 3;
691 swizzle_pipe[6] = 5;
692 break;
693 case 8:
694 swizzle_pipe[0] = 0;
695 swizzle_pipe[1] = 2;
696 swizzle_pipe[2] = 4;
697 swizzle_pipe[3] = 6;
698 swizzle_pipe[4] = 1;
699 swizzle_pipe[5] = 3;
700 swizzle_pipe[6] = 5;
701 swizzle_pipe[7] = 7;
702 break;
703 }
704
705 cur_backend = 0;
706 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
707 while (((1 << cur_backend) & enabled_backends_mask) == 0)
708 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
709
710 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
711
712 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
713 }
714
715 return backend_map;
716 }
717
718 static int r600_count_pipe_bits(uint32_t val)
719 {
720 int i, ret = 0;
721 for (i = 0; i < 32; i++) {
722 ret += val & 1;
723 val >>= 1;
724 }
725 return ret;
726 }
727
728 static void r600_gfx_init(struct drm_device *dev,
729 drm_radeon_private_t *dev_priv)
730 {
731 int i, j, num_qd_pipes;
732 u32 sx_debug_1;
733 u32 tc_cntl;
734 u32 arb_pop;
735 u32 num_gs_verts_per_thread;
736 u32 vgt_gs_per_es;
737 u32 gs_prim_buffer_depth = 0;
738 u32 sq_ms_fifo_sizes;
739 u32 sq_config;
740 u32 sq_gpr_resource_mgmt_1 = 0;
741 u32 sq_gpr_resource_mgmt_2 = 0;
742 u32 sq_thread_resource_mgmt = 0;
743 u32 sq_stack_resource_mgmt_1 = 0;
744 u32 sq_stack_resource_mgmt_2 = 0;
745 u32 hdp_host_path_cntl;
746 u32 backend_map;
747 u32 gb_tiling_config = 0;
748 u32 cc_rb_backend_disable = 0;
749 u32 cc_gc_shader_pipe_config = 0;
750 u32 ramcfg;
751
752 /* setup chip specs */
753 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
754 case CHIP_R600:
755 dev_priv->r600_max_pipes = 4;
756 dev_priv->r600_max_tile_pipes = 8;
757 dev_priv->r600_max_simds = 4;
758 dev_priv->r600_max_backends = 4;
759 dev_priv->r600_max_gprs = 256;
760 dev_priv->r600_max_threads = 192;
761 dev_priv->r600_max_stack_entries = 256;
762 dev_priv->r600_max_hw_contexts = 8;
763 dev_priv->r600_max_gs_threads = 16;
764 dev_priv->r600_sx_max_export_size = 128;
765 dev_priv->r600_sx_max_export_pos_size = 16;
766 dev_priv->r600_sx_max_export_smx_size = 128;
767 dev_priv->r600_sq_num_cf_insts = 2;
768 break;
769 case CHIP_RV630:
770 case CHIP_RV635:
771 dev_priv->r600_max_pipes = 2;
772 dev_priv->r600_max_tile_pipes = 2;
773 dev_priv->r600_max_simds = 3;
774 dev_priv->r600_max_backends = 1;
775 dev_priv->r600_max_gprs = 128;
776 dev_priv->r600_max_threads = 192;
777 dev_priv->r600_max_stack_entries = 128;
778 dev_priv->r600_max_hw_contexts = 8;
779 dev_priv->r600_max_gs_threads = 4;
780 dev_priv->r600_sx_max_export_size = 128;
781 dev_priv->r600_sx_max_export_pos_size = 16;
782 dev_priv->r600_sx_max_export_smx_size = 128;
783 dev_priv->r600_sq_num_cf_insts = 2;
784 break;
785 case CHIP_RV610:
786 case CHIP_RS780:
787 case CHIP_RS880:
788 case CHIP_RV620:
789 dev_priv->r600_max_pipes = 1;
790 dev_priv->r600_max_tile_pipes = 1;
791 dev_priv->r600_max_simds = 2;
792 dev_priv->r600_max_backends = 1;
793 dev_priv->r600_max_gprs = 128;
794 dev_priv->r600_max_threads = 192;
795 dev_priv->r600_max_stack_entries = 128;
796 dev_priv->r600_max_hw_contexts = 4;
797 dev_priv->r600_max_gs_threads = 4;
798 dev_priv->r600_sx_max_export_size = 128;
799 dev_priv->r600_sx_max_export_pos_size = 16;
800 dev_priv->r600_sx_max_export_smx_size = 128;
801 dev_priv->r600_sq_num_cf_insts = 1;
802 break;
803 case CHIP_RV670:
804 dev_priv->r600_max_pipes = 4;
805 dev_priv->r600_max_tile_pipes = 4;
806 dev_priv->r600_max_simds = 4;
807 dev_priv->r600_max_backends = 4;
808 dev_priv->r600_max_gprs = 192;
809 dev_priv->r600_max_threads = 192;
810 dev_priv->r600_max_stack_entries = 256;
811 dev_priv->r600_max_hw_contexts = 8;
812 dev_priv->r600_max_gs_threads = 16;
813 dev_priv->r600_sx_max_export_size = 128;
814 dev_priv->r600_sx_max_export_pos_size = 16;
815 dev_priv->r600_sx_max_export_smx_size = 128;
816 dev_priv->r600_sq_num_cf_insts = 2;
817 break;
818 default:
819 break;
820 }
821
822 /* Initialize HDP */
823 j = 0;
824 for (i = 0; i < 32; i++) {
825 RADEON_WRITE((0x2c14 + j), 0x00000000);
826 RADEON_WRITE((0x2c18 + j), 0x00000000);
827 RADEON_WRITE((0x2c1c + j), 0x00000000);
828 RADEON_WRITE((0x2c20 + j), 0x00000000);
829 RADEON_WRITE((0x2c24 + j), 0x00000000);
830 j += 0x18;
831 }
832
833 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
834
835 /* setup tiling, simd, pipe config */
836 ramcfg = RADEON_READ(R600_RAMCFG);
837
838 switch (dev_priv->r600_max_tile_pipes) {
839 case 1:
840 gb_tiling_config |= R600_PIPE_TILING(0);
841 break;
842 case 2:
843 gb_tiling_config |= R600_PIPE_TILING(1);
844 break;
845 case 4:
846 gb_tiling_config |= R600_PIPE_TILING(2);
847 break;
848 case 8:
849 gb_tiling_config |= R600_PIPE_TILING(3);
850 break;
851 default:
852 break;
853 }
854
855 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
856
857 gb_tiling_config |= R600_GROUP_SIZE(0);
858
859 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
860 gb_tiling_config |= R600_ROW_TILING(3);
861 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
862 } else {
863 gb_tiling_config |=
864 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
865 gb_tiling_config |=
866 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
867 }
868
869 gb_tiling_config |= R600_BANK_SWAPS(1);
870
871 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
872 dev_priv->r600_max_backends,
873 (0xff << dev_priv->r600_max_backends) & 0xff);
874 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
875
876 cc_gc_shader_pipe_config =
877 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
878 cc_gc_shader_pipe_config |=
879 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
880
881 cc_rb_backend_disable =
882 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
883
884 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
885 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
886 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
887
888 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
889 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
890 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
891
892 num_qd_pipes =
893 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
894 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
895 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
896
897 /* set HW defaults for 3D engine */
898 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
899 R600_ROQ_IB2_START(0x2b)));
900
901 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
902 R600_ROQ_END(0x40)));
903
904 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
905 R600_SYNC_GRADIENT |
906 R600_SYNC_WALKER |
907 R600_SYNC_ALIGNER));
908
909 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
910 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
911
912 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
913 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
914 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
915 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
916 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
917
918 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
919 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
922 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
924 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
925 else
926 RADEON_WRITE(R600_DB_DEBUG, 0);
927
928 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
929 R600_DEPTH_FLUSH(16) |
930 R600_DEPTH_PENDING_FREE(4) |
931 R600_DEPTH_CACHELINE_FREE(16)));
932 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
933 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
934
935 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
936 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
937
938 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
939 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
940 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
941 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
942 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
943 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
944 R600_FETCH_FIFO_HIWATER(0xa) |
945 R600_DONE_FIFO_HIWATER(0xe0) |
946 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
947 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
948 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
949 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
950 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
951 }
952 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
953
954 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
955 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
956 */
957 sq_config = RADEON_READ(R600_SQ_CONFIG);
958 sq_config &= ~(R600_PS_PRIO(3) |
959 R600_VS_PRIO(3) |
960 R600_GS_PRIO(3) |
961 R600_ES_PRIO(3));
962 sq_config |= (R600_DX9_CONSTS |
963 R600_VC_ENABLE |
964 R600_PS_PRIO(0) |
965 R600_VS_PRIO(1) |
966 R600_GS_PRIO(2) |
967 R600_ES_PRIO(3));
968
969 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
970 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
971 R600_NUM_VS_GPRS(124) |
972 R600_NUM_CLAUSE_TEMP_GPRS(4));
973 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
974 R600_NUM_ES_GPRS(0));
975 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
976 R600_NUM_VS_THREADS(48) |
977 R600_NUM_GS_THREADS(4) |
978 R600_NUM_ES_THREADS(4));
979 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
980 R600_NUM_VS_STACK_ENTRIES(128));
981 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
982 R600_NUM_ES_STACK_ENTRIES(0));
983 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
984 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
985 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
986 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
987 /* no vertex cache */
988 sq_config &= ~R600_VC_ENABLE;
989
990 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
991 R600_NUM_VS_GPRS(44) |
992 R600_NUM_CLAUSE_TEMP_GPRS(2));
993 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
994 R600_NUM_ES_GPRS(17));
995 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
996 R600_NUM_VS_THREADS(78) |
997 R600_NUM_GS_THREADS(4) |
998 R600_NUM_ES_THREADS(31));
999 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1000 R600_NUM_VS_STACK_ENTRIES(40));
1001 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1002 R600_NUM_ES_STACK_ENTRIES(16));
1003 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1004 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1005 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1006 R600_NUM_VS_GPRS(44) |
1007 R600_NUM_CLAUSE_TEMP_GPRS(2));
1008 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1009 R600_NUM_ES_GPRS(18));
1010 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1011 R600_NUM_VS_THREADS(78) |
1012 R600_NUM_GS_THREADS(4) |
1013 R600_NUM_ES_THREADS(31));
1014 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1015 R600_NUM_VS_STACK_ENTRIES(40));
1016 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1017 R600_NUM_ES_STACK_ENTRIES(16));
1018 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1019 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1020 R600_NUM_VS_GPRS(44) |
1021 R600_NUM_CLAUSE_TEMP_GPRS(2));
1022 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1023 R600_NUM_ES_GPRS(17));
1024 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1025 R600_NUM_VS_THREADS(78) |
1026 R600_NUM_GS_THREADS(4) |
1027 R600_NUM_ES_THREADS(31));
1028 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1029 R600_NUM_VS_STACK_ENTRIES(64));
1030 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1031 R600_NUM_ES_STACK_ENTRIES(64));
1032 }
1033
1034 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1035 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1036 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1037 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1038 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1039 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1040
1041 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1042 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1043 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1044 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1045 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1046 else
1047 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1048
1049 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1050 R600_S0_Y(0x4) |
1051 R600_S1_X(0x4) |
1052 R600_S1_Y(0xc)));
1053 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1054 R600_S0_Y(0xe) |
1055 R600_S1_X(0x2) |
1056 R600_S1_Y(0x2) |
1057 R600_S2_X(0xa) |
1058 R600_S2_Y(0x6) |
1059 R600_S3_X(0x6) |
1060 R600_S3_Y(0xa)));
1061 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1062 R600_S0_Y(0xb) |
1063 R600_S1_X(0x4) |
1064 R600_S1_Y(0xc) |
1065 R600_S2_X(0x1) |
1066 R600_S2_Y(0x6) |
1067 R600_S3_X(0xa) |
1068 R600_S3_Y(0xe)));
1069 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1070 R600_S4_Y(0x1) |
1071 R600_S5_X(0x0) |
1072 R600_S5_Y(0x0) |
1073 R600_S6_X(0xb) |
1074 R600_S6_Y(0x4) |
1075 R600_S7_X(0x7) |
1076 R600_S7_Y(0x8)));
1077
1078
1079 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1080 case CHIP_R600:
1081 case CHIP_RV630:
1082 case CHIP_RV635:
1083 gs_prim_buffer_depth = 0;
1084 break;
1085 case CHIP_RV610:
1086 case CHIP_RS780:
1087 case CHIP_RS880:
1088 case CHIP_RV620:
1089 gs_prim_buffer_depth = 32;
1090 break;
1091 case CHIP_RV670:
1092 gs_prim_buffer_depth = 128;
1093 break;
1094 default:
1095 break;
1096 }
1097
1098 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1099 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1100 /* Max value for this is 256 */
1101 if (vgt_gs_per_es > 256)
1102 vgt_gs_per_es = 256;
1103
1104 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1105 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1106 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1107 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1108
1109 /* more default values. 2D/3D driver should adjust as needed */
1110 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1111 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1112 RADEON_WRITE(R600_SX_MISC, 0);
1113 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1114 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1115 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1116 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1117 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1118 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1119
1120 /* clear render buffer base addresses */
1121 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1122 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1123 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1124 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1125 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1126 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1127 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1128 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1129
1130 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1131 case CHIP_RV610:
1132 case CHIP_RS780:
1133 case CHIP_RS880:
1134 case CHIP_RV620:
1135 tc_cntl = R600_TC_L2_SIZE(8);
1136 break;
1137 case CHIP_RV630:
1138 case CHIP_RV635:
1139 tc_cntl = R600_TC_L2_SIZE(4);
1140 break;
1141 case CHIP_R600:
1142 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1143 break;
1144 default:
1145 tc_cntl = R600_TC_L2_SIZE(0);
1146 break;
1147 }
1148
1149 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1150
1151 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1152 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1153
1154 arb_pop = RADEON_READ(R600_ARB_POP);
1155 arb_pop |= R600_ENABLE_TC128;
1156 RADEON_WRITE(R600_ARB_POP, arb_pop);
1157
1158 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1159 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1160 R600_NUM_CLIP_SEQ(3)));
1161 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1162
1163 }
1164
1165 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1166 u32 num_backends,
1167 u32 backend_disable_mask)
1168 {
1169 u32 backend_map = 0;
1170 u32 enabled_backends_mask;
1171 u32 enabled_backends_count;
1172 u32 cur_pipe;
1173 u32 swizzle_pipe[R7XX_MAX_PIPES];
1174 u32 cur_backend;
1175 u32 i;
1176
1177 if (num_tile_pipes > R7XX_MAX_PIPES)
1178 num_tile_pipes = R7XX_MAX_PIPES;
1179 if (num_tile_pipes < 1)
1180 num_tile_pipes = 1;
1181 if (num_backends > R7XX_MAX_BACKENDS)
1182 num_backends = R7XX_MAX_BACKENDS;
1183 if (num_backends < 1)
1184 num_backends = 1;
1185
1186 enabled_backends_mask = 0;
1187 enabled_backends_count = 0;
1188 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1189 if (((backend_disable_mask >> i) & 1) == 0) {
1190 enabled_backends_mask |= (1 << i);
1191 ++enabled_backends_count;
1192 }
1193 if (enabled_backends_count == num_backends)
1194 break;
1195 }
1196
1197 if (enabled_backends_count == 0) {
1198 enabled_backends_mask = 1;
1199 enabled_backends_count = 1;
1200 }
1201
1202 if (enabled_backends_count != num_backends)
1203 num_backends = enabled_backends_count;
1204
1205 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1206 switch (num_tile_pipes) {
1207 case 1:
1208 swizzle_pipe[0] = 0;
1209 break;
1210 case 2:
1211 swizzle_pipe[0] = 0;
1212 swizzle_pipe[1] = 1;
1213 break;
1214 case 3:
1215 swizzle_pipe[0] = 0;
1216 swizzle_pipe[1] = 2;
1217 swizzle_pipe[2] = 1;
1218 break;
1219 case 4:
1220 swizzle_pipe[0] = 0;
1221 swizzle_pipe[1] = 2;
1222 swizzle_pipe[2] = 3;
1223 swizzle_pipe[3] = 1;
1224 break;
1225 case 5:
1226 swizzle_pipe[0] = 0;
1227 swizzle_pipe[1] = 2;
1228 swizzle_pipe[2] = 4;
1229 swizzle_pipe[3] = 1;
1230 swizzle_pipe[4] = 3;
1231 break;
1232 case 6:
1233 swizzle_pipe[0] = 0;
1234 swizzle_pipe[1] = 2;
1235 swizzle_pipe[2] = 4;
1236 swizzle_pipe[3] = 5;
1237 swizzle_pipe[4] = 3;
1238 swizzle_pipe[5] = 1;
1239 break;
1240 case 7:
1241 swizzle_pipe[0] = 0;
1242 swizzle_pipe[1] = 2;
1243 swizzle_pipe[2] = 4;
1244 swizzle_pipe[3] = 6;
1245 swizzle_pipe[4] = 3;
1246 swizzle_pipe[5] = 1;
1247 swizzle_pipe[6] = 5;
1248 break;
1249 case 8:
1250 swizzle_pipe[0] = 0;
1251 swizzle_pipe[1] = 2;
1252 swizzle_pipe[2] = 4;
1253 swizzle_pipe[3] = 6;
1254 swizzle_pipe[4] = 3;
1255 swizzle_pipe[5] = 1;
1256 swizzle_pipe[6] = 7;
1257 swizzle_pipe[7] = 5;
1258 break;
1259 }
1260
1261 cur_backend = 0;
1262 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1263 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1264 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1265
1266 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1267
1268 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1269 }
1270
1271 return backend_map;
1272 }
1273
1274 static void r700_gfx_init(struct drm_device *dev,
1275 drm_radeon_private_t *dev_priv)
1276 {
1277 int i, j, num_qd_pipes;
1278 u32 sx_debug_1;
1279 u32 smx_dc_ctl0;
1280 u32 num_gs_verts_per_thread;
1281 u32 vgt_gs_per_es;
1282 u32 gs_prim_buffer_depth = 0;
1283 u32 sq_ms_fifo_sizes;
1284 u32 sq_config;
1285 u32 sq_thread_resource_mgmt;
1286 u32 hdp_host_path_cntl;
1287 u32 sq_dyn_gpr_size_simd_ab_0;
1288 u32 backend_map;
1289 u32 gb_tiling_config = 0;
1290 u32 cc_rb_backend_disable = 0;
1291 u32 cc_gc_shader_pipe_config = 0;
1292 u32 mc_arb_ramcfg;
1293 u32 db_debug4;
1294
1295 /* setup chip specs */
1296 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1297 case CHIP_RV770:
1298 dev_priv->r600_max_pipes = 4;
1299 dev_priv->r600_max_tile_pipes = 8;
1300 dev_priv->r600_max_simds = 10;
1301 dev_priv->r600_max_backends = 4;
1302 dev_priv->r600_max_gprs = 256;
1303 dev_priv->r600_max_threads = 248;
1304 dev_priv->r600_max_stack_entries = 512;
1305 dev_priv->r600_max_hw_contexts = 8;
1306 dev_priv->r600_max_gs_threads = 16 * 2;
1307 dev_priv->r600_sx_max_export_size = 128;
1308 dev_priv->r600_sx_max_export_pos_size = 16;
1309 dev_priv->r600_sx_max_export_smx_size = 112;
1310 dev_priv->r600_sq_num_cf_insts = 2;
1311
1312 dev_priv->r700_sx_num_of_sets = 7;
1313 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1314 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1315 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1316 break;
1317 case CHIP_RV730:
1318 dev_priv->r600_max_pipes = 2;
1319 dev_priv->r600_max_tile_pipes = 4;
1320 dev_priv->r600_max_simds = 8;
1321 dev_priv->r600_max_backends = 2;
1322 dev_priv->r600_max_gprs = 128;
1323 dev_priv->r600_max_threads = 248;
1324 dev_priv->r600_max_stack_entries = 256;
1325 dev_priv->r600_max_hw_contexts = 8;
1326 dev_priv->r600_max_gs_threads = 16 * 2;
1327 dev_priv->r600_sx_max_export_size = 256;
1328 dev_priv->r600_sx_max_export_pos_size = 32;
1329 dev_priv->r600_sx_max_export_smx_size = 224;
1330 dev_priv->r600_sq_num_cf_insts = 2;
1331
1332 dev_priv->r700_sx_num_of_sets = 7;
1333 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1334 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1335 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1336 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1337 dev_priv->r600_sx_max_export_pos_size -= 16;
1338 dev_priv->r600_sx_max_export_smx_size += 16;
1339 }
1340 break;
1341 case CHIP_RV710:
1342 dev_priv->r600_max_pipes = 2;
1343 dev_priv->r600_max_tile_pipes = 2;
1344 dev_priv->r600_max_simds = 2;
1345 dev_priv->r600_max_backends = 1;
1346 dev_priv->r600_max_gprs = 256;
1347 dev_priv->r600_max_threads = 192;
1348 dev_priv->r600_max_stack_entries = 256;
1349 dev_priv->r600_max_hw_contexts = 4;
1350 dev_priv->r600_max_gs_threads = 8 * 2;
1351 dev_priv->r600_sx_max_export_size = 128;
1352 dev_priv->r600_sx_max_export_pos_size = 16;
1353 dev_priv->r600_sx_max_export_smx_size = 112;
1354 dev_priv->r600_sq_num_cf_insts = 1;
1355
1356 dev_priv->r700_sx_num_of_sets = 7;
1357 dev_priv->r700_sc_prim_fifo_size = 0x40;
1358 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1359 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1360 break;
1361 case CHIP_RV740:
1362 dev_priv->r600_max_pipes = 4;
1363 dev_priv->r600_max_tile_pipes = 4;
1364 dev_priv->r600_max_simds = 8;
1365 dev_priv->r600_max_backends = 4;
1366 dev_priv->r600_max_gprs = 256;
1367 dev_priv->r600_max_threads = 248;
1368 dev_priv->r600_max_stack_entries = 512;
1369 dev_priv->r600_max_hw_contexts = 8;
1370 dev_priv->r600_max_gs_threads = 16 * 2;
1371 dev_priv->r600_sx_max_export_size = 256;
1372 dev_priv->r600_sx_max_export_pos_size = 32;
1373 dev_priv->r600_sx_max_export_smx_size = 224;
1374 dev_priv->r600_sq_num_cf_insts = 2;
1375
1376 dev_priv->r700_sx_num_of_sets = 7;
1377 dev_priv->r700_sc_prim_fifo_size = 0x100;
1378 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1379 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1380
1381 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1382 dev_priv->r600_sx_max_export_pos_size -= 16;
1383 dev_priv->r600_sx_max_export_smx_size += 16;
1384 }
1385 break;
1386 default:
1387 break;
1388 }
1389
1390 /* Initialize HDP */
1391 j = 0;
1392 for (i = 0; i < 32; i++) {
1393 RADEON_WRITE((0x2c14 + j), 0x00000000);
1394 RADEON_WRITE((0x2c18 + j), 0x00000000);
1395 RADEON_WRITE((0x2c1c + j), 0x00000000);
1396 RADEON_WRITE((0x2c20 + j), 0x00000000);
1397 RADEON_WRITE((0x2c24 + j), 0x00000000);
1398 j += 0x18;
1399 }
1400
1401 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1402
1403 /* setup tiling, simd, pipe config */
1404 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1405
1406 switch (dev_priv->r600_max_tile_pipes) {
1407 case 1:
1408 gb_tiling_config |= R600_PIPE_TILING(0);
1409 break;
1410 case 2:
1411 gb_tiling_config |= R600_PIPE_TILING(1);
1412 break;
1413 case 4:
1414 gb_tiling_config |= R600_PIPE_TILING(2);
1415 break;
1416 case 8:
1417 gb_tiling_config |= R600_PIPE_TILING(3);
1418 break;
1419 default:
1420 break;
1421 }
1422
1423 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1424 gb_tiling_config |= R600_BANK_TILING(1);
1425 else
1426 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1427
1428 gb_tiling_config |= R600_GROUP_SIZE(0);
1429
1430 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1431 gb_tiling_config |= R600_ROW_TILING(3);
1432 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1433 } else {
1434 gb_tiling_config |=
1435 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1436 gb_tiling_config |=
1437 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1438 }
1439
1440 gb_tiling_config |= R600_BANK_SWAPS(1);
1441
1442 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1443 dev_priv->r600_max_backends,
1444 (0xff << dev_priv->r600_max_backends) & 0xff);
1445 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1446
1447 cc_gc_shader_pipe_config =
1448 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1449 cc_gc_shader_pipe_config |=
1450 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1451
1452 cc_rb_backend_disable =
1453 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1454
1455 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1456 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1457 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1458
1459 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1460 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1461 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1462
1463 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1464 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1465 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1466 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1467 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1468
1469 num_qd_pipes =
1470 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1471 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1472 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1473
1474 /* set HW defaults for 3D engine */
1475 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1476 R600_ROQ_IB2_START(0x2b)));
1477
1478 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1479
1480 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1481 R600_SYNC_GRADIENT |
1482 R600_SYNC_WALKER |
1483 R600_SYNC_ALIGNER));
1484
1485 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1486 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1487 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1488
1489 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1490 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1491 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1492 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1493
1494 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1495 R700_GS_FLUSH_CTL(4) |
1496 R700_ACK_FLUSH_CTL(3) |
1497 R700_SYNC_FLUSH_CTL));
1498
1499 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1500 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1501 else {
1502 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1503 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1504 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1505 }
1506
1507 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1508 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1509 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1510
1511 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1512 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1513 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1514
1515 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1516
1517 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1518
1519 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1520
1521 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1522
1523 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1524
1525 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1526 R600_DONE_FIFO_HIWATER(0xe0) |
1527 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1528 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1529 case CHIP_RV770:
1530 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1531 break;
1532 case CHIP_RV730:
1533 case CHIP_RV710:
1534 case CHIP_RV740:
1535 default:
1536 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1537 break;
1538 }
1539 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1540
1541 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1542 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1543 */
1544 sq_config = RADEON_READ(R600_SQ_CONFIG);
1545 sq_config &= ~(R600_PS_PRIO(3) |
1546 R600_VS_PRIO(3) |
1547 R600_GS_PRIO(3) |
1548 R600_ES_PRIO(3));
1549 sq_config |= (R600_DX9_CONSTS |
1550 R600_VC_ENABLE |
1551 R600_EXPORT_SRC_C |
1552 R600_PS_PRIO(0) |
1553 R600_VS_PRIO(1) |
1554 R600_GS_PRIO(2) |
1555 R600_ES_PRIO(3));
1556 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1557 /* no vertex cache */
1558 sq_config &= ~R600_VC_ENABLE;
1559
1560 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1561
1562 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1563 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1564 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1565
1566 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1567 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1568
1569 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1570 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1571 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1572 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1573 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1574 else
1575 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1576 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1577
1578 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1579 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1580
1581 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1582 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1583
1584 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1585 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1586 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1587 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1588
1589 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1590 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1591 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1592 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1593 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1594 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1595 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1596 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1597
1598 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1599 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1600
1601 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1602 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1603 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1604 else
1605 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1606 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1607
1608 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1609 case CHIP_RV770:
1610 case CHIP_RV730:
1611 case CHIP_RV740:
1612 gs_prim_buffer_depth = 384;
1613 break;
1614 case CHIP_RV710:
1615 gs_prim_buffer_depth = 128;
1616 break;
1617 default:
1618 break;
1619 }
1620
1621 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1622 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1623 /* Max value for this is 256 */
1624 if (vgt_gs_per_es > 256)
1625 vgt_gs_per_es = 256;
1626
1627 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1628 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1629 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1630
1631 /* more default values. 2D/3D driver should adjust as needed */
1632 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1633 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1634 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1635 RADEON_WRITE(R600_SX_MISC, 0);
1636 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1637 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1638 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1639 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1640 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1641 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1642 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1643 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1644
1645 /* clear render buffer base addresses */
1646 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1647 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1648 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1649 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1650 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1651 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1652 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1653 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1654
1655 RADEON_WRITE(R700_TCP_CNTL, 0);
1656
1657 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1658 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1659
1660 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1661
1662 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1663 R600_NUM_CLIP_SEQ(3)));
1664
1665 }
1666
1667 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1668 drm_radeon_private_t *dev_priv,
1669 struct drm_file *file_priv)
1670 {
1671 struct drm_radeon_master_private *master_priv;
1672 u32 ring_start;
1673 u64 rptr_addr;
1674
1675 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1676 r700_gfx_init(dev, dev_priv);
1677 else
1678 r600_gfx_init(dev, dev_priv);
1679
1680 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1681 RADEON_READ(R600_GRBM_SOFT_RESET);
1682 DRM_UDELAY(15000);
1683 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1684
1685
1686 /* Set ring buffer size */
1687 #ifdef __BIG_ENDIAN
1688 RADEON_WRITE(R600_CP_RB_CNTL,
1689 RADEON_BUF_SWAP_32BIT |
1690 RADEON_RB_NO_UPDATE |
1691 (dev_priv->ring.rptr_update_l2qw << 8) |
1692 dev_priv->ring.size_l2qw);
1693 #else
1694 RADEON_WRITE(R600_CP_RB_CNTL,
1695 RADEON_RB_NO_UPDATE |
1696 (dev_priv->ring.rptr_update_l2qw << 8) |
1697 dev_priv->ring.size_l2qw);
1698 #endif
1699
1700 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1701
1702 /* Set the write pointer delay */
1703 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1704
1705 #ifdef __BIG_ENDIAN
1706 RADEON_WRITE(R600_CP_RB_CNTL,
1707 RADEON_BUF_SWAP_32BIT |
1708 RADEON_RB_NO_UPDATE |
1709 RADEON_RB_RPTR_WR_ENA |
1710 (dev_priv->ring.rptr_update_l2qw << 8) |
1711 dev_priv->ring.size_l2qw);
1712 #else
1713 RADEON_WRITE(R600_CP_RB_CNTL,
1714 RADEON_RB_NO_UPDATE |
1715 RADEON_RB_RPTR_WR_ENA |
1716 (dev_priv->ring.rptr_update_l2qw << 8) |
1717 dev_priv->ring.size_l2qw);
1718 #endif
1719
1720 /* Initialize the ring buffer's read and write pointers */
1721 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1722 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1723 SET_RING_HEAD(dev_priv, 0);
1724 dev_priv->ring.tail = 0;
1725
1726 #if __OS_HAS_AGP
1727 if (dev_priv->flags & RADEON_IS_AGP) {
1728 rptr_addr = dev_priv->ring_rptr->offset
1729 - dev->agp->base +
1730 dev_priv->gart_vm_start;
1731 } else
1732 #endif
1733 {
1734 rptr_addr = dev_priv->ring_rptr->offset
1735 - ((unsigned long) dev->sg->virtual)
1736 + dev_priv->gart_vm_start;
1737 }
1738 RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1739 rptr_addr & 0xffffffff);
1740 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1741 upper_32_bits(rptr_addr));
1742
1743 #ifdef __BIG_ENDIAN
1744 RADEON_WRITE(R600_CP_RB_CNTL,
1745 RADEON_BUF_SWAP_32BIT |
1746 (dev_priv->ring.rptr_update_l2qw << 8) |
1747 dev_priv->ring.size_l2qw);
1748 #else
1749 RADEON_WRITE(R600_CP_RB_CNTL,
1750 (dev_priv->ring.rptr_update_l2qw << 8) |
1751 dev_priv->ring.size_l2qw);
1752 #endif
1753
1754 #if __OS_HAS_AGP
1755 if (dev_priv->flags & RADEON_IS_AGP) {
1756 /* XXX */
1757 radeon_write_agp_base(dev_priv, dev->agp->base);
1758
1759 /* XXX */
1760 radeon_write_agp_location(dev_priv,
1761 (((dev_priv->gart_vm_start - 1 +
1762 dev_priv->gart_size) & 0xffff0000) |
1763 (dev_priv->gart_vm_start >> 16)));
1764
1765 ring_start = (dev_priv->cp_ring->offset
1766 - dev->agp->base
1767 + dev_priv->gart_vm_start);
1768 } else
1769 #endif
1770 ring_start = (dev_priv->cp_ring->offset
1771 - (unsigned long)dev->sg->virtual
1772 + dev_priv->gart_vm_start);
1773
1774 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1775
1776 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1777
1778 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1779
1780 /* Initialize the scratch register pointer. This will cause
1781 * the scratch register values to be written out to memory
1782 * whenever they are updated.
1783 *
1784 * We simply put this behind the ring read pointer, this works
1785 * with PCI GART as well as (whatever kind of) AGP GART
1786 */
1787 {
1788 u64 scratch_addr;
1789
1790 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1791 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1792 scratch_addr += R600_SCRATCH_REG_OFFSET;
1793 scratch_addr >>= 8;
1794 scratch_addr &= 0xffffffff;
1795
1796 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1797 }
1798
1799 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1800
1801 /* Turn on bus mastering */
1802 radeon_enable_bm(dev_priv);
1803
1804 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1805 RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1806
1807 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1808 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1809
1810 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1811 RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1812
1813 /* reset sarea copies of these */
1814 master_priv = file_priv->master->driver_priv;
1815 if (master_priv->sarea_priv) {
1816 master_priv->sarea_priv->last_frame = 0;
1817 master_priv->sarea_priv->last_dispatch = 0;
1818 master_priv->sarea_priv->last_clear = 0;
1819 }
1820
1821 r600_do_wait_for_idle(dev_priv);
1822
1823 }
1824
1825 int r600_do_cleanup_cp(struct drm_device *dev)
1826 {
1827 drm_radeon_private_t *dev_priv = dev->dev_private;
1828 DRM_DEBUG("\n");
1829
1830 /* Make sure interrupts are disabled here because the uninstall ioctl
1831 * may not have been called from userspace and after dev_private
1832 * is freed, it's too late.
1833 */
1834 if (dev->irq_enabled)
1835 drm_irq_uninstall(dev);
1836
1837 #if __OS_HAS_AGP
1838 if (dev_priv->flags & RADEON_IS_AGP) {
1839 if (dev_priv->cp_ring != NULL) {
1840 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1841 dev_priv->cp_ring = NULL;
1842 }
1843 if (dev_priv->ring_rptr != NULL) {
1844 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1845 dev_priv->ring_rptr = NULL;
1846 }
1847 if (dev->agp_buffer_map != NULL) {
1848 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1849 dev->agp_buffer_map = NULL;
1850 }
1851 } else
1852 #endif
1853 {
1854
1855 if (dev_priv->gart_info.bus_addr)
1856 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1857
1858 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1859 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1860 dev_priv->gart_info.addr = NULL;
1861 }
1862 }
1863 /* only clear to the start of flags */
1864 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1865
1866 return 0;
1867 }
1868
1869 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1870 struct drm_file *file_priv)
1871 {
1872 drm_radeon_private_t *dev_priv = dev->dev_private;
1873 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1874
1875 DRM_DEBUG("\n");
1876
1877 /* if we require new memory map but we don't have it fail */
1878 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1879 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1880 r600_do_cleanup_cp(dev);
1881 return -EINVAL;
1882 }
1883
1884 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1885 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1886 dev_priv->flags &= ~RADEON_IS_AGP;
1887 /* The writeback test succeeds, but when writeback is enabled,
1888 * the ring buffer read ptr update fails after first 128 bytes.
1889 */
1890 radeon_no_wb = 1;
1891 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1892 && !init->is_pci) {
1893 DRM_DEBUG("Restoring AGP flag\n");
1894 dev_priv->flags |= RADEON_IS_AGP;
1895 }
1896
1897 dev_priv->usec_timeout = init->usec_timeout;
1898 if (dev_priv->usec_timeout < 1 ||
1899 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1900 DRM_DEBUG("TIMEOUT problem!\n");
1901 r600_do_cleanup_cp(dev);
1902 return -EINVAL;
1903 }
1904
1905 /* Enable vblank on CRTC1 for older X servers
1906 */
1907 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1908
1909 dev_priv->cp_mode = init->cp_mode;
1910
1911 /* We don't support anything other than bus-mastering ring mode,
1912 * but the ring can be in either AGP or PCI space for the ring
1913 * read pointer.
1914 */
1915 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1916 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1917 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1918 r600_do_cleanup_cp(dev);
1919 return -EINVAL;
1920 }
1921
1922 switch (init->fb_bpp) {
1923 case 16:
1924 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1925 break;
1926 case 32:
1927 default:
1928 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1929 break;
1930 }
1931 dev_priv->front_offset = init->front_offset;
1932 dev_priv->front_pitch = init->front_pitch;
1933 dev_priv->back_offset = init->back_offset;
1934 dev_priv->back_pitch = init->back_pitch;
1935
1936 dev_priv->ring_offset = init->ring_offset;
1937 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1938 dev_priv->buffers_offset = init->buffers_offset;
1939 dev_priv->gart_textures_offset = init->gart_textures_offset;
1940
1941 master_priv->sarea = drm_getsarea(dev);
1942 if (!master_priv->sarea) {
1943 DRM_ERROR("could not find sarea!\n");
1944 r600_do_cleanup_cp(dev);
1945 return -EINVAL;
1946 }
1947
1948 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1949 if (!dev_priv->cp_ring) {
1950 DRM_ERROR("could not find cp ring region!\n");
1951 r600_do_cleanup_cp(dev);
1952 return -EINVAL;
1953 }
1954 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1955 if (!dev_priv->ring_rptr) {
1956 DRM_ERROR("could not find ring read pointer!\n");
1957 r600_do_cleanup_cp(dev);
1958 return -EINVAL;
1959 }
1960 dev->agp_buffer_token = init->buffers_offset;
1961 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1962 if (!dev->agp_buffer_map) {
1963 DRM_ERROR("could not find dma buffer region!\n");
1964 r600_do_cleanup_cp(dev);
1965 return -EINVAL;
1966 }
1967
1968 if (init->gart_textures_offset) {
1969 dev_priv->gart_textures =
1970 drm_core_findmap(dev, init->gart_textures_offset);
1971 if (!dev_priv->gart_textures) {
1972 DRM_ERROR("could not find GART texture region!\n");
1973 r600_do_cleanup_cp(dev);
1974 return -EINVAL;
1975 }
1976 }
1977
1978 #if __OS_HAS_AGP
1979 /* XXX */
1980 if (dev_priv->flags & RADEON_IS_AGP) {
1981 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1982 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1983 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1984 if (!dev_priv->cp_ring->handle ||
1985 !dev_priv->ring_rptr->handle ||
1986 !dev->agp_buffer_map->handle) {
1987 DRM_ERROR("could not find ioremap agp regions!\n");
1988 r600_do_cleanup_cp(dev);
1989 return -EINVAL;
1990 }
1991 } else
1992 #endif
1993 {
1994 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1995 dev_priv->ring_rptr->handle =
1996 (void *)dev_priv->ring_rptr->offset;
1997 dev->agp_buffer_map->handle =
1998 (void *)dev->agp_buffer_map->offset;
1999
2000 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2001 dev_priv->cp_ring->handle);
2002 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2003 dev_priv->ring_rptr->handle);
2004 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2005 dev->agp_buffer_map->handle);
2006 }
2007
2008 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2009 dev_priv->fb_size =
2010 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2011 - dev_priv->fb_location;
2012
2013 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2014 ((dev_priv->front_offset
2015 + dev_priv->fb_location) >> 10));
2016
2017 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2018 ((dev_priv->back_offset
2019 + dev_priv->fb_location) >> 10));
2020
2021 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2022 ((dev_priv->depth_offset
2023 + dev_priv->fb_location) >> 10));
2024
2025 dev_priv->gart_size = init->gart_size;
2026
2027 /* New let's set the memory map ... */
2028 if (dev_priv->new_memmap) {
2029 u32 base = 0;
2030
2031 DRM_INFO("Setting GART location based on new memory map\n");
2032
2033 /* If using AGP, try to locate the AGP aperture at the same
2034 * location in the card and on the bus, though we have to
2035 * align it down.
2036 */
2037 #if __OS_HAS_AGP
2038 /* XXX */
2039 if (dev_priv->flags & RADEON_IS_AGP) {
2040 base = dev->agp->base;
2041 /* Check if valid */
2042 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2043 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2044 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2045 dev->agp->base);
2046 base = 0;
2047 }
2048 }
2049 #endif
2050 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2051 if (base == 0) {
2052 base = dev_priv->fb_location + dev_priv->fb_size;
2053 if (base < dev_priv->fb_location ||
2054 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2055 base = dev_priv->fb_location
2056 - dev_priv->gart_size;
2057 }
2058 dev_priv->gart_vm_start = base & 0xffc00000u;
2059 if (dev_priv->gart_vm_start != base)
2060 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2061 base, dev_priv->gart_vm_start);
2062 }
2063
2064 #if __OS_HAS_AGP
2065 /* XXX */
2066 if (dev_priv->flags & RADEON_IS_AGP)
2067 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2068 - dev->agp->base
2069 + dev_priv->gart_vm_start);
2070 else
2071 #endif
2072 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2073 - (unsigned long)dev->sg->virtual
2074 + dev_priv->gart_vm_start);
2075
2076 DRM_DEBUG("fb 0x%08x size %d\n",
2077 (unsigned int) dev_priv->fb_location,
2078 (unsigned int) dev_priv->fb_size);
2079 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2080 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2081 (unsigned int) dev_priv->gart_vm_start);
2082 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2083 dev_priv->gart_buffers_offset);
2084
2085 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2086 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2087 + init->ring_size / sizeof(u32));
2088 dev_priv->ring.size = init->ring_size;
2089 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2090
2091 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2092 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2093
2094 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2095 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2096
2097 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2098
2099 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2100
2101 #if __OS_HAS_AGP
2102 if (dev_priv->flags & RADEON_IS_AGP) {
2103 /* XXX turn off pcie gart */
2104 } else
2105 #endif
2106 {
2107 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2108 /* if we have an offset set from userspace */
2109 if (!dev_priv->pcigart_offset_set) {
2110 DRM_ERROR("Need gart offset from userspace\n");
2111 r600_do_cleanup_cp(dev);
2112 return -EINVAL;
2113 }
2114
2115 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2116
2117 dev_priv->gart_info.bus_addr =
2118 dev_priv->pcigart_offset + dev_priv->fb_location;
2119 dev_priv->gart_info.mapping.offset =
2120 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2121 dev_priv->gart_info.mapping.size =
2122 dev_priv->gart_info.table_size;
2123
2124 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2125 if (!dev_priv->gart_info.mapping.handle) {
2126 DRM_ERROR("ioremap failed.\n");
2127 r600_do_cleanup_cp(dev);
2128 return -EINVAL;
2129 }
2130
2131 dev_priv->gart_info.addr =
2132 dev_priv->gart_info.mapping.handle;
2133
2134 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2135 dev_priv->gart_info.addr,
2136 dev_priv->pcigart_offset);
2137
2138 if (!r600_page_table_init(dev)) {
2139 DRM_ERROR("Failed to init GART table\n");
2140 r600_do_cleanup_cp(dev);
2141 return -EINVAL;
2142 }
2143
2144 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2145 r700_vm_init(dev);
2146 else
2147 r600_vm_init(dev);
2148 }
2149
2150 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2151 r700_cp_load_microcode(dev_priv);
2152 else
2153 r600_cp_load_microcode(dev_priv);
2154
2155 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2156
2157 dev_priv->last_buf = 0;
2158
2159 r600_do_engine_reset(dev);
2160 r600_test_writeback(dev_priv);
2161
2162 return 0;
2163 }
2164
2165 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2166 {
2167 drm_radeon_private_t *dev_priv = dev->dev_private;
2168
2169 DRM_DEBUG("\n");
2170 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2171 r700_vm_init(dev);
2172 r700_cp_load_microcode(dev_priv);
2173 } else {
2174 r600_vm_init(dev);
2175 r600_cp_load_microcode(dev_priv);
2176 }
2177 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2178 r600_do_engine_reset(dev);
2179
2180 return 0;
2181 }
2182
2183 /* Wait for the CP to go idle.
2184 */
2185 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2186 {
2187 RING_LOCALS;
2188 DRM_DEBUG("\n");
2189
2190 BEGIN_RING(5);
2191 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2192 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2193 /* wait for 3D idle clean */
2194 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2195 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2196 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2197
2198 ADVANCE_RING();
2199 COMMIT_RING();
2200
2201 return r600_do_wait_for_idle(dev_priv);
2202 }
2203
2204 /* Start the Command Processor.
2205 */
2206 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2207 {
2208 u32 cp_me;
2209 RING_LOCALS;
2210 DRM_DEBUG("\n");
2211
2212 BEGIN_RING(7);
2213 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2214 OUT_RING(0x00000001);
2215 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2216 OUT_RING(0x00000003);
2217 else
2218 OUT_RING(0x00000000);
2219 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2220 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2221 OUT_RING(0x00000000);
2222 OUT_RING(0x00000000);
2223 ADVANCE_RING();
2224 COMMIT_RING();
2225
2226 /* set the mux and reset the halt bit */
2227 cp_me = 0xff;
2228 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2229
2230 dev_priv->cp_running = 1;
2231
2232 }
2233
2234 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2235 {
2236 u32 cur_read_ptr;
2237 DRM_DEBUG("\n");
2238
2239 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2240 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2241 SET_RING_HEAD(dev_priv, cur_read_ptr);
2242 dev_priv->ring.tail = cur_read_ptr;
2243 }
2244
2245 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2246 {
2247 uint32_t cp_me;
2248
2249 DRM_DEBUG("\n");
2250
2251 cp_me = 0xff | R600_CP_ME_HALT;
2252
2253 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2254
2255 dev_priv->cp_running = 0;
2256 }
2257
2258 int r600_cp_dispatch_indirect(struct drm_device *dev,
2259 struct drm_buf *buf, int start, int end)
2260 {
2261 drm_radeon_private_t *dev_priv = dev->dev_private;
2262 RING_LOCALS;
2263
2264 if (start != end) {
2265 unsigned long offset = (dev_priv->gart_buffers_offset
2266 + buf->offset + start);
2267 int dwords = (end - start + 3) / sizeof(u32);
2268
2269 DRM_DEBUG("dwords:%d\n", dwords);
2270 DRM_DEBUG("offset 0x%lx\n", offset);
2271
2272
2273 /* Indirect buffer data must be a multiple of 16 dwords.
2274 * pad the data with a Type-2 CP packet.
2275 */
2276 while (dwords & 0xf) {
2277 u32 *data = (u32 *)
2278 ((char *)dev->agp_buffer_map->handle
2279 + buf->offset + start);
2280 data[dwords++] = RADEON_CP_PACKET2;
2281 }
2282
2283 /* Fire off the indirect buffer */
2284 BEGIN_RING(4);
2285 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2286 OUT_RING((offset & 0xfffffffc));
2287 OUT_RING((upper_32_bits(offset) & 0xff));
2288 OUT_RING(dwords);
2289 ADVANCE_RING();
2290 }
2291
2292 return 0;
2293 }
Linux with added FPC-III support