drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 #include "radeon_object.h"
  32
  33 /* TODO: Here are things that needs to be done :
  34  *      - surface allocator & initializer : (bit like scratch reg) should
  35  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  36  *        related to surface
  37  *      - WB : write back stuff (do it bit like scratch reg things)
  38  *      - Vblank : look at Jesse's rework and what we should do
  39  *      - r600/r700: gart & cp
  40  *      - cs : clean cs ioctl use bitmap & things like that.
  41  *      - power management stuff
  42  *      - Barrier in gart code
  43  *      - Unmappabled vram ?
  44  *      - TESTING, TESTING, TESTING
  45  */
  46
  47 #include <asm/atomic.h>
  48 #include <linux/wait.h>
  49 #include <linux/list.h>
  50 #include <linux/kref.h>
  51
  52 #include "radeon_mode.h"
  53 #include "radeon_reg.h"
  54 #include "r300.h"
  55
  56 /*
  57  * Modules parameters.
  58  */
  59 extern int radeon_no_wb;
  60 extern int radeon_modeset;
  61 extern int radeon_dynclks;
  62 extern int radeon_r4xx_atom;
  63 extern int radeon_agpmode;
  64 extern int radeon_vram_limit;
  65 extern int radeon_gart_size;
  66 extern int radeon_benchmarking;
  67 extern int radeon_testing;
  68 extern int radeon_connector_table;
  69
  70 /*
  71  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  72  * symbol;
  73  */
  74 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  75 #define RADEON_IB_POOL_SIZE             16
  76 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  77 #define RADEONFB_CONN_LIMIT             4
  78
  79 enum radeon_family {
  80         CHIP_R100,
  81         CHIP_RV100,
  82         CHIP_RS100,
  83         CHIP_RV200,
  84         CHIP_RS200,
  85         CHIP_R200,
  86         CHIP_RV250,
  87         CHIP_RS300,
  88         CHIP_RV280,
  89         CHIP_R300,
  90         CHIP_R350,
  91         CHIP_RV350,
  92         CHIP_RV380,
  93         CHIP_R420,
  94         CHIP_R423,
  95         CHIP_RV410,
  96         CHIP_RS400,
  97         CHIP_RS480,
  98         CHIP_RS600,
  99         CHIP_RS690,
 100         CHIP_RS740,
 101         CHIP_RV515,
 102         CHIP_R520,
 103         CHIP_RV530,
 104         CHIP_RV560,
 105         CHIP_RV570,
 106         CHIP_R580,
 107         CHIP_R600,
 108         CHIP_RV610,
 109         CHIP_RV630,
 110         CHIP_RV620,
 111         CHIP_RV635,
 112         CHIP_RV670,
 113         CHIP_RS780,
 114         CHIP_RV770,
 115         CHIP_RV730,
 116         CHIP_RV710,
 117         CHIP_RS880,
 118         CHIP_LAST,
 119 };
 120
 121 enum radeon_chip_flags {
 122         RADEON_FAMILY_MASK = 0x0000ffffUL,
 123         RADEON_FLAGS_MASK = 0xffff0000UL,
 124         RADEON_IS_MOBILITY = 0x00010000UL,
 125         RADEON_IS_IGP = 0x00020000UL,
 126         RADEON_SINGLE_CRTC = 0x00040000UL,
 127         RADEON_IS_AGP = 0x00080000UL,
 128         RADEON_HAS_HIERZ = 0x00100000UL,
 129         RADEON_IS_PCIE = 0x00200000UL,
 130         RADEON_NEW_MEMMAP = 0x00400000UL,
 131         RADEON_IS_PCI = 0x00800000UL,
 132         RADEON_IS_IGPGART = 0x01000000UL,
 133 };
 134
 135
 136 /*
 137  * Errata workarounds.
 138  */
 139 enum radeon_pll_errata {
 140         CHIP_ERRATA_R300_CG             = 0x00000001,
 141         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 142         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 143 };
 144
 145
 146 struct radeon_device;
 147
 148
 149 /*
 150  * BIOS.
 151  */
 152 bool radeon_get_bios(struct radeon_device *rdev);
 153
 154 /*
 155  * Clocks
 156  */
 157
 158 struct radeon_clock {
 159         struct radeon_pll p1pll;
 160         struct radeon_pll p2pll;
 161         struct radeon_pll spll;
 162         struct radeon_pll mpll;
 163         /* 10 Khz units */
 164         uint32_t default_mclk;
 165         uint32_t default_sclk;
 166 };
 167
 168 /*
 169  * Fences.
 170  */
 171 struct radeon_fence_driver {
 172         uint32_t                        scratch_reg;
 173         atomic_t                        seq;
 174         uint32_t                        last_seq;
 175         unsigned long                   count_timeout;
 176         wait_queue_head_t               queue;
 177         rwlock_t                        lock;
 178         struct list_head                created;
 179         struct list_head                emited;
 180         struct list_head                signaled;
 181 };
 182
 183 struct radeon_fence {
 184         struct radeon_device            *rdev;
 185         struct kref                     kref;
 186         struct list_head                list;
 187         /* protected by radeon_fence.lock */
 188         uint32_t                        seq;
 189         unsigned long                   timeout;
 190         bool                            emited;
 191         bool                            signaled;
 192 };
 193
 194 int radeon_fence_driver_init(struct radeon_device *rdev);
 195 void radeon_fence_driver_fini(struct radeon_device *rdev);
 196 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 197 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 198 void radeon_fence_process(struct radeon_device *rdev);
 199 bool radeon_fence_signaled(struct radeon_fence *fence);
 200 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 201 int radeon_fence_wait_next(struct radeon_device *rdev);
 202 int radeon_fence_wait_last(struct radeon_device *rdev);
 203 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 204 void radeon_fence_unref(struct radeon_fence **fence);
 205
 206 /*
 207  * Tiling registers
 208  */
 209 struct radeon_surface_reg {
 210         struct radeon_object *robj;
 211 };
 212
 213 #define RADEON_GEM_MAX_SURFACES 8
 214
 215 /*
 216  * Radeon buffer.
 217  */
 218 struct radeon_object;
 219
 220 struct radeon_object_list {
 221         struct list_head        list;
 222         struct radeon_object    *robj;
 223         uint64_t                gpu_offset;
 224         unsigned                rdomain;
 225         unsigned                wdomain;
 226         uint32_t                tiling_flags;
 227 };
 228
 229 int radeon_object_init(struct radeon_device *rdev);
 230 void radeon_object_fini(struct radeon_device *rdev);
 231 int radeon_object_create(struct radeon_device *rdev,
 232                          struct drm_gem_object *gobj,
 233                          unsigned long size,
 234                          bool kernel,
 235                          uint32_t domain,
 236                          bool interruptible,
 237                          struct radeon_object **robj_ptr);
 238 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
 239 void radeon_object_kunmap(struct radeon_object *robj);
 240 void radeon_object_unref(struct radeon_object **robj);
 241 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
 242                       uint64_t *gpu_addr);
 243 void radeon_object_unpin(struct radeon_object *robj);
 244 int radeon_object_wait(struct radeon_object *robj);
 245 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
 246 int radeon_object_evict_vram(struct radeon_device *rdev);
 247 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
 248 void radeon_object_force_delete(struct radeon_device *rdev);
 249 void radeon_object_list_add_object(struct radeon_object_list *lobj,
 250                                    struct list_head *head);
 251 int radeon_object_list_validate(struct list_head *head, void *fence);
 252 void radeon_object_list_unvalidate(struct list_head *head);
 253 void radeon_object_list_clean(struct list_head *head);
 254 int radeon_object_fbdev_mmap(struct radeon_object *robj,
 255                              struct vm_area_struct *vma);
 256 unsigned long radeon_object_size(struct radeon_object *robj);
 257 void radeon_object_clear_surface_reg(struct radeon_object *robj);
 258 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
 259                                bool force_drop);
 260 void radeon_object_set_tiling_flags(struct radeon_object *robj,
 261                                     uint32_t tiling_flags, uint32_t pitch);
 262 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
 263 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 264                            struct ttm_mem_reg *mem);
 265 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 266 /*
 267  * GEM objects.
 268  */
 269 struct radeon_gem {
 270         struct list_head        objects;
 271 };
 272
 273 int radeon_gem_init(struct radeon_device *rdev);
 274 void radeon_gem_fini(struct radeon_device *rdev);
 275 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 276                              int alignment, int initial_domain,
 277                              bool discardable, bool kernel,
 278                              bool interruptible,
 279                              struct drm_gem_object **obj);
 280 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 281                           uint64_t *gpu_addr);
 282 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 283
 284
 285 /*
 286  * GART structures, functions & helpers
 287  */
 288 struct radeon_mc;
 289
 290 struct radeon_gart_table_ram {
 291         volatile uint32_t               *ptr;
 292 };
 293
 294 struct radeon_gart_table_vram {
 295         struct radeon_object            *robj;
 296         volatile uint32_t               *ptr;
 297 };
 298
 299 union radeon_gart_table {
 300         struct radeon_gart_table_ram    ram;
 301         struct radeon_gart_table_vram   vram;
 302 };
 303
 304 struct radeon_gart {
 305         dma_addr_t                      table_addr;
 306         unsigned                        num_gpu_pages;
 307         unsigned                        num_cpu_pages;
 308         unsigned                        table_size;
 309         union radeon_gart_table         table;
 310         struct page                     **pages;
 311         dma_addr_t                      *pages_addr;
 312         bool                            ready;
 313 };
 314
 315 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 316 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 317 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 318 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 319 int radeon_gart_init(struct radeon_device *rdev);
 320 void radeon_gart_fini(struct radeon_device *rdev);
 321 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 322                         int pages);
 323 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 324                      int pages, struct page **pagelist);
 325
 326
 327 /*
 328  * GPU MC structures, functions & helpers
 329  */
 330 struct radeon_mc {
 331         resource_size_t         aper_size;
 332         resource_size_t         aper_base;
 333         resource_size_t         agp_base;
 334         unsigned                gtt_location;
 335         unsigned                gtt_size;
 336         unsigned                vram_location;
 337         /* for some chips with <= 32MB we need to lie
 338          * about vram size near mc fb location */
 339         unsigned                mc_vram_size;
 340         unsigned                vram_width;
 341         unsigned                real_vram_size;
 342         int                     vram_mtrr;
 343         bool                    vram_is_ddr;
 344 };
 345
 346 int radeon_mc_setup(struct radeon_device *rdev);
 347
 348
 349 /*
 350  * GPU scratch registers structures, functions & helpers
 351  */
 352 struct radeon_scratch {
 353         unsigned                num_reg;
 354         bool                    free[32];
 355         uint32_t                reg[32];
 356 };
 357
 358 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 359 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 360
 361
 362 /*
 363  * IRQS.
 364  */
 365 struct radeon_irq {
 366         bool            installed;
 367         bool            sw_int;
 368         /* FIXME: use a define max crtc rather than hardcode it */
 369         bool            crtc_vblank_int[2];
 370 };
 371
 372 int radeon_irq_kms_init(struct radeon_device *rdev);
 373 void radeon_irq_kms_fini(struct radeon_device *rdev);
 374
 375
 376 /*
 377  * CP & ring.
 378  */
 379 struct radeon_ib {
 380         struct list_head        list;
 381         unsigned long           idx;
 382         uint64_t                gpu_addr;
 383         struct radeon_fence     *fence;
 384         volatile uint32_t       *ptr;
 385         uint32_t                length_dw;
 386 };
 387
 388 struct radeon_ib_pool {
 389         struct mutex            mutex;
 390         struct radeon_object    *robj;
 391         struct list_head        scheduled_ibs;
 392         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 393         bool                    ready;
 394         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
 395 };
 396
 397 struct radeon_cp {
 398         struct radeon_object    *ring_obj;
 399         volatile uint32_t       *ring;
 400         unsigned                rptr;
 401         unsigned                wptr;
 402         unsigned                wptr_old;
 403         unsigned                ring_size;
 404         unsigned                ring_free_dw;
 405         int                     count_dw;
 406         uint64_t                gpu_addr;
 407         uint32_t                align_mask;
 408         uint32_t                ptr_mask;
 409         struct mutex            mutex;
 410         bool                    ready;
 411 };
 412
 413 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 414 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 415 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 416 int radeon_ib_pool_init(struct radeon_device *rdev);
 417 void radeon_ib_pool_fini(struct radeon_device *rdev);
 418 int radeon_ib_test(struct radeon_device *rdev);
 419 /* Ring access between begin & end cannot sleep */
 420 void radeon_ring_free_size(struct radeon_device *rdev);
 421 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 422 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 423 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 424 int radeon_ring_test(struct radeon_device *rdev);
 425 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 426 void radeon_ring_fini(struct radeon_device *rdev);
 427
 428
 429 /*
 430  * CS.
 431  */
 432 struct radeon_cs_reloc {
 433         struct drm_gem_object           *gobj;
 434         struct radeon_object            *robj;
 435         struct radeon_object_list       lobj;
 436         uint32_t                        handle;
 437         uint32_t                        flags;
 438 };
 439
 440 struct radeon_cs_chunk {
 441         uint32_t                chunk_id;
 442         uint32_t                length_dw;
 443         uint32_t                *kdata;
 444 };
 445
 446 struct radeon_cs_parser {
 447         struct radeon_device    *rdev;
 448         struct drm_file         *filp;
 449         /* chunks */
 450         unsigned                nchunks;
 451         struct radeon_cs_chunk  *chunks;
 452         uint64_t                *chunks_array;
 453         /* IB */
 454         unsigned                idx;
 455         /* relocations */
 456         unsigned                nrelocs;
 457         struct radeon_cs_reloc  *relocs;
 458         struct radeon_cs_reloc  **relocs_ptr;
 459         struct list_head        validated;
 460         /* indices of various chunks */
 461         int                     chunk_ib_idx;
 462         int                     chunk_relocs_idx;
 463         struct radeon_ib        *ib;
 464         void                    *track;
 465 };
 466
 467 struct radeon_cs_packet {
 468         unsigned        idx;
 469         unsigned        type;
 470         unsigned        reg;
 471         unsigned        opcode;
 472         int             count;
 473         unsigned        one_reg_wr;
 474 };
 475
 476 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 477                                       struct radeon_cs_packet *pkt,
 478                                       unsigned idx, unsigned reg);
 479 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 480                                       struct radeon_cs_packet *pkt);
 481
 482
 483 /*
 484  * AGP
 485  */
 486 int radeon_agp_init(struct radeon_device *rdev);
 487 void radeon_agp_fini(struct radeon_device *rdev);
 488
 489
 490 /*
 491  * Writeback
 492  */
 493 struct radeon_wb {
 494         struct radeon_object    *wb_obj;
 495         volatile uint32_t       *wb;
 496         uint64_t                gpu_addr;
 497 };
 498
 499 /**
 500  * struct radeon_pm - power management datas
 501  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 502  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 503  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 504  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 505  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 506  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 507  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 508  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 509  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 510  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 511  * @needed_bandwidth:   current bandwidth needs
 512  *
 513  * It keeps track of various data needed to take powermanagement decision.
 514  * Bandwith need is used to determine minimun clock of the GPU and memory.
 515  * Equation between gpu/memory clock and available bandwidth is hw dependent
 516  * (type of memory, bus size, efficiency, ...)
 517  */
 518 struct radeon_pm {
 519         fixed20_12              max_bandwidth;
 520         fixed20_12              igp_sideport_mclk;
 521         fixed20_12              igp_system_mclk;
 522         fixed20_12              igp_ht_link_clk;
 523         fixed20_12              igp_ht_link_width;
 524         fixed20_12              k8_bandwidth;
 525         fixed20_12              sideport_bandwidth;
 526         fixed20_12              ht_bandwidth;
 527         fixed20_12              core_bandwidth;
 528         fixed20_12              sclk;
 529         fixed20_12              needed_bandwidth;
 530 };
 531
 532
 533 /*
 534  * Benchmarking
 535  */
 536 void radeon_benchmark(struct radeon_device *rdev);
 537
 538
 539 /*
 540  * Testing
 541  */
 542 void radeon_test_moves(struct radeon_device *rdev);
 543
 544
 545 /*
 546  * Debugfs
 547  */
 548 int radeon_debugfs_add_files(struct radeon_device *rdev,
 549                              struct drm_info_list *files,
 550                              unsigned nfiles);
 551 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 552 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 553 int r100_debugfs_cp_init(struct radeon_device *rdev);
 554
 555
 556 /*
 557  * ASIC specific functions.
 558  */
 559 struct radeon_asic {
 560         int (*init)(struct radeon_device *rdev);
 561         void (*errata)(struct radeon_device *rdev);
 562         void (*vram_info)(struct radeon_device *rdev);
 563         int (*gpu_reset)(struct radeon_device *rdev);
 564         int (*mc_init)(struct radeon_device *rdev);
 565         void (*mc_fini)(struct radeon_device *rdev);
 566         int (*wb_init)(struct radeon_device *rdev);
 567         void (*wb_fini)(struct radeon_device *rdev);
 568         int (*gart_enable)(struct radeon_device *rdev);
 569         void (*gart_disable)(struct radeon_device *rdev);
 570         void (*gart_tlb_flush)(struct radeon_device *rdev);
 571         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 572         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 573         void (*cp_fini)(struct radeon_device *rdev);
 574         void (*cp_disable)(struct radeon_device *rdev);
 575         void (*ring_start)(struct radeon_device *rdev);
 576         int (*irq_set)(struct radeon_device *rdev);
 577         int (*irq_process)(struct radeon_device *rdev);
 578         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 579         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 580         int (*cs_parse)(struct radeon_cs_parser *p);
 581         int (*copy_blit)(struct radeon_device *rdev,
 582                          uint64_t src_offset,
 583                          uint64_t dst_offset,
 584                          unsigned num_pages,
 585                          struct radeon_fence *fence);
 586         int (*copy_dma)(struct radeon_device *rdev,
 587                         uint64_t src_offset,
 588                         uint64_t dst_offset,
 589                         unsigned num_pages,
 590                         struct radeon_fence *fence);
 591         int (*copy)(struct radeon_device *rdev,
 592                     uint64_t src_offset,
 593                     uint64_t dst_offset,
 594                     unsigned num_pages,
 595                     struct radeon_fence *fence);
 596         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 597         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 598         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 599         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 600         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 601                                uint32_t tiling_flags, uint32_t pitch,
 602                                uint32_t offset, uint32_t obj_size);
 603         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 604         void (*bandwidth_update)(struct radeon_device *rdev);
 605 };
 606
 607 union radeon_asic_config {
 608         struct r300_asic        r300;
 609 };
 610
 611
 612 /*
 613  * IOCTL.
 614  */
 615 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
 616                           struct drm_file *filp);
 617 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
 618                             struct drm_file *filp);
 619 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 620                          struct drm_file *file_priv);
 621 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 622                            struct drm_file *file_priv);
 623 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 624                             struct drm_file *file_priv);
 625 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
 626                            struct drm_file *file_priv);
 627 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 628                                 struct drm_file *filp);
 629 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 630                           struct drm_file *filp);
 631 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 632                           struct drm_file *filp);
 633 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 634                               struct drm_file *filp);
 635 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 636 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 637                                 struct drm_file *filp);
 638 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 639                                 struct drm_file *filp);
 640
 641
 642 /*
 643  * Core structure, functions and helpers.
 644  */
 645 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 646 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 647
 648 struct radeon_device {
 649         struct drm_device               *ddev;
 650         struct pci_dev                  *pdev;
 651         /* ASIC */
 652         union radeon_asic_config        config;
 653         enum radeon_family              family;
 654         unsigned long                   flags;
 655         int                             usec_timeout;
 656         enum radeon_pll_errata          pll_errata;
 657         int                             num_gb_pipes;
 658         int                             num_z_pipes;
 659         int                             disp_priority;
 660         /* BIOS */
 661         uint8_t                         *bios;
 662         bool                            is_atom_bios;
 663         uint16_t                        bios_header_start;
 664         struct radeon_object            *stollen_vga_memory;
 665         struct fb_info                  *fbdev_info;
 666         struct radeon_object            *fbdev_robj;
 667         struct radeon_framebuffer       *fbdev_rfb;
 668         /* Register mmio */
 669         resource_size_t                 rmmio_base;
 670         resource_size_t                 rmmio_size;
 671         void                            *rmmio;
 672         radeon_rreg_t                   mc_rreg;
 673         radeon_wreg_t                   mc_wreg;
 674         radeon_rreg_t                   pll_rreg;
 675         radeon_wreg_t                   pll_wreg;
 676         uint32_t                        pcie_reg_mask;
 677         radeon_rreg_t                   pciep_rreg;
 678         radeon_wreg_t                   pciep_wreg;
 679         struct radeon_clock             clock;
 680         struct radeon_mc                mc;
 681         struct radeon_gart              gart;
 682         struct radeon_mode_info         mode_info;
 683         struct radeon_scratch           scratch;
 684         struct radeon_mman              mman;
 685         struct radeon_fence_driver      fence_drv;
 686         struct radeon_cp                cp;
 687         struct radeon_ib_pool           ib_pool;
 688         struct radeon_irq               irq;
 689         struct radeon_asic              *asic;
 690         struct radeon_gem               gem;
 691         struct radeon_pm                pm;
 692         struct mutex                    cs_mutex;
 693         struct radeon_wb                wb;
 694         bool                            gpu_lockup;
 695         bool                            shutdown;
 696         bool                            suspend;
 697         bool                            need_dma32;
 698         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
 699 };
 700
 701 int radeon_device_init(struct radeon_device *rdev,
 702                        struct drm_device *ddev,
 703                        struct pci_dev *pdev,
 704                        uint32_t flags);
 705 void radeon_device_fini(struct radeon_device *rdev);
 706 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 707
 708 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 709 {
 710         if (reg < 0x10000)
 711                 return readl(((void __iomem *)rdev->rmmio) + reg);
 712         else {
 713                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 714                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 715         }
 716 }
 717
 718 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 719 {
 720         if (reg < 0x10000)
 721                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
 722         else {
 723                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 724                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 725         }
 726 }
 727
 728
 729 /*
 730  * Registers read & write functions.
 731  */
 732 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
 733 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
 734 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
 735 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
 736 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 737 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 738 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
 739 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
 740 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
 741 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
 742 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
 743 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
 744 #define WREG32_P(reg, val, mask)                                \
 745         do {                                                    \
 746                 uint32_t tmp_ = RREG32(reg);                    \
 747                 tmp_ &= (mask);                                 \
 748                 tmp_ |= ((val) & ~(mask));                      \
 749                 WREG32(reg, tmp_);                              \
 750         } while (0)
 751 #define WREG32_PLL_P(reg, val, mask)                            \
 752         do {                                                    \
 753                 uint32_t tmp_ = RREG32_PLL(reg);                \
 754                 tmp_ &= (mask);                                 \
 755                 tmp_ |= ((val) & ~(mask));                      \
 756                 WREG32_PLL(reg, tmp_);                          \
 757         } while (0)
 758
 759 /*
 760  * Indirect registers accessor
 761  */
 762 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 763 {
 764         uint32_t r;
 765
 766         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 767         r = RREG32(RADEON_PCIE_DATA);
 768         return r;
 769 }
 770
 771 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 772 {
 773         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 774         WREG32(RADEON_PCIE_DATA, (v));
 775 }
 776
 777 void r100_pll_errata_after_index(struct radeon_device *rdev);
 778
 779
 780 /*
 781  * ASICs helpers.
 782  */
 783 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
 784                             (rdev->pdev->device == 0x5969))
 785 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
 786                 (rdev->family == CHIP_RV200) || \
 787                 (rdev->family == CHIP_RS100) || \
 788                 (rdev->family == CHIP_RS200) || \
 789                 (rdev->family == CHIP_RV250) || \
 790                 (rdev->family == CHIP_RV280) || \
 791                 (rdev->family == CHIP_RS300))
 792 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
 793                 (rdev->family == CHIP_RV350) ||                 \
 794                 (rdev->family == CHIP_R350)  ||                 \
 795                 (rdev->family == CHIP_RV380) ||                 \
 796                 (rdev->family == CHIP_R420)  ||                 \
 797                 (rdev->family == CHIP_R423)  ||                 \
 798                 (rdev->family == CHIP_RV410) ||                 \
 799                 (rdev->family == CHIP_RS400) ||                 \
 800                 (rdev->family == CHIP_RS480))
 801 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
 802 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
 803 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
 804
 805
 806 /*
 807  * BIOS helpers.
 808  */
 809 #define RBIOS8(i) (rdev->bios[i])
 810 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
 811 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
 812
 813 int radeon_combios_init(struct radeon_device *rdev);
 814 void radeon_combios_fini(struct radeon_device *rdev);
 815 int radeon_atombios_init(struct radeon_device *rdev);
 816 void radeon_atombios_fini(struct radeon_device *rdev);
 817
 818
 819 /*
 820  * RING helpers.
 821  */
 822 #define CP_PACKET0                      0x00000000
 823 #define         PACKET0_BASE_INDEX_SHIFT        0
 824 #define         PACKET0_BASE_INDEX_MASK         (0x1ffff << 0)
 825 #define         PACKET0_COUNT_SHIFT             16
 826 #define         PACKET0_COUNT_MASK              (0x3fff << 16)
 827 #define CP_PACKET1                      0x40000000
 828 #define CP_PACKET2                      0x80000000
 829 #define         PACKET2_PAD_SHIFT               0
 830 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
 831 #define CP_PACKET3                      0xC0000000
 832 #define         PACKET3_IT_OPCODE_SHIFT         8
 833 #define         PACKET3_IT_OPCODE_MASK          (0xff << 8)
 834 #define         PACKET3_COUNT_SHIFT             16
 835 #define         PACKET3_COUNT_MASK              (0x3fff << 16)
 836 /* PACKET3 op code */
 837 #define         PACKET3_NOP                     0x10
 838 #define         PACKET3_3D_DRAW_VBUF            0x28
 839 #define         PACKET3_3D_DRAW_IMMD            0x29
 840 #define         PACKET3_3D_DRAW_INDX            0x2A
 841 #define         PACKET3_3D_LOAD_VBPNTR          0x2F
 842 #define         PACKET3_INDX_BUFFER             0x33
 843 #define         PACKET3_3D_DRAW_VBUF_2          0x34
 844 #define         PACKET3_3D_DRAW_IMMD_2          0x35
 845 #define         PACKET3_3D_DRAW_INDX_2          0x36
 846 #define         PACKET3_BITBLT_MULTI            0x9B
 847
 848 #define PACKET0(reg, n) (CP_PACKET0 |                                   \
 849                          REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |      \
 850                          REG_SET(PACKET0_COUNT, (n)))
 851 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
 852 #define PACKET3(op, n)  (CP_PACKET3 |                                   \
 853                          REG_SET(PACKET3_IT_OPCODE, (op)) |             \
 854                          REG_SET(PACKET3_COUNT, (n)))
 855
 856 #define PACKET_TYPE0    0
 857 #define PACKET_TYPE1    1
 858 #define PACKET_TYPE2    2
 859 #define PACKET_TYPE3    3
 860
 861 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
 862 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
 863 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
 864 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
 865 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
 866
 867 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 868 {
 869 #if DRM_DEBUG_CODE
 870         if (rdev->cp.count_dw <= 0) {
 871                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
 872         }
 873 #endif
 874         rdev->cp.ring[rdev->cp.wptr++] = v;
 875         rdev->cp.wptr &= rdev->cp.ptr_mask;
 876         rdev->cp.count_dw--;
 877         rdev->cp.ring_free_dw--;
 878 }
 879
 880
 881 /*
 882  * ASICs macro.
 883  */
 884 #define radeon_init(rdev) (rdev)->asic->init((rdev))
 885 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 886 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
 887 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
 888 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
 889 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
 890 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
 891 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
 892 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
 893 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
 894 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
 895 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 896 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
 897 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
 898 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
 899 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
 900 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
 901 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
 902 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
 903 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
 904 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
 905 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
 906 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
 907 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
 908 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 909 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 910 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
 911 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
 912 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
 913 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 914 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 915
 916 #endif