drivers/gpu/drm/radeon/rs400.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <drm/drmP.h>
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32 #include "radeon_share.h"
  33
  34 /* rs400,rs480 depends on : */
  35 void r100_hdp_reset(struct radeon_device *rdev);
  36 void r100_mc_disable_clients(struct radeon_device *rdev);
  37 int r300_mc_wait_for_idle(struct radeon_device *rdev);
  38 void r420_pipes_init(struct radeon_device *rdev);
  39
  40 /* This files gather functions specifics to :
  41  * rs400,rs480
  42  *
  43  * Some of these functions might be used by newer ASICs.
  44  */
  45 void rs400_gpu_init(struct radeon_device *rdev);
  46 int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  47
  48
  49 /*
  50  * GART functions.
  51  */
  52 void rs400_gart_adjust_size(struct radeon_device *rdev)
  53 {
  54         /* Check gart size */
  55         switch (rdev->mc.gtt_size/(1024*1024)) {
  56         case 32:
  57         case 64:
  58         case 128:
  59         case 256:
  60         case 512:
  61         case 1024:
  62         case 2048:
  63                 break;
  64         default:
  65                 DRM_ERROR("Unable to use IGP GART size %uM\n",
  66                           rdev->mc.gtt_size >> 20);
  67                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
  68                 DRM_ERROR("Forcing to 32M GART size\n");
  69                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  70                 return;
  71         }
  72         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  73                 /* FIXME: RS400 & RS480 seems to have issue with GART size
  74                  * if 4G of system memory (needs more testing) */
  75                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  76                 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
  77         }
  78 }
  79
  80 void rs400_gart_tlb_flush(struct radeon_device *rdev)
  81 {
  82         uint32_t tmp;
  83         unsigned int timeout = rdev->usec_timeout;
  84
  85         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
  86         do {
  87                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  88                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
  89                         break;
  90                 DRM_UDELAY(1);
  91                 timeout--;
  92         } while (timeout > 0);
  93         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
  94 }
  95
  96 int rs400_gart_enable(struct radeon_device *rdev)
  97 {
  98         uint32_t size_reg;
  99         uint32_t tmp;
 100         int r;
 101
 102         /* Initialize common gart structure */
 103         r = radeon_gart_init(rdev);
 104         if (r) {
 105                 return r;
 106         }
 107         if (rs400_debugfs_pcie_gart_info_init(rdev)) {
 108                 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
 109         }
 110
 111         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 112         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 113         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 114         /* Check gart size */
 115         switch(rdev->mc.gtt_size / (1024 * 1024)) {
 116         case 32:
 117                 size_reg = RS480_VA_SIZE_32MB;
 118                 break;
 119         case 64:
 120                 size_reg = RS480_VA_SIZE_64MB;
 121                 break;
 122         case 128:
 123                 size_reg = RS480_VA_SIZE_128MB;
 124                 break;
 125         case 256:
 126                 size_reg = RS480_VA_SIZE_256MB;
 127                 break;
 128         case 512:
 129                 size_reg = RS480_VA_SIZE_512MB;
 130                 break;
 131         case 1024:
 132                 size_reg = RS480_VA_SIZE_1GB;
 133                 break;
 134         case 2048:
 135                 size_reg = RS480_VA_SIZE_2GB;
 136                 break;
 137         default:
 138                 return -EINVAL;
 139         }
 140         if (rdev->gart.table.ram.ptr == NULL) {
 141                 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 142                 r = radeon_gart_table_ram_alloc(rdev);
 143                 if (r) {
 144                         return r;
 145                 }
 146         }
 147         /* It should be fine to program it to max value */
 148         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 149                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
 150                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
 151         } else {
 152                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
 153                 WREG32(RS480_AGP_BASE_2, 0);
 154         }
 155         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 156         tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16);
 157         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
 158         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 159                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
 160                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 161                 WREG32(RADEON_BUS_CNTL, tmp);
 162         } else {
 163                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
 164                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 165                 WREG32(RADEON_BUS_CNTL, tmp);
 166         }
 167         /* Table should be in 32bits address space so ignore bits above. */
 168         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
 169         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
 170
 171         WREG32_MC(RS480_GART_BASE, tmp);
 172         /* TODO: more tweaking here */
 173         WREG32_MC(RS480_GART_FEATURE_ID,
 174                   (RS480_TLB_ENABLE |
 175                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
 176         /* Disable snooping */
 177         WREG32_MC(RS480_AGP_MODE_CNTL,
 178                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
 179         /* Disable AGP mode */
 180         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
 181          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
 182         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 183                 WREG32_MC(RS480_MC_MISC_CNTL,
 184                           (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
 185         } else {
 186                 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 187         }
 188         /* Enable gart */
 189         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
 190         rs400_gart_tlb_flush(rdev);
 191         rdev->gart.ready = true;
 192         return 0;
 193 }
 194
 195 void rs400_gart_disable(struct radeon_device *rdev)
 196 {
 197         uint32_t tmp;
 198
 199         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 200         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 201         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 202         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 203 }
 204
 205 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 206 {
 207         uint32_t entry;
 208
 209         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 210                 return -EINVAL;
 211         }
 212
 213         entry = (lower_32_bits(addr) & PAGE_MASK) |
 214                 ((upper_32_bits(addr) & 0xff) << 4) |
 215                 0xc;
 216         entry = cpu_to_le32(entry);
 217         rdev->gart.table.ram.ptr[i] = entry;
 218         return 0;
 219 }
 220
 221
 222 /*
 223  * MC functions.
 224  */
 225 int rs400_mc_init(struct radeon_device *rdev)
 226 {
 227         uint32_t tmp;
 228         int r;
 229
 230         if (r100_debugfs_rbbm_init(rdev)) {
 231                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 232         }
 233
 234         rs400_gpu_init(rdev);
 235         rs400_gart_disable(rdev);
 236         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 237         rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
 238         rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
 239         r = radeon_mc_setup(rdev);
 240         if (r) {
 241                 return r;
 242         }
 243
 244         r100_mc_disable_clients(rdev);
 245         if (r300_mc_wait_for_idle(rdev)) {
 246                 printk(KERN_WARNING "Failed to wait MC idle while "
 247                        "programming pipes. Bad things might happen.\n");
 248         }
 249
 250         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 251         tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
 252         tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
 253         WREG32(RADEON_MC_FB_LOCATION, tmp);
 254         tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS;
 255         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
 256         (void)RREG32(RADEON_HOST_PATH_CNTL);
 257         WREG32(RADEON_HOST_PATH_CNTL, tmp);
 258         (void)RREG32(RADEON_HOST_PATH_CNTL);
 259         return 0;
 260 }
 261
 262 void rs400_mc_fini(struct radeon_device *rdev)
 263 {
 264         rs400_gart_disable(rdev);
 265         radeon_gart_table_ram_free(rdev);
 266         radeon_gart_fini(rdev);
 267 }
 268
 269
 270 /*
 271  * Global GPU functions
 272  */
 273 void rs400_errata(struct radeon_device *rdev)
 274 {
 275         rdev->pll_errata = 0;
 276 }
 277
 278 void rs400_gpu_init(struct radeon_device *rdev)
 279 {
 280         /* FIXME: HDP same place on rs400 ? */
 281         r100_hdp_reset(rdev);
 282         /* FIXME: is this correct ? */
 283         r420_pipes_init(rdev);
 284         if (r300_mc_wait_for_idle(rdev)) {
 285                 printk(KERN_WARNING "Failed to wait MC idle while "
 286                        "programming pipes. Bad things might happen.\n");
 287         }
 288 }
 289
 290
 291 /*
 292  * VRAM info.
 293  */
 294 void rs400_vram_info(struct radeon_device *rdev)
 295 {
 296         rs400_gart_adjust_size(rdev);
 297         /* DDR for all card after R300 & IGP */
 298         rdev->mc.vram_is_ddr = true;
 299         rdev->mc.vram_width = 128;
 300
 301         r100_vram_init_sizes(rdev);
 302 }
 303
 304
 305 /*
 306  * Indirect registers accessor
 307  */
 308 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 309 {
 310         uint32_t r;
 311
 312         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
 313         r = RREG32(RS480_NB_MC_DATA);
 314         WREG32(RS480_NB_MC_INDEX, 0xff);
 315         return r;
 316 }
 317
 318 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 319 {
 320         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
 321         WREG32(RS480_NB_MC_DATA, (v));
 322         WREG32(RS480_NB_MC_INDEX, 0xff);
 323 }
 324
 325
 326 /*
 327  * Debugfs info
 328  */
 329 #if defined(CONFIG_DEBUG_FS)
 330 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
 331 {
 332         struct drm_info_node *node = (struct drm_info_node *) m->private;
 333         struct drm_device *dev = node->minor->dev;
 334         struct radeon_device *rdev = dev->dev_private;
 335         uint32_t tmp;
 336
 337         tmp = RREG32(RADEON_HOST_PATH_CNTL);
 338         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
 339         tmp = RREG32(RADEON_BUS_CNTL);
 340         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
 341         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 342         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
 343         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 344                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
 345                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
 346                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
 347                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
 348                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
 349                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
 350                 tmp = RREG32_MC(0x100);
 351                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
 352                 tmp = RREG32(0x134);
 353                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
 354         } else {
 355                 tmp = RREG32(RADEON_AGP_BASE);
 356                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
 357                 tmp = RREG32(RS480_AGP_BASE_2);
 358                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
 359                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
 360                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
 361         }
 362         tmp = RREG32_MC(RS480_GART_BASE);
 363         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
 364         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
 365         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
 366         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
 367         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
 368         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
 369         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
 370         tmp = RREG32_MC(0x5F);
 371         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
 372         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
 373         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
 374         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
 375         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
 376         tmp = RREG32_MC(0x3B);
 377         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
 378         tmp = RREG32_MC(0x3C);
 379         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
 380         tmp = RREG32_MC(0x30);
 381         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
 382         tmp = RREG32_MC(0x31);
 383         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
 384         tmp = RREG32_MC(0x32);
 385         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
 386         tmp = RREG32_MC(0x33);
 387         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
 388         tmp = RREG32_MC(0x34);
 389         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
 390         tmp = RREG32_MC(0x35);
 391         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
 392         tmp = RREG32_MC(0x36);
 393         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
 394         tmp = RREG32_MC(0x37);
 395         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
 396         return 0;
 397 }
 398
 399 static struct drm_info_list rs400_gart_info_list[] = {
 400         {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
 401 };
 402 #endif
 403
 404 int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 405 {
 406 #if defined(CONFIG_DEBUG_FS)
 407         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
 408 #else
 409         return 0;
 410 #endif
 411 }