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[linux/fpc-iii.git] / drivers / net / igb / igb_ethtool.c
blobd004c359244c9b03e2e5e753f5300abc15be8bc1
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37
38 #include "igb.h"
39
40 struct igb_stats {
41 char stat_string[ETH_GSTRING_LEN];
42 int sizeof_stat;
43 int stat_offset;
44 };
45
46 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
47 offsetof(struct igb_adapter, m)
48 static const struct igb_stats igb_gstrings_stats[] = {
49 { "rx_packets", IGB_STAT(stats.gprc) },
50 { "tx_packets", IGB_STAT(stats.gptc) },
51 { "rx_bytes", IGB_STAT(stats.gorc) },
52 { "tx_bytes", IGB_STAT(stats.gotc) },
53 { "rx_broadcast", IGB_STAT(stats.bprc) },
54 { "tx_broadcast", IGB_STAT(stats.bptc) },
55 { "rx_multicast", IGB_STAT(stats.mprc) },
56 { "tx_multicast", IGB_STAT(stats.mptc) },
57 { "rx_errors", IGB_STAT(net_stats.rx_errors) },
58 { "tx_errors", IGB_STAT(net_stats.tx_errors) },
59 { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
60 { "multicast", IGB_STAT(stats.mprc) },
61 { "collisions", IGB_STAT(stats.colc) },
62 { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
63 { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
64 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
65 { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
66 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
67 { "rx_queue_drop_packet_count", IGB_STAT(net_stats.rx_fifo_errors) },
68 { "rx_missed_errors", IGB_STAT(stats.mpc) },
69 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
70 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
71 { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
72 { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
73 { "tx_window_errors", IGB_STAT(stats.latecol) },
74 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
75 { "tx_deferred_ok", IGB_STAT(stats.dc) },
76 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
77 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
78 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
79 { "tx_restart_queue", IGB_STAT(restart_queue) },
80 { "rx_long_length_errors", IGB_STAT(stats.roc) },
81 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
82 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
83 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
84 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
85 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
86 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
87 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
88 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
89 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
90 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
91 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
92 { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
93 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
94 { "tx_smbus", IGB_STAT(stats.mgptc) },
95 { "rx_smbus", IGB_STAT(stats.mgprc) },
96 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
97 };
98
99 #define IGB_QUEUE_STATS_LEN \
100 (((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues)* \
101 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))) + \
102 ((((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
103 (sizeof(struct igb_tx_queue_stats) / sizeof(u64))))
104 #define IGB_GLOBAL_STATS_LEN \
105 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
106 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
107 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
108 "Register test (offline)", "Eeprom test (offline)",
109 "Interrupt test (offline)", "Loopback test (offline)",
110 "Link test (on/offline)"
111 };
112 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
113
114 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
115 {
116 struct igb_adapter *adapter = netdev_priv(netdev);
117 struct e1000_hw *hw = &adapter->hw;
118
119 if (hw->phy.media_type == e1000_media_type_copper) {
120
121 ecmd->supported = (SUPPORTED_10baseT_Half |
122 SUPPORTED_10baseT_Full |
123 SUPPORTED_100baseT_Half |
124 SUPPORTED_100baseT_Full |
125 SUPPORTED_1000baseT_Full|
126 SUPPORTED_Autoneg |
127 SUPPORTED_TP);
128 ecmd->advertising = ADVERTISED_TP;
129
130 if (hw->mac.autoneg == 1) {
131 ecmd->advertising |= ADVERTISED_Autoneg;
132 /* the e1000 autoneg seems to match ethtool nicely */
133 ecmd->advertising |= hw->phy.autoneg_advertised;
134 }
135
136 ecmd->port = PORT_TP;
137 ecmd->phy_address = hw->phy.addr;
138 } else {
139 ecmd->supported = (SUPPORTED_1000baseT_Full |
140 SUPPORTED_FIBRE |
141 SUPPORTED_Autoneg);
142
143 ecmd->advertising = (ADVERTISED_1000baseT_Full |
144 ADVERTISED_FIBRE |
145 ADVERTISED_Autoneg);
146
147 ecmd->port = PORT_FIBRE;
148 }
149
150 ecmd->transceiver = XCVR_INTERNAL;
151
152 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
153
154 adapter->hw.mac.ops.get_speed_and_duplex(hw,
155 &adapter->link_speed,
156 &adapter->link_duplex);
157 ecmd->speed = adapter->link_speed;
158
159 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
160 * and HALF_DUPLEX != DUPLEX_HALF */
161
162 if (adapter->link_duplex == FULL_DUPLEX)
163 ecmd->duplex = DUPLEX_FULL;
164 else
165 ecmd->duplex = DUPLEX_HALF;
166 } else {
167 ecmd->speed = -1;
168 ecmd->duplex = -1;
169 }
170
171 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
172 return 0;
173 }
174
175 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
176 {
177 struct igb_adapter *adapter = netdev_priv(netdev);
178 struct e1000_hw *hw = &adapter->hw;
179
180 /* When SoL/IDER sessions are active, autoneg/speed/duplex
181 * cannot be changed */
182 if (igb_check_reset_block(hw)) {
183 dev_err(&adapter->pdev->dev, "Cannot change link "
184 "characteristics when SoL/IDER is active.\n");
185 return -EINVAL;
186 }
187
188 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
189 msleep(1);
190
191 if (ecmd->autoneg == AUTONEG_ENABLE) {
192 hw->mac.autoneg = 1;
193 hw->phy.autoneg_advertised = ecmd->advertising |
194 ADVERTISED_TP |
195 ADVERTISED_Autoneg;
196 ecmd->advertising = hw->phy.autoneg_advertised;
197 if (adapter->fc_autoneg)
198 hw->fc.requested_mode = e1000_fc_default;
199 } else {
200 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
201 clear_bit(__IGB_RESETTING, &adapter->state);
202 return -EINVAL;
203 }
204 }
205
206 /* reset the link */
207 if (netif_running(adapter->netdev)) {
208 igb_down(adapter);
209 igb_up(adapter);
210 } else
211 igb_reset(adapter);
212
213 clear_bit(__IGB_RESETTING, &adapter->state);
214 return 0;
215 }
216
217 static void igb_get_pauseparam(struct net_device *netdev,
218 struct ethtool_pauseparam *pause)
219 {
220 struct igb_adapter *adapter = netdev_priv(netdev);
221 struct e1000_hw *hw = &adapter->hw;
222
223 pause->autoneg =
224 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
225
226 if (hw->fc.current_mode == e1000_fc_rx_pause)
227 pause->rx_pause = 1;
228 else if (hw->fc.current_mode == e1000_fc_tx_pause)
229 pause->tx_pause = 1;
230 else if (hw->fc.current_mode == e1000_fc_full) {
231 pause->rx_pause = 1;
232 pause->tx_pause = 1;
233 }
234 }
235
236 static int igb_set_pauseparam(struct net_device *netdev,
237 struct ethtool_pauseparam *pause)
238 {
239 struct igb_adapter *adapter = netdev_priv(netdev);
240 struct e1000_hw *hw = &adapter->hw;
241 int retval = 0;
242
243 adapter->fc_autoneg = pause->autoneg;
244
245 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
246 msleep(1);
247
248 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
249 hw->fc.requested_mode = e1000_fc_default;
250 if (netif_running(adapter->netdev)) {
251 igb_down(adapter);
252 igb_up(adapter);
253 } else
254 igb_reset(adapter);
255 } else {
256 if (pause->rx_pause && pause->tx_pause)
257 hw->fc.requested_mode = e1000_fc_full;
258 else if (pause->rx_pause && !pause->tx_pause)
259 hw->fc.requested_mode = e1000_fc_rx_pause;
260 else if (!pause->rx_pause && pause->tx_pause)
261 hw->fc.requested_mode = e1000_fc_tx_pause;
262 else if (!pause->rx_pause && !pause->tx_pause)
263 hw->fc.requested_mode = e1000_fc_none;
264
265 hw->fc.current_mode = hw->fc.requested_mode;
266
267 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
268 igb_force_mac_fc(hw) : igb_setup_link(hw));
269 }
270
271 clear_bit(__IGB_RESETTING, &adapter->state);
272 return retval;
273 }
274
275 static u32 igb_get_rx_csum(struct net_device *netdev)
276 {
277 struct igb_adapter *adapter = netdev_priv(netdev);
278 return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED);
279 }
280
281 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
282 {
283 struct igb_adapter *adapter = netdev_priv(netdev);
284
285 if (data)
286 adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED;
287 else
288 adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED;
289
290 return 0;
291 }
292
293 static u32 igb_get_tx_csum(struct net_device *netdev)
294 {
295 return (netdev->features & NETIF_F_IP_CSUM) != 0;
296 }
297
298 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
299 {
300 struct igb_adapter *adapter = netdev_priv(netdev);
301
302 if (data) {
303 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
304 if (adapter->hw.mac.type == e1000_82576)
305 netdev->features |= NETIF_F_SCTP_CSUM;
306 } else {
307 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
308 NETIF_F_SCTP_CSUM);
309 }
310
311 return 0;
312 }
313
314 static int igb_set_tso(struct net_device *netdev, u32 data)
315 {
316 struct igb_adapter *adapter = netdev_priv(netdev);
317
318 if (data) {
319 netdev->features |= NETIF_F_TSO;
320 netdev->features |= NETIF_F_TSO6;
321 } else {
322 netdev->features &= ~NETIF_F_TSO;
323 netdev->features &= ~NETIF_F_TSO6;
324 }
325
326 dev_info(&adapter->pdev->dev, "TSO is %s\n",
327 data ? "Enabled" : "Disabled");
328 return 0;
329 }
330
331 static u32 igb_get_msglevel(struct net_device *netdev)
332 {
333 struct igb_adapter *adapter = netdev_priv(netdev);
334 return adapter->msg_enable;
335 }
336
337 static void igb_set_msglevel(struct net_device *netdev, u32 data)
338 {
339 struct igb_adapter *adapter = netdev_priv(netdev);
340 adapter->msg_enable = data;
341 }
342
343 static int igb_get_regs_len(struct net_device *netdev)
344 {
345 #define IGB_REGS_LEN 551
346 return IGB_REGS_LEN * sizeof(u32);
347 }
348
349 static void igb_get_regs(struct net_device *netdev,
350 struct ethtool_regs *regs, void *p)
351 {
352 struct igb_adapter *adapter = netdev_priv(netdev);
353 struct e1000_hw *hw = &adapter->hw;
354 u32 *regs_buff = p;
355 u8 i;
356
357 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
358
359 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
360
361 /* General Registers */
362 regs_buff[0] = rd32(E1000_CTRL);
363 regs_buff[1] = rd32(E1000_STATUS);
364 regs_buff[2] = rd32(E1000_CTRL_EXT);
365 regs_buff[3] = rd32(E1000_MDIC);
366 regs_buff[4] = rd32(E1000_SCTL);
367 regs_buff[5] = rd32(E1000_CONNSW);
368 regs_buff[6] = rd32(E1000_VET);
369 regs_buff[7] = rd32(E1000_LEDCTL);
370 regs_buff[8] = rd32(E1000_PBA);
371 regs_buff[9] = rd32(E1000_PBS);
372 regs_buff[10] = rd32(E1000_FRTIMER);
373 regs_buff[11] = rd32(E1000_TCPTIMER);
374
375 /* NVM Register */
376 regs_buff[12] = rd32(E1000_EECD);
377
378 /* Interrupt */
379 /* Reading EICS for EICR because they read the
380 * same but EICS does not clear on read */
381 regs_buff[13] = rd32(E1000_EICS);
382 regs_buff[14] = rd32(E1000_EICS);
383 regs_buff[15] = rd32(E1000_EIMS);
384 regs_buff[16] = rd32(E1000_EIMC);
385 regs_buff[17] = rd32(E1000_EIAC);
386 regs_buff[18] = rd32(E1000_EIAM);
387 /* Reading ICS for ICR because they read the
388 * same but ICS does not clear on read */
389 regs_buff[19] = rd32(E1000_ICS);
390 regs_buff[20] = rd32(E1000_ICS);
391 regs_buff[21] = rd32(E1000_IMS);
392 regs_buff[22] = rd32(E1000_IMC);
393 regs_buff[23] = rd32(E1000_IAC);
394 regs_buff[24] = rd32(E1000_IAM);
395 regs_buff[25] = rd32(E1000_IMIRVP);
396
397 /* Flow Control */
398 regs_buff[26] = rd32(E1000_FCAL);
399 regs_buff[27] = rd32(E1000_FCAH);
400 regs_buff[28] = rd32(E1000_FCTTV);
401 regs_buff[29] = rd32(E1000_FCRTL);
402 regs_buff[30] = rd32(E1000_FCRTH);
403 regs_buff[31] = rd32(E1000_FCRTV);
404
405 /* Receive */
406 regs_buff[32] = rd32(E1000_RCTL);
407 regs_buff[33] = rd32(E1000_RXCSUM);
408 regs_buff[34] = rd32(E1000_RLPML);
409 regs_buff[35] = rd32(E1000_RFCTL);
410 regs_buff[36] = rd32(E1000_MRQC);
411 regs_buff[37] = rd32(E1000_VT_CTL);
412
413 /* Transmit */
414 regs_buff[38] = rd32(E1000_TCTL);
415 regs_buff[39] = rd32(E1000_TCTL_EXT);
416 regs_buff[40] = rd32(E1000_TIPG);
417 regs_buff[41] = rd32(E1000_DTXCTL);
418
419 /* Wake Up */
420 regs_buff[42] = rd32(E1000_WUC);
421 regs_buff[43] = rd32(E1000_WUFC);
422 regs_buff[44] = rd32(E1000_WUS);
423 regs_buff[45] = rd32(E1000_IPAV);
424 regs_buff[46] = rd32(E1000_WUPL);
425
426 /* MAC */
427 regs_buff[47] = rd32(E1000_PCS_CFG0);
428 regs_buff[48] = rd32(E1000_PCS_LCTL);
429 regs_buff[49] = rd32(E1000_PCS_LSTAT);
430 regs_buff[50] = rd32(E1000_PCS_ANADV);
431 regs_buff[51] = rd32(E1000_PCS_LPAB);
432 regs_buff[52] = rd32(E1000_PCS_NPTX);
433 regs_buff[53] = rd32(E1000_PCS_LPABNP);
434
435 /* Statistics */
436 regs_buff[54] = adapter->stats.crcerrs;
437 regs_buff[55] = adapter->stats.algnerrc;
438 regs_buff[56] = adapter->stats.symerrs;
439 regs_buff[57] = adapter->stats.rxerrc;
440 regs_buff[58] = adapter->stats.mpc;
441 regs_buff[59] = adapter->stats.scc;
442 regs_buff[60] = adapter->stats.ecol;
443 regs_buff[61] = adapter->stats.mcc;
444 regs_buff[62] = adapter->stats.latecol;
445 regs_buff[63] = adapter->stats.colc;
446 regs_buff[64] = adapter->stats.dc;
447 regs_buff[65] = adapter->stats.tncrs;
448 regs_buff[66] = adapter->stats.sec;
449 regs_buff[67] = adapter->stats.htdpmc;
450 regs_buff[68] = adapter->stats.rlec;
451 regs_buff[69] = adapter->stats.xonrxc;
452 regs_buff[70] = adapter->stats.xontxc;
453 regs_buff[71] = adapter->stats.xoffrxc;
454 regs_buff[72] = adapter->stats.xofftxc;
455 regs_buff[73] = adapter->stats.fcruc;
456 regs_buff[74] = adapter->stats.prc64;
457 regs_buff[75] = adapter->stats.prc127;
458 regs_buff[76] = adapter->stats.prc255;
459 regs_buff[77] = adapter->stats.prc511;
460 regs_buff[78] = adapter->stats.prc1023;
461 regs_buff[79] = adapter->stats.prc1522;
462 regs_buff[80] = adapter->stats.gprc;
463 regs_buff[81] = adapter->stats.bprc;
464 regs_buff[82] = adapter->stats.mprc;
465 regs_buff[83] = adapter->stats.gptc;
466 regs_buff[84] = adapter->stats.gorc;
467 regs_buff[86] = adapter->stats.gotc;
468 regs_buff[88] = adapter->stats.rnbc;
469 regs_buff[89] = adapter->stats.ruc;
470 regs_buff[90] = adapter->stats.rfc;
471 regs_buff[91] = adapter->stats.roc;
472 regs_buff[92] = adapter->stats.rjc;
473 regs_buff[93] = adapter->stats.mgprc;
474 regs_buff[94] = adapter->stats.mgpdc;
475 regs_buff[95] = adapter->stats.mgptc;
476 regs_buff[96] = adapter->stats.tor;
477 regs_buff[98] = adapter->stats.tot;
478 regs_buff[100] = adapter->stats.tpr;
479 regs_buff[101] = adapter->stats.tpt;
480 regs_buff[102] = adapter->stats.ptc64;
481 regs_buff[103] = adapter->stats.ptc127;
482 regs_buff[104] = adapter->stats.ptc255;
483 regs_buff[105] = adapter->stats.ptc511;
484 regs_buff[106] = adapter->stats.ptc1023;
485 regs_buff[107] = adapter->stats.ptc1522;
486 regs_buff[108] = adapter->stats.mptc;
487 regs_buff[109] = adapter->stats.bptc;
488 regs_buff[110] = adapter->stats.tsctc;
489 regs_buff[111] = adapter->stats.iac;
490 regs_buff[112] = adapter->stats.rpthc;
491 regs_buff[113] = adapter->stats.hgptc;
492 regs_buff[114] = adapter->stats.hgorc;
493 regs_buff[116] = adapter->stats.hgotc;
494 regs_buff[118] = adapter->stats.lenerrs;
495 regs_buff[119] = adapter->stats.scvpc;
496 regs_buff[120] = adapter->stats.hrmpc;
497
498 /* These should probably be added to e1000_regs.h instead */
499 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
500 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
501 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
502 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
503 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
504 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
505 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
506
507 for (i = 0; i < 4; i++)
508 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
509 for (i = 0; i < 4; i++)
510 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
511 for (i = 0; i < 4; i++)
512 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
513 for (i = 0; i < 4; i++)
514 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
515 for (i = 0; i < 4; i++)
516 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
517 for (i = 0; i < 4; i++)
518 regs_buff[141 + i] = rd32(E1000_RDH(i));
519 for (i = 0; i < 4; i++)
520 regs_buff[145 + i] = rd32(E1000_RDT(i));
521 for (i = 0; i < 4; i++)
522 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
523
524 for (i = 0; i < 10; i++)
525 regs_buff[153 + i] = rd32(E1000_EITR(i));
526 for (i = 0; i < 8; i++)
527 regs_buff[163 + i] = rd32(E1000_IMIR(i));
528 for (i = 0; i < 8; i++)
529 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
530 for (i = 0; i < 16; i++)
531 regs_buff[179 + i] = rd32(E1000_RAL(i));
532 for (i = 0; i < 16; i++)
533 regs_buff[195 + i] = rd32(E1000_RAH(i));
534
535 for (i = 0; i < 4; i++)
536 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
537 for (i = 0; i < 4; i++)
538 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
539 for (i = 0; i < 4; i++)
540 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
541 for (i = 0; i < 4; i++)
542 regs_buff[223 + i] = rd32(E1000_TDH(i));
543 for (i = 0; i < 4; i++)
544 regs_buff[227 + i] = rd32(E1000_TDT(i));
545 for (i = 0; i < 4; i++)
546 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
547 for (i = 0; i < 4; i++)
548 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
549 for (i = 0; i < 4; i++)
550 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
551 for (i = 0; i < 4; i++)
552 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
553
554 for (i = 0; i < 4; i++)
555 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
556 for (i = 0; i < 4; i++)
557 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
558 for (i = 0; i < 32; i++)
559 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
560 for (i = 0; i < 128; i++)
561 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
562 for (i = 0; i < 128; i++)
563 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
564 for (i = 0; i < 4; i++)
565 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
566
567 regs_buff[547] = rd32(E1000_TDFH);
568 regs_buff[548] = rd32(E1000_TDFT);
569 regs_buff[549] = rd32(E1000_TDFHS);
570 regs_buff[550] = rd32(E1000_TDFPC);
571
572 }
573
574 static int igb_get_eeprom_len(struct net_device *netdev)
575 {
576 struct igb_adapter *adapter = netdev_priv(netdev);
577 return adapter->hw.nvm.word_size * 2;
578 }
579
580 static int igb_get_eeprom(struct net_device *netdev,
581 struct ethtool_eeprom *eeprom, u8 *bytes)
582 {
583 struct igb_adapter *adapter = netdev_priv(netdev);
584 struct e1000_hw *hw = &adapter->hw;
585 u16 *eeprom_buff;
586 int first_word, last_word;
587 int ret_val = 0;
588 u16 i;
589
590 if (eeprom->len == 0)
591 return -EINVAL;
592
593 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
594
595 first_word = eeprom->offset >> 1;
596 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
597
598 eeprom_buff = kmalloc(sizeof(u16) *
599 (last_word - first_word + 1), GFP_KERNEL);
600 if (!eeprom_buff)
601 return -ENOMEM;
602
603 if (hw->nvm.type == e1000_nvm_eeprom_spi)
604 ret_val = hw->nvm.ops.read(hw, first_word,
605 last_word - first_word + 1,
606 eeprom_buff);
607 else {
608 for (i = 0; i < last_word - first_word + 1; i++) {
609 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
610 &eeprom_buff[i]);
611 if (ret_val)
612 break;
613 }
614 }
615
616 /* Device's eeprom is always little-endian, word addressable */
617 for (i = 0; i < last_word - first_word + 1; i++)
618 le16_to_cpus(&eeprom_buff[i]);
619
620 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
621 eeprom->len);
622 kfree(eeprom_buff);
623
624 return ret_val;
625 }
626
627 static int igb_set_eeprom(struct net_device *netdev,
628 struct ethtool_eeprom *eeprom, u8 *bytes)
629 {
630 struct igb_adapter *adapter = netdev_priv(netdev);
631 struct e1000_hw *hw = &adapter->hw;
632 u16 *eeprom_buff;
633 void *ptr;
634 int max_len, first_word, last_word, ret_val = 0;
635 u16 i;
636
637 if (eeprom->len == 0)
638 return -EOPNOTSUPP;
639
640 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
641 return -EFAULT;
642
643 max_len = hw->nvm.word_size * 2;
644
645 first_word = eeprom->offset >> 1;
646 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
647 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
648 if (!eeprom_buff)
649 return -ENOMEM;
650
651 ptr = (void *)eeprom_buff;
652
653 if (eeprom->offset & 1) {
654 /* need read/modify/write of first changed EEPROM word */
655 /* only the second byte of the word is being modified */
656 ret_val = hw->nvm.ops.read(hw, first_word, 1,
657 &eeprom_buff[0]);
658 ptr++;
659 }
660 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
661 /* need read/modify/write of last changed EEPROM word */
662 /* only the first byte of the word is being modified */
663 ret_val = hw->nvm.ops.read(hw, last_word, 1,
664 &eeprom_buff[last_word - first_word]);
665 }
666
667 /* Device's eeprom is always little-endian, word addressable */
668 for (i = 0; i < last_word - first_word + 1; i++)
669 le16_to_cpus(&eeprom_buff[i]);
670
671 memcpy(ptr, bytes, eeprom->len);
672
673 for (i = 0; i < last_word - first_word + 1; i++)
674 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
675
676 ret_val = hw->nvm.ops.write(hw, first_word,
677 last_word - first_word + 1, eeprom_buff);
678
679 /* Update the checksum over the first part of the EEPROM if needed
680 * and flush shadow RAM for 82573 controllers */
681 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
682 igb_update_nvm_checksum(hw);
683
684 kfree(eeprom_buff);
685 return ret_val;
686 }
687
688 static void igb_get_drvinfo(struct net_device *netdev,
689 struct ethtool_drvinfo *drvinfo)
690 {
691 struct igb_adapter *adapter = netdev_priv(netdev);
692 char firmware_version[32];
693 u16 eeprom_data;
694
695 strncpy(drvinfo->driver, igb_driver_name, 32);
696 strncpy(drvinfo->version, igb_driver_version, 32);
697
698 /* EEPROM image version # is reported as firmware version # for
699 * 82575 controllers */
700 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
701 sprintf(firmware_version, "%d.%d-%d",
702 (eeprom_data & 0xF000) >> 12,
703 (eeprom_data & 0x0FF0) >> 4,
704 eeprom_data & 0x000F);
705
706 strncpy(drvinfo->fw_version, firmware_version, 32);
707 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
708 drvinfo->n_stats = IGB_STATS_LEN;
709 drvinfo->testinfo_len = IGB_TEST_LEN;
710 drvinfo->regdump_len = igb_get_regs_len(netdev);
711 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
712 }
713
714 static void igb_get_ringparam(struct net_device *netdev,
715 struct ethtool_ringparam *ring)
716 {
717 struct igb_adapter *adapter = netdev_priv(netdev);
718
719 ring->rx_max_pending = IGB_MAX_RXD;
720 ring->tx_max_pending = IGB_MAX_TXD;
721 ring->rx_mini_max_pending = 0;
722 ring->rx_jumbo_max_pending = 0;
723 ring->rx_pending = adapter->rx_ring_count;
724 ring->tx_pending = adapter->tx_ring_count;
725 ring->rx_mini_pending = 0;
726 ring->rx_jumbo_pending = 0;
727 }
728
729 static int igb_set_ringparam(struct net_device *netdev,
730 struct ethtool_ringparam *ring)
731 {
732 struct igb_adapter *adapter = netdev_priv(netdev);
733 struct igb_ring *temp_ring;
734 int i, err;
735 u32 new_rx_count, new_tx_count;
736
737 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
738 return -EINVAL;
739
740 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
741 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
742 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
743
744 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
745 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
746 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
747
748 if ((new_tx_count == adapter->tx_ring_count) &&
749 (new_rx_count == adapter->rx_ring_count)) {
750 /* nothing to do */
751 return 0;
752 }
753
754 if (adapter->num_tx_queues > adapter->num_rx_queues)
755 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
756 else
757 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
758 if (!temp_ring)
759 return -ENOMEM;
760
761 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
762 msleep(1);
763
764 if (netif_running(adapter->netdev))
765 igb_down(adapter);
766
767 /*
768 * We can't just free everything and then setup again,
769 * because the ISRs in MSI-X mode get passed pointers
770 * to the tx and rx ring structs.
771 */
772 if (new_tx_count != adapter->tx_ring_count) {
773 memcpy(temp_ring, adapter->tx_ring,
774 adapter->num_tx_queues * sizeof(struct igb_ring));
775
776 for (i = 0; i < adapter->num_tx_queues; i++) {
777 temp_ring[i].count = new_tx_count;
778 err = igb_setup_tx_resources(adapter, &temp_ring[i]);
779 if (err) {
780 while (i) {
781 i--;
782 igb_free_tx_resources(&temp_ring[i]);
783 }
784 goto err_setup;
785 }
786 }
787
788 for (i = 0; i < adapter->num_tx_queues; i++)
789 igb_free_tx_resources(&adapter->tx_ring[i]);
790
791 memcpy(adapter->tx_ring, temp_ring,
792 adapter->num_tx_queues * sizeof(struct igb_ring));
793
794 adapter->tx_ring_count = new_tx_count;
795 }
796
797 if (new_rx_count != adapter->rx_ring->count) {
798 memcpy(temp_ring, adapter->rx_ring,
799 adapter->num_rx_queues * sizeof(struct igb_ring));
800
801 for (i = 0; i < adapter->num_rx_queues; i++) {
802 temp_ring[i].count = new_rx_count;
803 err = igb_setup_rx_resources(adapter, &temp_ring[i]);
804 if (err) {
805 while (i) {
806 i--;
807 igb_free_rx_resources(&temp_ring[i]);
808 }
809 goto err_setup;
810 }
811
812 }
813
814 for (i = 0; i < adapter->num_rx_queues; i++)
815 igb_free_rx_resources(&adapter->rx_ring[i]);
816
817 memcpy(adapter->rx_ring, temp_ring,
818 adapter->num_rx_queues * sizeof(struct igb_ring));
819
820 adapter->rx_ring_count = new_rx_count;
821 }
822
823 err = 0;
824 err_setup:
825 if (netif_running(adapter->netdev))
826 igb_up(adapter);
827
828 clear_bit(__IGB_RESETTING, &adapter->state);
829 vfree(temp_ring);
830 return err;
831 }
832
833 /* ethtool register test data */
834 struct igb_reg_test {
835 u16 reg;
836 u16 reg_offset;
837 u16 array_len;
838 u16 test_type;
839 u32 mask;
840 u32 write;
841 };
842
843 /* In the hardware, registers are laid out either singly, in arrays
844 * spaced 0x100 bytes apart, or in contiguous tables. We assume
845 * most tests take place on arrays or single registers (handled
846 * as a single-element array) and special-case the tables.
847 * Table tests are always pattern tests.
848 *
849 * We also make provision for some required setup steps by specifying
850 * registers to be written without any read-back testing.
851 */
852
853 #define PATTERN_TEST 1
854 #define SET_READ_TEST 2
855 #define WRITE_NO_TEST 3
856 #define TABLE32_TEST 4
857 #define TABLE64_TEST_LO 5
858 #define TABLE64_TEST_HI 6
859
860 /* 82576 reg test */
861 static struct igb_reg_test reg_test_82576[] = {
862 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
863 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
864 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
865 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
866 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
867 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
868 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
869 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
870 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
871 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
872 /* Enable all RX queues before testing. */
873 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
874 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
875 /* RDH is read-only for 82576, only test RDT. */
876 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
877 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
878 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
879 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
880 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
881 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
882 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
883 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
884 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
885 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
886 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
887 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
888 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
889 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
890 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
891 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
892 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
893 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
894 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
895 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
896 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
897 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
898 { 0, 0, 0, 0 }
899 };
900
901 /* 82575 register test */
902 static struct igb_reg_test reg_test_82575[] = {
903 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
904 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
905 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
906 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
907 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
908 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
909 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
910 /* Enable all four RX queues before testing. */
911 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
912 /* RDH is read-only for 82575, only test RDT. */
913 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
914 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
915 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
916 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
917 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
918 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
919 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
920 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
921 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
922 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
923 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
924 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
925 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
926 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
927 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
928 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
929 { 0, 0, 0, 0 }
930 };
931
932 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
933 int reg, u32 mask, u32 write)
934 {
935 struct e1000_hw *hw = &adapter->hw;
936 u32 pat, val;
937 u32 _test[] =
938 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
939 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
940 wr32(reg, (_test[pat] & write));
941 val = rd32(reg);
942 if (val != (_test[pat] & write & mask)) {
943 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
944 "failed: got 0x%08X expected 0x%08X\n",
945 reg, val, (_test[pat] & write & mask));
946 *data = reg;
947 return 1;
948 }
949 }
950 return 0;
951 }
952
953 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
954 int reg, u32 mask, u32 write)
955 {
956 struct e1000_hw *hw = &adapter->hw;
957 u32 val;
958 wr32(reg, write & mask);
959 val = rd32(reg);
960 if ((write & mask) != (val & mask)) {
961 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
962 " got 0x%08X expected 0x%08X\n", reg,
963 (val & mask), (write & mask));
964 *data = reg;
965 return 1;
966 }
967 return 0;
968 }
969
970 #define REG_PATTERN_TEST(reg, mask, write) \
971 do { \
972 if (reg_pattern_test(adapter, data, reg, mask, write)) \
973 return 1; \
974 } while (0)
975
976 #define REG_SET_AND_CHECK(reg, mask, write) \
977 do { \
978 if (reg_set_and_check(adapter, data, reg, mask, write)) \
979 return 1; \
980 } while (0)
981
982 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
983 {
984 struct e1000_hw *hw = &adapter->hw;
985 struct igb_reg_test *test;
986 u32 value, before, after;
987 u32 i, toggle;
988
989 toggle = 0x7FFFF3FF;
990
991 switch (adapter->hw.mac.type) {
992 case e1000_82576:
993 test = reg_test_82576;
994 break;
995 default:
996 test = reg_test_82575;
997 break;
998 }
999
1000 /* Because the status register is such a special case,
1001 * we handle it separately from the rest of the register
1002 * tests. Some bits are read-only, some toggle, and some
1003 * are writable on newer MACs.
1004 */
1005 before = rd32(E1000_STATUS);
1006 value = (rd32(E1000_STATUS) & toggle);
1007 wr32(E1000_STATUS, toggle);
1008 after = rd32(E1000_STATUS) & toggle;
1009 if (value != after) {
1010 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1011 "got: 0x%08X expected: 0x%08X\n", after, value);
1012 *data = 1;
1013 return 1;
1014 }
1015 /* restore previous status */
1016 wr32(E1000_STATUS, before);
1017
1018 /* Perform the remainder of the register test, looping through
1019 * the test table until we either fail or reach the null entry.
1020 */
1021 while (test->reg) {
1022 for (i = 0; i < test->array_len; i++) {
1023 switch (test->test_type) {
1024 case PATTERN_TEST:
1025 REG_PATTERN_TEST(test->reg +
1026 (i * test->reg_offset),
1027 test->mask,
1028 test->write);
1029 break;
1030 case SET_READ_TEST:
1031 REG_SET_AND_CHECK(test->reg +
1032 (i * test->reg_offset),
1033 test->mask,
1034 test->write);
1035 break;
1036 case WRITE_NO_TEST:
1037 writel(test->write,
1038 (adapter->hw.hw_addr + test->reg)
1039 + (i * test->reg_offset));
1040 break;
1041 case TABLE32_TEST:
1042 REG_PATTERN_TEST(test->reg + (i * 4),
1043 test->mask,
1044 test->write);
1045 break;
1046 case TABLE64_TEST_LO:
1047 REG_PATTERN_TEST(test->reg + (i * 8),
1048 test->mask,
1049 test->write);
1050 break;
1051 case TABLE64_TEST_HI:
1052 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1053 test->mask,
1054 test->write);
1055 break;
1056 }
1057 }
1058 test++;
1059 }
1060
1061 *data = 0;
1062 return 0;
1063 }
1064
1065 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1066 {
1067 u16 temp;
1068 u16 checksum = 0;
1069 u16 i;
1070
1071 *data = 0;
1072 /* Read and add up the contents of the EEPROM */
1073 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1074 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
1075 < 0) {
1076 *data = 1;
1077 break;
1078 }
1079 checksum += temp;
1080 }
1081
1082 /* If Checksum is not Correct return error else test passed */
1083 if ((checksum != (u16) NVM_SUM) && !(*data))
1084 *data = 2;
1085
1086 return *data;
1087 }
1088
1089 static irqreturn_t igb_test_intr(int irq, void *data)
1090 {
1091 struct net_device *netdev = (struct net_device *) data;
1092 struct igb_adapter *adapter = netdev_priv(netdev);
1093 struct e1000_hw *hw = &adapter->hw;
1094
1095 adapter->test_icr |= rd32(E1000_ICR);
1096
1097 return IRQ_HANDLED;
1098 }
1099
1100 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1101 {
1102 struct e1000_hw *hw = &adapter->hw;
1103 struct net_device *netdev = adapter->netdev;
1104 u32 mask, ics_mask, i = 0, shared_int = true;
1105 u32 irq = adapter->pdev->irq;
1106
1107 *data = 0;
1108
1109 /* Hook up test interrupt handler just for this test */
1110 if (adapter->msix_entries)
1111 /* NOTE: we don't test MSI-X interrupts here, yet */
1112 return 0;
1113
1114 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1115 shared_int = false;
1116 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1117 *data = 1;
1118 return -1;
1119 }
1120 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1121 netdev->name, netdev)) {
1122 shared_int = false;
1123 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1124 netdev->name, netdev)) {
1125 *data = 1;
1126 return -1;
1127 }
1128 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1129 (shared_int ? "shared" : "unshared"));
1130 /* Disable all the interrupts */
1131 wr32(E1000_IMC, 0xFFFFFFFF);
1132 msleep(10);
1133
1134 /* Define all writable bits for ICS */
1135 switch(hw->mac.type) {
1136 case e1000_82575:
1137 ics_mask = 0x37F47EDD;
1138 break;
1139 case e1000_82576:
1140 ics_mask = 0x77D4FBFD;
1141 break;
1142 default:
1143 ics_mask = 0x7FFFFFFF;
1144 break;
1145 }
1146
1147 /* Test each interrupt */
1148 for (; i < 31; i++) {
1149 /* Interrupt to test */
1150 mask = 1 << i;
1151
1152 if (!(mask & ics_mask))
1153 continue;
1154
1155 if (!shared_int) {
1156 /* Disable the interrupt to be reported in
1157 * the cause register and then force the same
1158 * interrupt and see if one gets posted. If
1159 * an interrupt was posted to the bus, the
1160 * test failed.
1161 */
1162 adapter->test_icr = 0;
1163
1164 /* Flush any pending interrupts */
1165 wr32(E1000_ICR, ~0);
1166
1167 wr32(E1000_IMC, mask);
1168 wr32(E1000_ICS, mask);
1169 msleep(10);
1170
1171 if (adapter->test_icr & mask) {
1172 *data = 3;
1173 break;
1174 }
1175 }
1176
1177 /* Enable the interrupt to be reported in
1178 * the cause register and then force the same
1179 * interrupt and see if one gets posted. If
1180 * an interrupt was not posted to the bus, the
1181 * test failed.
1182 */
1183 adapter->test_icr = 0;
1184
1185 /* Flush any pending interrupts */
1186 wr32(E1000_ICR, ~0);
1187
1188 wr32(E1000_IMS, mask);
1189 wr32(E1000_ICS, mask);
1190 msleep(10);
1191
1192 if (!(adapter->test_icr & mask)) {
1193 *data = 4;
1194 break;
1195 }
1196
1197 if (!shared_int) {
1198 /* Disable the other interrupts to be reported in
1199 * the cause register and then force the other
1200 * interrupts and see if any get posted. If
1201 * an interrupt was posted to the bus, the
1202 * test failed.
1203 */
1204 adapter->test_icr = 0;
1205
1206 /* Flush any pending interrupts */
1207 wr32(E1000_ICR, ~0);
1208
1209 wr32(E1000_IMC, ~mask);
1210 wr32(E1000_ICS, ~mask);
1211 msleep(10);
1212
1213 if (adapter->test_icr & mask) {
1214 *data = 5;
1215 break;
1216 }
1217 }
1218 }
1219
1220 /* Disable all the interrupts */
1221 wr32(E1000_IMC, ~0);
1222 msleep(10);
1223
1224 /* Unhook test interrupt handler */
1225 free_irq(irq, netdev);
1226
1227 return *data;
1228 }
1229
1230 static void igb_free_desc_rings(struct igb_adapter *adapter)
1231 {
1232 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1233 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1234 struct pci_dev *pdev = adapter->pdev;
1235 int i;
1236
1237 if (tx_ring->desc && tx_ring->buffer_info) {
1238 for (i = 0; i < tx_ring->count; i++) {
1239 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1240 if (buf->dma)
1241 pci_unmap_single(pdev, buf->dma, buf->length,
1242 PCI_DMA_TODEVICE);
1243 if (buf->skb)
1244 dev_kfree_skb(buf->skb);
1245 }
1246 }
1247
1248 if (rx_ring->desc && rx_ring->buffer_info) {
1249 for (i = 0; i < rx_ring->count; i++) {
1250 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1251 if (buf->dma)
1252 pci_unmap_single(pdev, buf->dma,
1253 IGB_RXBUFFER_2048,
1254 PCI_DMA_FROMDEVICE);
1255 if (buf->skb)
1256 dev_kfree_skb(buf->skb);
1257 }
1258 }
1259
1260 if (tx_ring->desc) {
1261 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1262 tx_ring->dma);
1263 tx_ring->desc = NULL;
1264 }
1265 if (rx_ring->desc) {
1266 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1267 rx_ring->dma);
1268 rx_ring->desc = NULL;
1269 }
1270
1271 kfree(tx_ring->buffer_info);
1272 tx_ring->buffer_info = NULL;
1273 kfree(rx_ring->buffer_info);
1274 rx_ring->buffer_info = NULL;
1275
1276 return;
1277 }
1278
1279 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1280 {
1281 struct e1000_hw *hw = &adapter->hw;
1282 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1283 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1284 struct pci_dev *pdev = adapter->pdev;
1285 struct igb_buffer *buffer_info;
1286 u32 rctl;
1287 int i, ret_val;
1288
1289 /* Setup Tx descriptor ring and Tx buffers */
1290
1291 if (!tx_ring->count)
1292 tx_ring->count = IGB_DEFAULT_TXD;
1293
1294 tx_ring->buffer_info = kcalloc(tx_ring->count,
1295 sizeof(struct igb_buffer),
1296 GFP_KERNEL);
1297 if (!tx_ring->buffer_info) {
1298 ret_val = 1;
1299 goto err_nomem;
1300 }
1301
1302 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1303 tx_ring->size = ALIGN(tx_ring->size, 4096);
1304 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1305 &tx_ring->dma);
1306 if (!tx_ring->desc) {
1307 ret_val = 2;
1308 goto err_nomem;
1309 }
1310 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1311
1312 wr32(E1000_TDBAL(0),
1313 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1314 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1315 wr32(E1000_TDLEN(0),
1316 tx_ring->count * sizeof(union e1000_adv_tx_desc));
1317 wr32(E1000_TDH(0), 0);
1318 wr32(E1000_TDT(0), 0);
1319 wr32(E1000_TCTL,
1320 E1000_TCTL_PSP | E1000_TCTL_EN |
1321 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1322 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1323
1324 for (i = 0; i < tx_ring->count; i++) {
1325 union e1000_adv_tx_desc *tx_desc;
1326 struct sk_buff *skb;
1327 unsigned int size = 1024;
1328
1329 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
1330 skb = alloc_skb(size, GFP_KERNEL);
1331 if (!skb) {
1332 ret_val = 3;
1333 goto err_nomem;
1334 }
1335 skb_put(skb, size);
1336 buffer_info = &tx_ring->buffer_info[i];
1337 buffer_info->skb = skb;
1338 buffer_info->length = skb->len;
1339 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1340 PCI_DMA_TODEVICE);
1341 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1342 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1343 E1000_ADVTXD_PAYLEN_SHIFT;
1344 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1345 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1346 E1000_TXD_CMD_IFCS |
1347 E1000_TXD_CMD_RS |
1348 E1000_ADVTXD_DTYP_DATA |
1349 E1000_ADVTXD_DCMD_DEXT);
1350 }
1351
1352 /* Setup Rx descriptor ring and Rx buffers */
1353
1354 if (!rx_ring->count)
1355 rx_ring->count = IGB_DEFAULT_RXD;
1356
1357 rx_ring->buffer_info = kcalloc(rx_ring->count,
1358 sizeof(struct igb_buffer),
1359 GFP_KERNEL);
1360 if (!rx_ring->buffer_info) {
1361 ret_val = 4;
1362 goto err_nomem;
1363 }
1364
1365 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1366 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1367 &rx_ring->dma);
1368 if (!rx_ring->desc) {
1369 ret_val = 5;
1370 goto err_nomem;
1371 }
1372 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1373
1374 rctl = rd32(E1000_RCTL);
1375 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1376 wr32(E1000_RDBAL(0),
1377 ((u64) rx_ring->dma & 0xFFFFFFFF));
1378 wr32(E1000_RDBAH(0),
1379 ((u64) rx_ring->dma >> 32));
1380 wr32(E1000_RDLEN(0), rx_ring->size);
1381 wr32(E1000_RDH(0), 0);
1382 wr32(E1000_RDT(0), 0);
1383 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1384 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1385 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1386 wr32(E1000_RCTL, rctl);
1387 wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
1388
1389 for (i = 0; i < rx_ring->count; i++) {
1390 union e1000_adv_rx_desc *rx_desc;
1391 struct sk_buff *skb;
1392
1393 buffer_info = &rx_ring->buffer_info[i];
1394 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
1395 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1396 GFP_KERNEL);
1397 if (!skb) {
1398 ret_val = 6;
1399 goto err_nomem;
1400 }
1401 skb_reserve(skb, NET_IP_ALIGN);
1402 buffer_info->skb = skb;
1403 buffer_info->dma = pci_map_single(pdev, skb->data,
1404 IGB_RXBUFFER_2048,
1405 PCI_DMA_FROMDEVICE);
1406 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
1407 memset(skb->data, 0x00, skb->len);
1408 }
1409
1410 return 0;
1411
1412 err_nomem:
1413 igb_free_desc_rings(adapter);
1414 return ret_val;
1415 }
1416
1417 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1418 {
1419 struct e1000_hw *hw = &adapter->hw;
1420
1421 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1422 igb_write_phy_reg(hw, 29, 0x001F);
1423 igb_write_phy_reg(hw, 30, 0x8FFC);
1424 igb_write_phy_reg(hw, 29, 0x001A);
1425 igb_write_phy_reg(hw, 30, 0x8FF0);
1426 }
1427
1428 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1429 {
1430 struct e1000_hw *hw = &adapter->hw;
1431 u32 ctrl_reg = 0;
1432
1433 hw->mac.autoneg = false;
1434
1435 if (hw->phy.type == e1000_phy_m88) {
1436 /* Auto-MDI/MDIX Off */
1437 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1438 /* reset to update Auto-MDI/MDIX */
1439 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1440 /* autoneg off */
1441 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1442 }
1443
1444 ctrl_reg = rd32(E1000_CTRL);
1445
1446 /* force 1000, set loopback */
1447 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1448
1449 /* Now set up the MAC to the same speed/duplex as the PHY. */
1450 ctrl_reg = rd32(E1000_CTRL);
1451 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1452 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1453 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1454 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1455 E1000_CTRL_FD | /* Force Duplex to FULL */
1456 E1000_CTRL_SLU); /* Set link up enable bit */
1457
1458 if (hw->phy.type == e1000_phy_m88)
1459 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1460
1461 wr32(E1000_CTRL, ctrl_reg);
1462
1463 /* Disable the receiver on the PHY so when a cable is plugged in, the
1464 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1465 */
1466 if (hw->phy.type == e1000_phy_m88)
1467 igb_phy_disable_receiver(adapter);
1468
1469 udelay(500);
1470
1471 return 0;
1472 }
1473
1474 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1475 {
1476 return igb_integrated_phy_loopback(adapter);
1477 }
1478
1479 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1480 {
1481 struct e1000_hw *hw = &adapter->hw;
1482 u32 reg;
1483
1484 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1485 reg = rd32(E1000_RCTL);
1486 reg |= E1000_RCTL_LBM_TCVR;
1487 wr32(E1000_RCTL, reg);
1488
1489 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1490
1491 reg = rd32(E1000_CTRL);
1492 reg &= ~(E1000_CTRL_RFCE |
1493 E1000_CTRL_TFCE |
1494 E1000_CTRL_LRST);
1495 reg |= E1000_CTRL_SLU |
1496 E1000_CTRL_FD;
1497 wr32(E1000_CTRL, reg);
1498
1499 /* Unset switch control to serdes energy detect */
1500 reg = rd32(E1000_CONNSW);
1501 reg &= ~E1000_CONNSW_ENRGSRC;
1502 wr32(E1000_CONNSW, reg);
1503
1504 /* Set PCS register for forced speed */
1505 reg = rd32(E1000_PCS_LCTL);
1506 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1507 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1508 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1509 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1510 E1000_PCS_LCTL_FSD | /* Force Speed */
1511 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1512 wr32(E1000_PCS_LCTL, reg);
1513
1514 return 0;
1515 } else if (hw->phy.media_type == e1000_media_type_copper) {
1516 return igb_set_phy_loopback(adapter);
1517 }
1518
1519 return 7;
1520 }
1521
1522 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1523 {
1524 struct e1000_hw *hw = &adapter->hw;
1525 u32 rctl;
1526 u16 phy_reg;
1527
1528 rctl = rd32(E1000_RCTL);
1529 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1530 wr32(E1000_RCTL, rctl);
1531
1532 hw->mac.autoneg = true;
1533 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1534 if (phy_reg & MII_CR_LOOPBACK) {
1535 phy_reg &= ~MII_CR_LOOPBACK;
1536 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1537 igb_phy_sw_reset(hw);
1538 }
1539 }
1540
1541 static void igb_create_lbtest_frame(struct sk_buff *skb,
1542 unsigned int frame_size)
1543 {
1544 memset(skb->data, 0xFF, frame_size);
1545 frame_size &= ~1;
1546 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1547 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1548 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1549 }
1550
1551 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1552 {
1553 frame_size &= ~1;
1554 if (*(skb->data + 3) == 0xFF)
1555 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1556 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1557 return 0;
1558 return 13;
1559 }
1560
1561 static int igb_run_loopback_test(struct igb_adapter *adapter)
1562 {
1563 struct e1000_hw *hw = &adapter->hw;
1564 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1565 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1566 struct pci_dev *pdev = adapter->pdev;
1567 int i, j, k, l, lc, good_cnt;
1568 int ret_val = 0;
1569 unsigned long time;
1570
1571 wr32(E1000_RDT(0), rx_ring->count - 1);
1572
1573 /* Calculate the loop count based on the largest descriptor ring
1574 * The idea is to wrap the largest ring a number of times using 64
1575 * send/receive pairs during each loop
1576 */
1577
1578 if (rx_ring->count <= tx_ring->count)
1579 lc = ((tx_ring->count / 64) * 2) + 1;
1580 else
1581 lc = ((rx_ring->count / 64) * 2) + 1;
1582
1583 k = l = 0;
1584 for (j = 0; j <= lc; j++) { /* loop count loop */
1585 for (i = 0; i < 64; i++) { /* send the packets */
1586 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1587 1024);
1588 pci_dma_sync_single_for_device(pdev,
1589 tx_ring->buffer_info[k].dma,
1590 tx_ring->buffer_info[k].length,
1591 PCI_DMA_TODEVICE);
1592 k++;
1593 if (k == tx_ring->count)
1594 k = 0;
1595 }
1596 wr32(E1000_TDT(0), k);
1597 msleep(200);
1598 time = jiffies; /* set the start time for the receive */
1599 good_cnt = 0;
1600 do { /* receive the sent packets */
1601 pci_dma_sync_single_for_cpu(pdev,
1602 rx_ring->buffer_info[l].dma,
1603 IGB_RXBUFFER_2048,
1604 PCI_DMA_FROMDEVICE);
1605
1606 ret_val = igb_check_lbtest_frame(
1607 rx_ring->buffer_info[l].skb, 1024);
1608 if (!ret_val)
1609 good_cnt++;
1610 l++;
1611 if (l == rx_ring->count)
1612 l = 0;
1613 /* time + 20 msecs (200 msecs on 2.4) is more than
1614 * enough time to complete the receives, if it's
1615 * exceeded, break and error off
1616 */
1617 } while (good_cnt < 64 && jiffies < (time + 20));
1618 if (good_cnt != 64) {
1619 ret_val = 13; /* ret_val is the same as mis-compare */
1620 break;
1621 }
1622 if (jiffies >= (time + 20)) {
1623 ret_val = 14; /* error code for time out error */
1624 break;
1625 }
1626 } /* end loop count loop */
1627 return ret_val;
1628 }
1629
1630 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1631 {
1632 /* PHY loopback cannot be performed if SoL/IDER
1633 * sessions are active */
1634 if (igb_check_reset_block(&adapter->hw)) {
1635 dev_err(&adapter->pdev->dev,
1636 "Cannot do PHY loopback test "
1637 "when SoL/IDER is active.\n");
1638 *data = 0;
1639 goto out;
1640 }
1641 *data = igb_setup_desc_rings(adapter);
1642 if (*data)
1643 goto out;
1644 *data = igb_setup_loopback_test(adapter);
1645 if (*data)
1646 goto err_loopback;
1647 *data = igb_run_loopback_test(adapter);
1648 igb_loopback_cleanup(adapter);
1649
1650 err_loopback:
1651 igb_free_desc_rings(adapter);
1652 out:
1653 return *data;
1654 }
1655
1656 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1657 {
1658 struct e1000_hw *hw = &adapter->hw;
1659 *data = 0;
1660 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1661 int i = 0;
1662 hw->mac.serdes_has_link = false;
1663
1664 /* On some blade server designs, link establishment
1665 * could take as long as 2-3 minutes */
1666 do {
1667 hw->mac.ops.check_for_link(&adapter->hw);
1668 if (hw->mac.serdes_has_link)
1669 return *data;
1670 msleep(20);
1671 } while (i++ < 3750);
1672
1673 *data = 1;
1674 } else {
1675 hw->mac.ops.check_for_link(&adapter->hw);
1676 if (hw->mac.autoneg)
1677 msleep(4000);
1678
1679 if (!(rd32(E1000_STATUS) &
1680 E1000_STATUS_LU))
1681 *data = 1;
1682 }
1683 return *data;
1684 }
1685
1686 static void igb_diag_test(struct net_device *netdev,
1687 struct ethtool_test *eth_test, u64 *data)
1688 {
1689 struct igb_adapter *adapter = netdev_priv(netdev);
1690 u16 autoneg_advertised;
1691 u8 forced_speed_duplex, autoneg;
1692 bool if_running = netif_running(netdev);
1693
1694 set_bit(__IGB_TESTING, &adapter->state);
1695 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1696 /* Offline tests */
1697
1698 /* save speed, duplex, autoneg settings */
1699 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1700 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1701 autoneg = adapter->hw.mac.autoneg;
1702
1703 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1704
1705 /* Link test performed before hardware reset so autoneg doesn't
1706 * interfere with test result */
1707 if (igb_link_test(adapter, &data[4]))
1708 eth_test->flags |= ETH_TEST_FL_FAILED;
1709
1710 if (if_running)
1711 /* indicate we're in test mode */
1712 dev_close(netdev);
1713 else
1714 igb_reset(adapter);
1715
1716 if (igb_reg_test(adapter, &data[0]))
1717 eth_test->flags |= ETH_TEST_FL_FAILED;
1718
1719 igb_reset(adapter);
1720 if (igb_eeprom_test(adapter, &data[1]))
1721 eth_test->flags |= ETH_TEST_FL_FAILED;
1722
1723 igb_reset(adapter);
1724 if (igb_intr_test(adapter, &data[2]))
1725 eth_test->flags |= ETH_TEST_FL_FAILED;
1726
1727 igb_reset(adapter);
1728 if (igb_loopback_test(adapter, &data[3]))
1729 eth_test->flags |= ETH_TEST_FL_FAILED;
1730
1731 /* restore speed, duplex, autoneg settings */
1732 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1733 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1734 adapter->hw.mac.autoneg = autoneg;
1735
1736 /* force this routine to wait until autoneg complete/timeout */
1737 adapter->hw.phy.autoneg_wait_to_complete = true;
1738 igb_reset(adapter);
1739 adapter->hw.phy.autoneg_wait_to_complete = false;
1740
1741 clear_bit(__IGB_TESTING, &adapter->state);
1742 if (if_running)
1743 dev_open(netdev);
1744 } else {
1745 dev_info(&adapter->pdev->dev, "online testing starting\n");
1746 /* Online tests */
1747 if (igb_link_test(adapter, &data[4]))
1748 eth_test->flags |= ETH_TEST_FL_FAILED;
1749
1750 /* Online tests aren't run; pass by default */
1751 data[0] = 0;
1752 data[1] = 0;
1753 data[2] = 0;
1754 data[3] = 0;
1755
1756 clear_bit(__IGB_TESTING, &adapter->state);
1757 }
1758 msleep_interruptible(4 * 1000);
1759 }
1760
1761 static int igb_wol_exclusion(struct igb_adapter *adapter,
1762 struct ethtool_wolinfo *wol)
1763 {
1764 struct e1000_hw *hw = &adapter->hw;
1765 int retval = 1; /* fail by default */
1766
1767 switch (hw->device_id) {
1768 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1769 /* WoL not supported */
1770 wol->supported = 0;
1771 break;
1772 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1773 case E1000_DEV_ID_82576_FIBER:
1774 case E1000_DEV_ID_82576_SERDES:
1775 /* Wake events not supported on port B */
1776 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1777 wol->supported = 0;
1778 break;
1779 }
1780 /* return success for non excluded adapter ports */
1781 retval = 0;
1782 break;
1783 case E1000_DEV_ID_82576_QUAD_COPPER:
1784 /* quad port adapters only support WoL on port A */
1785 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1786 wol->supported = 0;
1787 break;
1788 }
1789 /* return success for non excluded adapter ports */
1790 retval = 0;
1791 break;
1792 default:
1793 /* dual port cards only support WoL on port A from now on
1794 * unless it was enabled in the eeprom for port B
1795 * so exclude FUNC_1 ports from having WoL enabled */
1796 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1797 !adapter->eeprom_wol) {
1798 wol->supported = 0;
1799 break;
1800 }
1801
1802 retval = 0;
1803 }
1804
1805 return retval;
1806 }
1807
1808 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1809 {
1810 struct igb_adapter *adapter = netdev_priv(netdev);
1811
1812 wol->supported = WAKE_UCAST | WAKE_MCAST |
1813 WAKE_BCAST | WAKE_MAGIC;
1814 wol->wolopts = 0;
1815
1816 /* this function will set ->supported = 0 and return 1 if wol is not
1817 * supported by this hardware */
1818 if (igb_wol_exclusion(adapter, wol) ||
1819 !device_can_wakeup(&adapter->pdev->dev))
1820 return;
1821
1822 /* apply any specific unsupported masks here */
1823 switch (adapter->hw.device_id) {
1824 default:
1825 break;
1826 }
1827
1828 if (adapter->wol & E1000_WUFC_EX)
1829 wol->wolopts |= WAKE_UCAST;
1830 if (adapter->wol & E1000_WUFC_MC)
1831 wol->wolopts |= WAKE_MCAST;
1832 if (adapter->wol & E1000_WUFC_BC)
1833 wol->wolopts |= WAKE_BCAST;
1834 if (adapter->wol & E1000_WUFC_MAG)
1835 wol->wolopts |= WAKE_MAGIC;
1836
1837 return;
1838 }
1839
1840 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1841 {
1842 struct igb_adapter *adapter = netdev_priv(netdev);
1843
1844 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1845 return -EOPNOTSUPP;
1846
1847 if (igb_wol_exclusion(adapter, wol) ||
1848 !device_can_wakeup(&adapter->pdev->dev))
1849 return wol->wolopts ? -EOPNOTSUPP : 0;
1850
1851 /* these settings will always override what we currently have */
1852 adapter->wol = 0;
1853
1854 if (wol->wolopts & WAKE_UCAST)
1855 adapter->wol |= E1000_WUFC_EX;
1856 if (wol->wolopts & WAKE_MCAST)
1857 adapter->wol |= E1000_WUFC_MC;
1858 if (wol->wolopts & WAKE_BCAST)
1859 adapter->wol |= E1000_WUFC_BC;
1860 if (wol->wolopts & WAKE_MAGIC)
1861 adapter->wol |= E1000_WUFC_MAG;
1862
1863 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1864
1865 return 0;
1866 }
1867
1868 /* bit defines for adapter->led_status */
1869 #define IGB_LED_ON 0
1870
1871 static int igb_phys_id(struct net_device *netdev, u32 data)
1872 {
1873 struct igb_adapter *adapter = netdev_priv(netdev);
1874 struct e1000_hw *hw = &adapter->hw;
1875
1876 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1877 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1878
1879 igb_blink_led(hw);
1880 msleep_interruptible(data * 1000);
1881
1882 igb_led_off(hw);
1883 clear_bit(IGB_LED_ON, &adapter->led_status);
1884 igb_cleanup_led(hw);
1885
1886 return 0;
1887 }
1888
1889 static int igb_set_coalesce(struct net_device *netdev,
1890 struct ethtool_coalesce *ec)
1891 {
1892 struct igb_adapter *adapter = netdev_priv(netdev);
1893 struct e1000_hw *hw = &adapter->hw;
1894 int i;
1895
1896 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1897 ((ec->rx_coalesce_usecs > 3) &&
1898 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1899 (ec->rx_coalesce_usecs == 2))
1900 return -EINVAL;
1901
1902 /* convert to rate of irq's per second */
1903 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1904 adapter->itr_setting = ec->rx_coalesce_usecs;
1905 adapter->itr = IGB_START_ITR;
1906 } else {
1907 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1908 adapter->itr = adapter->itr_setting;
1909 }
1910
1911 for (i = 0; i < adapter->num_rx_queues; i++)
1912 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1913
1914 return 0;
1915 }
1916
1917 static int igb_get_coalesce(struct net_device *netdev,
1918 struct ethtool_coalesce *ec)
1919 {
1920 struct igb_adapter *adapter = netdev_priv(netdev);
1921
1922 if (adapter->itr_setting <= 3)
1923 ec->rx_coalesce_usecs = adapter->itr_setting;
1924 else
1925 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1926
1927 return 0;
1928 }
1929
1930
1931 static int igb_nway_reset(struct net_device *netdev)
1932 {
1933 struct igb_adapter *adapter = netdev_priv(netdev);
1934 if (netif_running(netdev))
1935 igb_reinit_locked(adapter);
1936 return 0;
1937 }
1938
1939 static int igb_get_sset_count(struct net_device *netdev, int sset)
1940 {
1941 switch (sset) {
1942 case ETH_SS_STATS:
1943 return IGB_STATS_LEN;
1944 case ETH_SS_TEST:
1945 return IGB_TEST_LEN;
1946 default:
1947 return -ENOTSUPP;
1948 }
1949 }
1950
1951 static void igb_get_ethtool_stats(struct net_device *netdev,
1952 struct ethtool_stats *stats, u64 *data)
1953 {
1954 struct igb_adapter *adapter = netdev_priv(netdev);
1955 u64 *queue_stat;
1956 int stat_count_tx = sizeof(struct igb_tx_queue_stats) / sizeof(u64);
1957 int stat_count_rx = sizeof(struct igb_rx_queue_stats) / sizeof(u64);
1958 int j;
1959 int i;
1960
1961 igb_update_stats(adapter);
1962 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1963 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1964 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1965 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1966 }
1967 for (j = 0; j < adapter->num_tx_queues; j++) {
1968 int k;
1969 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1970 for (k = 0; k < stat_count_tx; k++)
1971 data[i + k] = queue_stat[k];
1972 i += k;
1973 }
1974 for (j = 0; j < adapter->num_rx_queues; j++) {
1975 int k;
1976 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1977 for (k = 0; k < stat_count_rx; k++)
1978 data[i + k] = queue_stat[k];
1979 i += k;
1980 }
1981 }
1982
1983 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1984 {
1985 struct igb_adapter *adapter = netdev_priv(netdev);
1986 u8 *p = data;
1987 int i;
1988
1989 switch (stringset) {
1990 case ETH_SS_TEST:
1991 memcpy(data, *igb_gstrings_test,
1992 IGB_TEST_LEN*ETH_GSTRING_LEN);
1993 break;
1994 case ETH_SS_STATS:
1995 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1996 memcpy(p, igb_gstrings_stats[i].stat_string,
1997 ETH_GSTRING_LEN);
1998 p += ETH_GSTRING_LEN;
1999 }
2000 for (i = 0; i < adapter->num_tx_queues; i++) {
2001 sprintf(p, "tx_queue_%u_packets", i);
2002 p += ETH_GSTRING_LEN;
2003 sprintf(p, "tx_queue_%u_bytes", i);
2004 p += ETH_GSTRING_LEN;
2005 }
2006 for (i = 0; i < adapter->num_rx_queues; i++) {
2007 sprintf(p, "rx_queue_%u_packets", i);
2008 p += ETH_GSTRING_LEN;
2009 sprintf(p, "rx_queue_%u_bytes", i);
2010 p += ETH_GSTRING_LEN;
2011 sprintf(p, "rx_queue_%u_drops", i);
2012 p += ETH_GSTRING_LEN;
2013 }
2014 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2015 break;
2016 }
2017 }
2018
2019 static const struct ethtool_ops igb_ethtool_ops = {
2020 .get_settings = igb_get_settings,
2021 .set_settings = igb_set_settings,
2022 .get_drvinfo = igb_get_drvinfo,
2023 .get_regs_len = igb_get_regs_len,
2024 .get_regs = igb_get_regs,
2025 .get_wol = igb_get_wol,
2026 .set_wol = igb_set_wol,
2027 .get_msglevel = igb_get_msglevel,
2028 .set_msglevel = igb_set_msglevel,
2029 .nway_reset = igb_nway_reset,
2030 .get_link = ethtool_op_get_link,
2031 .get_eeprom_len = igb_get_eeprom_len,
2032 .get_eeprom = igb_get_eeprom,
2033 .set_eeprom = igb_set_eeprom,
2034 .get_ringparam = igb_get_ringparam,
2035 .set_ringparam = igb_set_ringparam,
2036 .get_pauseparam = igb_get_pauseparam,
2037 .set_pauseparam = igb_set_pauseparam,
2038 .get_rx_csum = igb_get_rx_csum,
2039 .set_rx_csum = igb_set_rx_csum,
2040 .get_tx_csum = igb_get_tx_csum,
2041 .set_tx_csum = igb_set_tx_csum,
2042 .get_sg = ethtool_op_get_sg,
2043 .set_sg = ethtool_op_set_sg,
2044 .get_tso = ethtool_op_get_tso,
2045 .set_tso = igb_set_tso,
2046 .self_test = igb_diag_test,
2047 .get_strings = igb_get_strings,
2048 .phys_id = igb_phys_id,
2049 .get_sset_count = igb_get_sset_count,
2050 .get_ethtool_stats = igb_get_ethtool_stats,
2051 .get_coalesce = igb_get_coalesce,
2052 .set_coalesce = igb_set_coalesce,
2053 };
2054
2055 void igb_set_ethtool_ops(struct net_device *netdev)
2056 {
2057 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2058 }
Linux with added FPC-III support