drivers/net/pcmcia/nmclan_cs.c

   1 /* ----------------------------------------------------------------------------
   2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
   3   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
   4
   5   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
   6   Access Controller for Ethernet (MACE).  It is essentially the Am2150
   7   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
   8
   9 Written by Roger C. Pao <rpao@paonet.org>
  10   Copyright 1995 Roger C. Pao
  11   Linux 2.5 cleanups Copyright Red Hat 2003
  12
  13   This software may be used and distributed according to the terms of
  14   the GNU General Public License.
  15
  16 Ported to Linux 1.3.* network driver environment by
  17   Matti Aarnio <mea@utu.fi>
  18
  19 References
  20
  21   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
  22   Am79C940 (MACE) Data Sheet, 1994
  23   Am79C90 (C-LANCE) Data Sheet, 1994
  24   Linux PCMCIA Programmer's Guide v1.17
  25   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
  26
  27   Eric Mears, New Media Corporation
  28   Tom Pollard, New Media Corporation
  29   Dean Siasoyco, New Media Corporation
  30   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
  31   Donald Becker <becker@scyld.com>
  32   David Hinds <dahinds@users.sourceforge.net>
  33
  34   The Linux client driver is based on the 3c589_cs.c client driver by
  35   David Hinds.
  36
  37   The Linux network driver outline is based on the 3c589_cs.c driver,
  38   the 8390.c driver, and the example skeleton.c kernel code, which are
  39   by Donald Becker.
  40
  41   The Am2150 network driver hardware interface code is based on the
  42   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
  43
  44   Special thanks for testing and help in debugging this driver goes
  45   to Ken Lesniak.
  46
  47 -------------------------------------------------------------------------------
  48 Driver Notes and Issues
  49 -------------------------------------------------------------------------------
  50
  51 1. Developed on a Dell 320SLi
  52    PCMCIA Card Services 2.6.2
  53    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
  54
  55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
  56    'insmod pcmcia_core.o io_speed=300'.
  57    This will avoid problems with fast systems which causes rx_framecnt
  58    to return random values.
  59
  60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
  61    before extraction.
  62
  63 4. There is a bad slow-down problem in this driver.
  64
  65 5. Future: Multicast processing.  In the meantime, do _not_ compile your
  66    kernel with multicast ip enabled.
  67
  68 -------------------------------------------------------------------------------
  69 History
  70 -------------------------------------------------------------------------------
  71 Log: nmclan_cs.c,v
  72  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@redhat.com>
  73  * Fixed hang on card eject as we probe it
  74  * Cleaned up to use new style locking.
  75  *
  76  * Revision 0.16  1995/07/01  06:42:17  rpao
  77  * Bug fix: nmclan_reset() called CardServices incorrectly.
  78  *
  79  * Revision 0.15  1995/05/24  08:09:47  rpao
  80  * Re-implement MULTI_TX dev->tbusy handling.
  81  *
  82  * Revision 0.14  1995/05/23  03:19:30  rpao
  83  * Added, in nmclan_config(), "tuple.Attributes = 0;".
  84  * Modified MACE ID check to ignore chip revision level.
  85  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
  86  *
  87  * Revision 0.13  1995/05/18  05:56:34  rpao
  88  * Statistics changes.
  89  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
  90  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
  91  *
  92  * Revision 0.12  1995/05/14  00:12:23  rpao
  93  * Statistics overhaul.
  94  *
  95
  96 95/05/13 rpao   V0.10a
  97                 Bug fix: MACE statistics counters used wrong I/O ports.
  98                 Bug fix: mace_interrupt() needed to allow statistics to be
  99                 processed without RX or TX interrupts pending.
 100 95/05/11 rpao   V0.10
 101                 Multiple transmit request processing.
 102                 Modified statistics to use MACE counters where possible.
 103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
 104                 *Released
 105 95/05/10 rpao   V0.08
 106                 Bug fix: Make all non-exported functions private by using
 107                 static keyword.
 108                 Bug fix: Test IntrCnt _before_ reading MACE_IR.
 109 95/05/10 rpao   V0.07 Statistics.
 110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
 111
 112 ---------------------------------------------------------------------------- */
 113
 114 #define DRV_NAME        "nmclan_cs"
 115 #define DRV_VERSION     "0.16"
 116
 117
 118 /* ----------------------------------------------------------------------------
 119 Conditional Compilation Options
 120 ---------------------------------------------------------------------------- */
 121
 122 #define MULTI_TX                        0
 123 #define RESET_ON_TIMEOUT                1
 124 #define TX_INTERRUPTABLE                1
 125 #define RESET_XILINX                    0
 126
 127 /* ----------------------------------------------------------------------------
 128 Include Files
 129 ---------------------------------------------------------------------------- */
 130
 131 #include <linux/module.h>
 132 #include <linux/kernel.h>
 133 #include <linux/init.h>
 134 #include <linux/ptrace.h>
 135 #include <linux/slab.h>
 136 #include <linux/string.h>
 137 #include <linux/timer.h>
 138 #include <linux/interrupt.h>
 139 #include <linux/in.h>
 140 #include <linux/delay.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/netdevice.h>
 143 #include <linux/etherdevice.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/if_arp.h>
 146 #include <linux/ioport.h>
 147 #include <linux/bitops.h>
 148
 149 #include <pcmcia/version.h>
 150 #include <pcmcia/cs_types.h>
 151 #include <pcmcia/cs.h>
 152 #include <pcmcia/cisreg.h>
 153 #include <pcmcia/cistpl.h>
 154 #include <pcmcia/ds.h>
 155
 156 #include <asm/uaccess.h>
 157 #include <asm/io.h>
 158 #include <asm/system.h>
 159
 160 /* ----------------------------------------------------------------------------
 161 Defines
 162 ---------------------------------------------------------------------------- */
 163
 164 #define ETHER_ADDR_LEN                  ETH_ALEN
 165                                         /* 6 bytes in an Ethernet Address */
 166 #define MACE_LADRF_LEN                  8
 167                                         /* 8 bytes in Logical Address Filter */
 168
 169 /* Loop Control Defines */
 170 #define MACE_MAX_IR_ITERATIONS          10
 171 #define MACE_MAX_RX_ITERATIONS          12
 172         /*
 173         TBD: Dean brought this up, and I assumed the hardware would
 174         handle it:
 175
 176         If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
 177         non-zero when the isr exits.  We may not get another interrupt
 178         to process the remaining packets for some time.
 179         */
 180
 181 /*
 182 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
 183 which manages the interface between the MACE and the PCMCIA bus.  It
 184 also includes buffer management for the 32K x 8 SRAM to control up to
 185 four transmit and 12 receive frames at a time.
 186 */
 187 #define AM2150_MAX_TX_FRAMES            4
 188 #define AM2150_MAX_RX_FRAMES            12
 189
 190 /* Am2150 Ethernet Card I/O Mapping */
 191 #define AM2150_RCV                      0x00
 192 #define AM2150_XMT                      0x04
 193 #define AM2150_XMT_SKIP                 0x09
 194 #define AM2150_RCV_NEXT                 0x0A
 195 #define AM2150_RCV_FRAME_COUNT          0x0B
 196 #define AM2150_MACE_BANK                0x0C
 197 #define AM2150_MACE_BASE                0x10
 198
 199 /* MACE Registers */
 200 #define MACE_RCVFIFO                    0
 201 #define MACE_XMTFIFO                    1
 202 #define MACE_XMTFC                      2
 203 #define MACE_XMTFS                      3
 204 #define MACE_XMTRC                      4
 205 #define MACE_RCVFC                      5
 206 #define MACE_RCVFS                      6
 207 #define MACE_FIFOFC                     7
 208 #define MACE_IR                         8
 209 #define MACE_IMR                        9
 210 #define MACE_PR                         10
 211 #define MACE_BIUCC                      11
 212 #define MACE_FIFOCC                     12
 213 #define MACE_MACCC                      13
 214 #define MACE_PLSCC                      14
 215 #define MACE_PHYCC                      15
 216 #define MACE_CHIPIDL                    16
 217 #define MACE_CHIPIDH                    17
 218 #define MACE_IAC                        18
 219 /* Reserved */
 220 #define MACE_LADRF                      20
 221 #define MACE_PADR                       21
 222 /* Reserved */
 223 /* Reserved */
 224 #define MACE_MPC                        24
 225 /* Reserved */
 226 #define MACE_RNTPC                      26
 227 #define MACE_RCVCC                      27
 228 /* Reserved */
 229 #define MACE_UTR                        29
 230 #define MACE_RTR1                       30
 231 #define MACE_RTR2                       31
 232
 233 /* MACE Bit Masks */
 234 #define MACE_XMTRC_EXDEF                0x80
 235 #define MACE_XMTRC_XMTRC                0x0F
 236
 237 #define MACE_XMTFS_XMTSV                0x80
 238 #define MACE_XMTFS_UFLO                 0x40
 239 #define MACE_XMTFS_LCOL                 0x20
 240 #define MACE_XMTFS_MORE                 0x10
 241 #define MACE_XMTFS_ONE                  0x08
 242 #define MACE_XMTFS_DEFER                0x04
 243 #define MACE_XMTFS_LCAR                 0x02
 244 #define MACE_XMTFS_RTRY                 0x01
 245
 246 #define MACE_RCVFS_RCVSTS               0xF000
 247 #define MACE_RCVFS_OFLO                 0x8000
 248 #define MACE_RCVFS_CLSN                 0x4000
 249 #define MACE_RCVFS_FRAM                 0x2000
 250 #define MACE_RCVFS_FCS                  0x1000
 251
 252 #define MACE_FIFOFC_RCVFC               0xF0
 253 #define MACE_FIFOFC_XMTFC               0x0F
 254
 255 #define MACE_IR_JAB                     0x80
 256 #define MACE_IR_BABL                    0x40
 257 #define MACE_IR_CERR                    0x20
 258 #define MACE_IR_RCVCCO                  0x10
 259 #define MACE_IR_RNTPCO                  0x08
 260 #define MACE_IR_MPCO                    0x04
 261 #define MACE_IR_RCVINT                  0x02
 262 #define MACE_IR_XMTINT                  0x01
 263
 264 #define MACE_MACCC_PROM                 0x80
 265 #define MACE_MACCC_DXMT2PD              0x40
 266 #define MACE_MACCC_EMBA                 0x20
 267 #define MACE_MACCC_RESERVED             0x10
 268 #define MACE_MACCC_DRCVPA               0x08
 269 #define MACE_MACCC_DRCVBC               0x04
 270 #define MACE_MACCC_ENXMT                0x02
 271 #define MACE_MACCC_ENRCV                0x01
 272
 273 #define MACE_PHYCC_LNKFL                0x80
 274 #define MACE_PHYCC_DLNKTST              0x40
 275 #define MACE_PHYCC_REVPOL               0x20
 276 #define MACE_PHYCC_DAPC                 0x10
 277 #define MACE_PHYCC_LRT                  0x08
 278 #define MACE_PHYCC_ASEL                 0x04
 279 #define MACE_PHYCC_RWAKE                0x02
 280 #define MACE_PHYCC_AWAKE                0x01
 281
 282 #define MACE_IAC_ADDRCHG                0x80
 283 #define MACE_IAC_PHYADDR                0x04
 284 #define MACE_IAC_LOGADDR                0x02
 285
 286 #define MACE_UTR_RTRE                   0x80
 287 #define MACE_UTR_RTRD                   0x40
 288 #define MACE_UTR_RPA                    0x20
 289 #define MACE_UTR_FCOLL                  0x10
 290 #define MACE_UTR_RCVFCSE                0x08
 291 #define MACE_UTR_LOOP_INCL_MENDEC       0x06
 292 #define MACE_UTR_LOOP_NO_MENDEC         0x04
 293 #define MACE_UTR_LOOP_EXTERNAL          0x02
 294 #define MACE_UTR_LOOP_NONE              0x00
 295 #define MACE_UTR_RESERVED               0x01
 296
 297 /* Switch MACE register bank (only 0 and 1 are valid) */
 298 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
 299
 300 #define MACE_IMR_DEFAULT \
 301   (0xFF - \
 302     ( \
 303       MACE_IR_CERR | \
 304       MACE_IR_RCVCCO | \
 305       MACE_IR_RNTPCO | \
 306       MACE_IR_MPCO | \
 307       MACE_IR_RCVINT | \
 308       MACE_IR_XMTINT \
 309     ) \
 310   )
 311 #undef MACE_IMR_DEFAULT
 312 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
 313
 314 #define TX_TIMEOUT              ((400*HZ)/1000)
 315
 316 /* ----------------------------------------------------------------------------
 317 Type Definitions
 318 ---------------------------------------------------------------------------- */
 319
 320 typedef struct _mace_statistics {
 321     /* MACE_XMTFS */
 322     int xmtsv;
 323     int uflo;
 324     int lcol;
 325     int more;
 326     int one;
 327     int defer;
 328     int lcar;
 329     int rtry;
 330
 331     /* MACE_XMTRC */
 332     int exdef;
 333     int xmtrc;
 334
 335     /* RFS1--Receive Status (RCVSTS) */
 336     int oflo;
 337     int clsn;
 338     int fram;
 339     int fcs;
 340
 341     /* RFS2--Runt Packet Count (RNTPC) */
 342     int rfs_rntpc;
 343
 344     /* RFS3--Receive Collision Count (RCVCC) */
 345     int rfs_rcvcc;
 346
 347     /* MACE_IR */
 348     int jab;
 349     int babl;
 350     int cerr;
 351     int rcvcco;
 352     int rntpco;
 353     int mpco;
 354
 355     /* MACE_MPC */
 356     int mpc;
 357
 358     /* MACE_RNTPC */
 359     int rntpc;
 360
 361     /* MACE_RCVCC */
 362     int rcvcc;
 363 } mace_statistics;
 364
 365 typedef struct _mace_private {
 366     dev_link_t link;
 367     dev_node_t node;
 368     struct net_device_stats linux_stats; /* Linux statistics counters */
 369     mace_statistics mace_stats; /* MACE chip statistics counters */
 370
 371     /* restore_multicast_list() state variables */
 372     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
 373     int multicast_num_addrs;
 374
 375     char tx_free_frames; /* Number of free transmit frame buffers */
 376     char tx_irq_disabled; /* MACE TX interrupt disabled */
 377
 378     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
 379 } mace_private;
 380
 381 /* ----------------------------------------------------------------------------
 382 Private Global Variables
 383 ---------------------------------------------------------------------------- */
 384
 385 #ifdef PCMCIA_DEBUG
 386 static char rcsid[] =
 387 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
 388 static char *version =
 389 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
 390 #endif
 391
 392 static dev_info_t dev_info="nmclan_cs";
 393 static dev_link_t *dev_list;
 394
 395 static char *if_names[]={
 396     "Auto", "10baseT", "BNC",
 397 };
 398
 399 /* ----------------------------------------------------------------------------
 400 Parameters
 401         These are the parameters that can be set during loading with
 402         'insmod'.
 403 ---------------------------------------------------------------------------- */
 404
 405 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
 406 MODULE_LICENSE("GPL");
 407
 408 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
 409
 410 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
 411 INT_MODULE_PARM(if_port, 0);
 412
 413 #ifdef PCMCIA_DEBUG
 414 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
 415 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
 416 #else
 417 #define DEBUG(n, args...)
 418 #endif
 419
 420 /* ----------------------------------------------------------------------------
 421 Function Prototypes
 422 ---------------------------------------------------------------------------- */
 423
 424 static void nmclan_config(dev_link_t *link);
 425 static void nmclan_release(dev_link_t *link);
 426 static int nmclan_event(event_t event, int priority,
 427                         event_callback_args_t *args);
 428
 429 static void nmclan_reset(struct net_device *dev);
 430 static int mace_config(struct net_device *dev, struct ifmap *map);
 431 static int mace_open(struct net_device *dev);
 432 static int mace_close(struct net_device *dev);
 433 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
 434 static void mace_tx_timeout(struct net_device *dev);
 435 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 436 static struct net_device_stats *mace_get_stats(struct net_device *dev);
 437 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
 438 static void restore_multicast_list(struct net_device *dev);
 439 static void set_multicast_list(struct net_device *dev);
 440 static struct ethtool_ops netdev_ethtool_ops;
 441
 442
 443 static dev_link_t *nmclan_attach(void);
 444 static void nmclan_detach(dev_link_t *);
 445
 446 /* ----------------------------------------------------------------------------
 447 nmclan_attach
 448         Creates an "instance" of the driver, allocating local data
 449         structures for one device.  The device is registered with Card
 450         Services.
 451 ---------------------------------------------------------------------------- */
 452
 453 static dev_link_t *nmclan_attach(void)
 454 {
 455     mace_private *lp;
 456     dev_link_t *link;
 457     struct net_device *dev;
 458     client_reg_t client_reg;
 459     int ret;
 460
 461     DEBUG(0, "nmclan_attach()\n");
 462     DEBUG(1, "%s\n", rcsid);
 463
 464     /* Create new ethernet device */
 465     dev = alloc_etherdev(sizeof(mace_private));
 466     if (!dev)
 467         return NULL;
 468     lp = netdev_priv(dev);
 469     link = &lp->link;
 470     link->priv = dev;
 471
 472     spin_lock_init(&lp->bank_lock);
 473     link->io.NumPorts1 = 32;
 474     link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
 475     link->io.IOAddrLines = 5;
 476     link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
 477     link->irq.IRQInfo1 = IRQ_LEVEL_ID;
 478     link->irq.Handler = &mace_interrupt;
 479     link->irq.Instance = dev;
 480     link->conf.Attributes = CONF_ENABLE_IRQ;
 481     link->conf.Vcc = 50;
 482     link->conf.IntType = INT_MEMORY_AND_IO;
 483     link->conf.ConfigIndex = 1;
 484     link->conf.Present = PRESENT_OPTION;
 485
 486     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 487
 488     SET_MODULE_OWNER(dev);
 489     dev->hard_start_xmit = &mace_start_xmit;
 490     dev->set_config = &mace_config;
 491     dev->get_stats = &mace_get_stats;
 492     dev->set_multicast_list = &set_multicast_list;
 493     SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
 494     dev->open = &mace_open;
 495     dev->stop = &mace_close;
 496 #ifdef HAVE_TX_TIMEOUT
 497     dev->tx_timeout = mace_tx_timeout;
 498     dev->watchdog_timeo = TX_TIMEOUT;
 499 #endif
 500
 501     /* Register with Card Services */
 502     link->next = dev_list;
 503     dev_list = link;
 504     client_reg.dev_info = &dev_info;
 505     client_reg.EventMask =
 506         CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL |
 507         CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET |
 508         CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME;
 509     client_reg.event_handler = &nmclan_event;
 510     client_reg.Version = 0x0210;
 511     client_reg.event_callback_args.client_data = link;
 512     ret = pcmcia_register_client(&link->handle, &client_reg);
 513     if (ret != 0) {
 514         cs_error(link->handle, RegisterClient, ret);
 515         nmclan_detach(link);
 516         return NULL;
 517     }
 518
 519     return link;
 520 } /* nmclan_attach */
 521
 522 /* ----------------------------------------------------------------------------
 523 nmclan_detach
 524         This deletes a driver "instance".  The device is de-registered
 525         with Card Services.  If it has been released, all local data
 526         structures are freed.  Otherwise, the structures will be freed
 527         when the device is released.
 528 ---------------------------------------------------------------------------- */
 529
 530 static void nmclan_detach(dev_link_t *link)
 531 {
 532     struct net_device *dev = link->priv;
 533     dev_link_t **linkp;
 534
 535     DEBUG(0, "nmclan_detach(0x%p)\n", link);
 536
 537     /* Locate device structure */
 538     for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
 539         if (*linkp == link) break;
 540     if (*linkp == NULL)
 541         return;
 542
 543     if (link->dev)
 544         unregister_netdev(dev);
 545
 546     if (link->state & DEV_CONFIG)
 547         nmclan_release(link);
 548
 549     if (link->handle)
 550         pcmcia_deregister_client(link->handle);
 551
 552     /* Unlink device structure, free bits */
 553     *linkp = link->next;
 554     free_netdev(dev);
 555 } /* nmclan_detach */
 556
 557 /* ----------------------------------------------------------------------------
 558 mace_read
 559         Reads a MACE register.  This is bank independent; however, the
 560         caller must ensure that this call is not interruptable.  We are
 561         assuming that during normal operation, the MACE is always in
 562         bank 0.
 563 ---------------------------------------------------------------------------- */
 564 static int mace_read(mace_private *lp, kio_addr_t ioaddr, int reg)
 565 {
 566   int data = 0xFF;
 567   unsigned long flags;
 568
 569   switch (reg >> 4) {
 570     case 0: /* register 0-15 */
 571       data = inb(ioaddr + AM2150_MACE_BASE + reg);
 572       break;
 573     case 1: /* register 16-31 */
 574       spin_lock_irqsave(&lp->bank_lock, flags);
 575       MACEBANK(1);
 576       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 577       MACEBANK(0);
 578       spin_unlock_irqrestore(&lp->bank_lock, flags);
 579       break;
 580   }
 581   return (data & 0xFF);
 582 } /* mace_read */
 583
 584 /* ----------------------------------------------------------------------------
 585 mace_write
 586         Writes to a MACE register.  This is bank independent; however,
 587         the caller must ensure that this call is not interruptable.  We
 588         are assuming that during normal operation, the MACE is always in
 589         bank 0.
 590 ---------------------------------------------------------------------------- */
 591 static void mace_write(mace_private *lp, kio_addr_t ioaddr, int reg, int data)
 592 {
 593   unsigned long flags;
 594
 595   switch (reg >> 4) {
 596     case 0: /* register 0-15 */
 597       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
 598       break;
 599     case 1: /* register 16-31 */
 600       spin_lock_irqsave(&lp->bank_lock, flags);
 601       MACEBANK(1);
 602       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 603       MACEBANK(0);
 604       spin_unlock_irqrestore(&lp->bank_lock, flags);
 605       break;
 606   }
 607 } /* mace_write */
 608
 609 /* ----------------------------------------------------------------------------
 610 mace_init
 611         Resets the MACE chip.
 612 ---------------------------------------------------------------------------- */
 613 static int mace_init(mace_private *lp, kio_addr_t ioaddr, char *enet_addr)
 614 {
 615   int i;
 616   int ct = 0;
 617
 618   /* MACE Software reset */
 619   mace_write(lp, ioaddr, MACE_BIUCC, 1);
 620   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
 621     /* Wait for reset bit to be cleared automatically after <= 200ns */;
 622     if(++ct > 500)
 623     {
 624         printk(KERN_ERR "mace: reset failed, card removed ?\n");
 625         return -1;
 626     }
 627     udelay(1);
 628   }
 629   mace_write(lp, ioaddr, MACE_BIUCC, 0);
 630
 631   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
 632   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
 633
 634   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
 635   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
 636
 637   /*
 638    * Bit 2-1 PORTSEL[1-0] Port Select.
 639    * 00 AUI/10Base-2
 640    * 01 10Base-T
 641    * 10 DAI Port (reserved in Am2150)
 642    * 11 GPSI
 643    * For this card, only the first two are valid.
 644    * So, PLSCC should be set to
 645    * 0x00 for 10Base-2
 646    * 0x02 for 10Base-T
 647    * Or just set ASEL in PHYCC below!
 648    */
 649   switch (if_port) {
 650     case 1:
 651       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
 652       break;
 653     case 2:
 654       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
 655       break;
 656     default:
 657       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
 658       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
 659          and the MACE device will automatically select the operating media
 660          interface port. */
 661       break;
 662   }
 663
 664   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
 665   /* Poll ADDRCHG bit */
 666   ct = 0;
 667   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
 668   {
 669         if(++ ct > 500)
 670         {
 671                 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
 672                 return -1;
 673         }
 674   }
 675   /* Set PADR register */
 676   for (i = 0; i < ETHER_ADDR_LEN; i++)
 677     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
 678
 679   /* MAC Configuration Control Register should be written last */
 680   /* Let set_multicast_list set this. */
 681   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
 682   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
 683   return 0;
 684 } /* mace_init */
 685
 686 /* ----------------------------------------------------------------------------
 687 nmclan_config
 688         This routine is scheduled to run after a CARD_INSERTION event
 689         is received, to configure the PCMCIA socket, and to make the
 690         ethernet device available to the system.
 691 ---------------------------------------------------------------------------- */
 692
 693 #define CS_CHECK(fn, ret) \
 694   do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 695
 696 static void nmclan_config(dev_link_t *link)
 697 {
 698   client_handle_t handle = link->handle;
 699   struct net_device *dev = link->priv;
 700   mace_private *lp = netdev_priv(dev);
 701   tuple_t tuple;
 702   cisparse_t parse;
 703   u_char buf[64];
 704   int i, last_ret, last_fn;
 705   kio_addr_t ioaddr;
 706
 707   DEBUG(0, "nmclan_config(0x%p)\n", link);
 708
 709   tuple.Attributes = 0;
 710   tuple.TupleData = buf;
 711   tuple.TupleDataMax = 64;
 712   tuple.TupleOffset = 0;
 713   tuple.DesiredTuple = CISTPL_CONFIG;
 714   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
 715   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
 716   CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
 717   link->conf.ConfigBase = parse.config.base;
 718
 719   /* Configure card */
 720   link->state |= DEV_CONFIG;
 721
 722   CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io));
 723   CS_CHECK(RequestIRQ, pcmcia_request_irq(handle, &link->irq));
 724   CS_CHECK(RequestConfiguration, pcmcia_request_configuration(handle, &link->conf));
 725   dev->irq = link->irq.AssignedIRQ;
 726   dev->base_addr = link->io.BasePort1;
 727
 728   ioaddr = dev->base_addr;
 729
 730   /* Read the ethernet address from the CIS. */
 731   tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
 732   tuple.TupleData = buf;
 733   tuple.TupleDataMax = 64;
 734   tuple.TupleOffset = 0;
 735   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
 736   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
 737   memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
 738
 739   /* Verify configuration by reading the MACE ID. */
 740   {
 741     char sig[2];
 742
 743     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
 744     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
 745     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
 746       DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
 747             sig[0], sig[1]);
 748     } else {
 749       printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
 750              " be 0x40 0x?9\n", sig[0], sig[1]);
 751       link->state &= ~DEV_CONFIG_PENDING;
 752       return;
 753     }
 754   }
 755
 756   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
 757         goto failed;
 758
 759   /* The if_port symbol can be set when the module is loaded */
 760   if (if_port <= 2)
 761     dev->if_port = if_port;
 762   else
 763     printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
 764
 765   link->dev = &lp->node;
 766   link->state &= ~DEV_CONFIG_PENDING;
 767   SET_NETDEV_DEV(dev, &handle_to_dev(handle));
 768
 769   i = register_netdev(dev);
 770   if (i != 0) {
 771     printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
 772     link->dev = NULL;
 773     goto failed;
 774   }
 775
 776   strcpy(lp->node.dev_name, dev->name);
 777
 778   printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",
 779          dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);
 780   for (i = 0; i < 6; i++)
 781       printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));
 782   return;
 783
 784 cs_failed:
 785     cs_error(link->handle, last_fn, last_ret);
 786 failed:
 787     nmclan_release(link);
 788     return;
 789
 790 } /* nmclan_config */
 791
 792 /* ----------------------------------------------------------------------------
 793 nmclan_release
 794         After a card is removed, nmclan_release() will unregister the
 795         net device, and release the PCMCIA configuration.  If the device
 796         is still open, this will be postponed until it is closed.
 797 ---------------------------------------------------------------------------- */
 798 static void nmclan_release(dev_link_t *link)
 799 {
 800
 801   DEBUG(0, "nmclan_release(0x%p)\n", link);
 802
 803   pcmcia_release_configuration(link->handle);
 804   pcmcia_release_io(link->handle, &link->io);
 805   pcmcia_release_irq(link->handle, &link->irq);
 806
 807   link->state &= ~DEV_CONFIG;
 808 }
 809
 810 /* ----------------------------------------------------------------------------
 811 nmclan_event
 812         The card status event handler.  Mostly, this schedules other
 813         stuff to run after an event is received.  A CARD_REMOVAL event
 814         also sets some flags to discourage the net drivers from trying
 815         to talk to the card any more.
 816 ---------------------------------------------------------------------------- */
 817 static int nmclan_event(event_t event, int priority,
 818                        event_callback_args_t *args)
 819 {
 820   dev_link_t *link = args->client_data;
 821   struct net_device *dev = link->priv;
 822
 823   DEBUG(1, "nmclan_event(0x%06x)\n", event);
 824
 825   switch (event) {
 826     case CS_EVENT_CARD_REMOVAL:
 827       link->state &= ~DEV_PRESENT;
 828       if (link->state & DEV_CONFIG)
 829         netif_device_detach(dev);
 830       break;
 831     case CS_EVENT_CARD_INSERTION:
 832       link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
 833       nmclan_config(link);
 834       break;
 835     case CS_EVENT_PM_SUSPEND:
 836       link->state |= DEV_SUSPEND;
 837       /* Fall through... */
 838     case CS_EVENT_RESET_PHYSICAL:
 839       if (link->state & DEV_CONFIG) {
 840         if (link->open)
 841           netif_device_detach(dev);
 842         pcmcia_release_configuration(link->handle);
 843       }
 844       break;
 845     case CS_EVENT_PM_RESUME:
 846       link->state &= ~DEV_SUSPEND;
 847       /* Fall through... */
 848     case CS_EVENT_CARD_RESET:
 849       if (link->state & DEV_CONFIG) {
 850         pcmcia_request_configuration(link->handle, &link->conf);
 851         if (link->open) {
 852           nmclan_reset(dev);
 853           netif_device_attach(dev);
 854         }
 855       }
 856       break;
 857     case CS_EVENT_RESET_REQUEST:
 858       return 1;
 859       break;
 860   }
 861   return 0;
 862 } /* nmclan_event */
 863
 864 /* ----------------------------------------------------------------------------
 865 nmclan_reset
 866         Reset and restore all of the Xilinx and MACE registers.
 867 ---------------------------------------------------------------------------- */
 868 static void nmclan_reset(struct net_device *dev)
 869 {
 870   mace_private *lp = netdev_priv(dev);
 871
 872 #if RESET_XILINX
 873   dev_link_t *link = &lp->link;
 874   conf_reg_t reg;
 875   u_long OrigCorValue;
 876
 877   /* Save original COR value */
 878   reg.Function = 0;
 879   reg.Action = CS_READ;
 880   reg.Offset = CISREG_COR;
 881   reg.Value = 0;
 882   pcmcia_access_configuration_register(link->handle, &reg);
 883   OrigCorValue = reg.Value;
 884
 885   /* Reset Xilinx */
 886   reg.Action = CS_WRITE;
 887   reg.Offset = CISREG_COR;
 888   DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
 889         OrigCorValue);
 890   reg.Value = COR_SOFT_RESET;
 891   pcmcia_access_configuration_register(link->handle, &reg);
 892   /* Need to wait for 20 ms for PCMCIA to finish reset. */
 893
 894   /* Restore original COR configuration index */
 895   reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
 896   pcmcia_access_configuration_register(link->handle, &reg);
 897   /* Xilinx is now completely reset along with the MACE chip. */
 898   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 899
 900 #endif /* #if RESET_XILINX */
 901
 902   /* Xilinx is now completely reset along with the MACE chip. */
 903   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 904
 905   /* Reinitialize the MACE chip for operation. */
 906   mace_init(lp, dev->base_addr, dev->dev_addr);
 907   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
 908
 909   /* Restore the multicast list and enable TX and RX. */
 910   restore_multicast_list(dev);
 911 } /* nmclan_reset */
 912
 913 /* ----------------------------------------------------------------------------
 914 mace_config
 915         [Someone tell me what this is supposed to do?  Is if_port a defined
 916         standard?  If so, there should be defines to indicate 1=10Base-T,
 917         2=10Base-2, etc. including limited automatic detection.]
 918 ---------------------------------------------------------------------------- */
 919 static int mace_config(struct net_device *dev, struct ifmap *map)
 920 {
 921   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
 922     if (map->port <= 2) {
 923       dev->if_port = map->port;
 924       printk(KERN_INFO "%s: switched to %s port\n", dev->name,
 925              if_names[dev->if_port]);
 926     } else
 927       return -EINVAL;
 928   }
 929   return 0;
 930 } /* mace_config */
 931
 932 /* ----------------------------------------------------------------------------
 933 mace_open
 934         Open device driver.
 935 ---------------------------------------------------------------------------- */
 936 static int mace_open(struct net_device *dev)
 937 {
 938   kio_addr_t ioaddr = dev->base_addr;
 939   mace_private *lp = netdev_priv(dev);
 940   dev_link_t *link = &lp->link;
 941
 942   if (!DEV_OK(link))
 943     return -ENODEV;
 944
 945   link->open++;
 946
 947   MACEBANK(0);
 948
 949   netif_start_queue(dev);
 950   nmclan_reset(dev);
 951
 952   return 0; /* Always succeed */
 953 } /* mace_open */
 954
 955 /* ----------------------------------------------------------------------------
 956 mace_close
 957         Closes device driver.
 958 ---------------------------------------------------------------------------- */
 959 static int mace_close(struct net_device *dev)
 960 {
 961   kio_addr_t ioaddr = dev->base_addr;
 962   mace_private *lp = netdev_priv(dev);
 963   dev_link_t *link = &lp->link;
 964
 965   DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
 966
 967   /* Mask off all interrupts from the MACE chip. */
 968   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 969
 970   link->open--;
 971   netif_stop_queue(dev);
 972
 973   return 0;
 974 } /* mace_close */
 975
 976 static void netdev_get_drvinfo(struct net_device *dev,
 977                                struct ethtool_drvinfo *info)
 978 {
 979         strcpy(info->driver, DRV_NAME);
 980         strcpy(info->version, DRV_VERSION);
 981         sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
 982 }
 983
 984 #ifdef PCMCIA_DEBUG
 985 static u32 netdev_get_msglevel(struct net_device *dev)
 986 {
 987         return pc_debug;
 988 }
 989
 990 static void netdev_set_msglevel(struct net_device *dev, u32 level)
 991 {
 992         pc_debug = level;
 993 }
 994 #endif /* PCMCIA_DEBUG */
 995
 996 static struct ethtool_ops netdev_ethtool_ops = {
 997         .get_drvinfo            = netdev_get_drvinfo,
 998 #ifdef PCMCIA_DEBUG
 999         .get_msglevel           = netdev_get_msglevel,
1000         .set_msglevel           = netdev_set_msglevel,
1001 #endif /* PCMCIA_DEBUG */
1002 };
1003
1004 /* ----------------------------------------------------------------------------
1005 mace_start_xmit
1006         This routine begins the packet transmit function.  When completed,
1007         it will generate a transmit interrupt.
1008
1009         According to /usr/src/linux/net/inet/dev.c, if _start_xmit
1010         returns 0, the "packet is now solely the responsibility of the
1011         driver."  If _start_xmit returns non-zero, the "transmission
1012         failed, put skb back into a list."
1013 ---------------------------------------------------------------------------- */
1014
1015 static void mace_tx_timeout(struct net_device *dev)
1016 {
1017   mace_private *lp = netdev_priv(dev);
1018   dev_link_t *link = &lp->link;
1019
1020   printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
1021 #if RESET_ON_TIMEOUT
1022   printk("resetting card\n");
1023   pcmcia_reset_card(link->handle, NULL);
1024 #else /* #if RESET_ON_TIMEOUT */
1025   printk("NOT resetting card\n");
1026 #endif /* #if RESET_ON_TIMEOUT */
1027   dev->trans_start = jiffies;
1028   netif_wake_queue(dev);
1029 }
1030
1031 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
1032 {
1033   mace_private *lp = netdev_priv(dev);
1034   kio_addr_t ioaddr = dev->base_addr;
1035
1036   netif_stop_queue(dev);
1037
1038   DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
1039         dev->name, (long)skb->len);
1040
1041 #if (!TX_INTERRUPTABLE)
1042   /* Disable MACE TX interrupts. */
1043   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
1044     ioaddr + AM2150_MACE_BASE + MACE_IMR);
1045   lp->tx_irq_disabled=1;
1046 #endif /* #if (!TX_INTERRUPTABLE) */
1047
1048   {
1049     /* This block must not be interrupted by another transmit request!
1050        mace_tx_timeout will take care of timer-based retransmissions from
1051        the upper layers.  The interrupt handler is guaranteed never to
1052        service a transmit interrupt while we are in here.
1053     */
1054
1055     lp->linux_stats.tx_bytes += skb->len;
1056     lp->tx_free_frames--;
1057
1058     /* WARNING: Write the _exact_ number of bytes written in the header! */
1059     /* Put out the word header [must be an outw()] . . . */
1060     outw(skb->len, ioaddr + AM2150_XMT);
1061     /* . . . and the packet [may be any combination of outw() and outb()] */
1062     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
1063     if (skb->len & 1) {
1064       /* Odd byte transfer */
1065       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
1066     }
1067
1068     dev->trans_start = jiffies;
1069
1070 #if MULTI_TX
1071     if (lp->tx_free_frames > 0)
1072       netif_start_queue(dev);
1073 #endif /* #if MULTI_TX */
1074   }
1075
1076 #if (!TX_INTERRUPTABLE)
1077   /* Re-enable MACE TX interrupts. */
1078   lp->tx_irq_disabled=0;
1079   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
1080 #endif /* #if (!TX_INTERRUPTABLE) */
1081
1082   dev_kfree_skb(skb);
1083
1084   return 0;
1085 } /* mace_start_xmit */
1086
1087 /* ----------------------------------------------------------------------------
1088 mace_interrupt
1089         The interrupt handler.
1090 ---------------------------------------------------------------------------- */
1091 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1092 {
1093   struct net_device *dev = (struct net_device *) dev_id;
1094   mace_private *lp = netdev_priv(dev);
1095   kio_addr_t ioaddr = dev->base_addr;
1096   int status;
1097   int IntrCnt = MACE_MAX_IR_ITERATIONS;
1098
1099   if (dev == NULL) {
1100     DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1101           irq);
1102     return IRQ_NONE;
1103   }
1104
1105   if (lp->tx_irq_disabled) {
1106     printk(
1107       (lp->tx_irq_disabled?
1108        KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1109        "[isr=%02X, imr=%02X]\n":
1110        KERN_NOTICE "%s: Re-entering the interrupt handler "
1111        "[isr=%02X, imr=%02X]\n"),
1112       dev->name,
1113       inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1114       inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1115     );
1116     /* WARNING: MACE_IR has been read! */
1117     return IRQ_NONE;
1118   }
1119
1120   if (!netif_device_present(dev)) {
1121     DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1122     return IRQ_NONE;
1123   }
1124
1125   do {
1126     /* WARNING: MACE_IR is a READ/CLEAR port! */
1127     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1128
1129     DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1130
1131     if (status & MACE_IR_RCVINT) {
1132       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1133     }
1134
1135     if (status & MACE_IR_XMTINT) {
1136       unsigned char fifofc;
1137       unsigned char xmtrc;
1138       unsigned char xmtfs;
1139
1140       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1141       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1142         lp->linux_stats.tx_errors++;
1143         outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1144       }
1145
1146       /* Transmit Retry Count (XMTRC, reg 4) */
1147       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1148       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1149       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1150
1151       if (
1152         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1153         MACE_XMTFS_XMTSV /* Transmit Status Valid */
1154       ) {
1155         lp->mace_stats.xmtsv++;
1156
1157         if (xmtfs & ~MACE_XMTFS_XMTSV) {
1158           if (xmtfs & MACE_XMTFS_UFLO) {
1159             /* Underflow.  Indicates that the Transmit FIFO emptied before
1160                the end of frame was reached. */
1161             lp->mace_stats.uflo++;
1162           }
1163           if (xmtfs & MACE_XMTFS_LCOL) {
1164             /* Late Collision */
1165             lp->mace_stats.lcol++;
1166           }
1167           if (xmtfs & MACE_XMTFS_MORE) {
1168             /* MORE than one retry was needed */
1169             lp->mace_stats.more++;
1170           }
1171           if (xmtfs & MACE_XMTFS_ONE) {
1172             /* Exactly ONE retry occurred */
1173             lp->mace_stats.one++;
1174           }
1175           if (xmtfs & MACE_XMTFS_DEFER) {
1176             /* Transmission was defered */
1177             lp->mace_stats.defer++;
1178           }
1179           if (xmtfs & MACE_XMTFS_LCAR) {
1180             /* Loss of carrier */
1181             lp->mace_stats.lcar++;
1182           }
1183           if (xmtfs & MACE_XMTFS_RTRY) {
1184             /* Retry error: transmit aborted after 16 attempts */
1185             lp->mace_stats.rtry++;
1186           }
1187         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1188
1189       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1190
1191       lp->linux_stats.tx_packets++;
1192       lp->tx_free_frames++;
1193       netif_wake_queue(dev);
1194     } /* if (status & MACE_IR_XMTINT) */
1195
1196     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1197       if (status & MACE_IR_JAB) {
1198         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1199         lp->mace_stats.jab++;
1200       }
1201       if (status & MACE_IR_BABL) {
1202         /* Babble Error.  >1518 bytes transmitted. */
1203         lp->mace_stats.babl++;
1204       }
1205       if (status & MACE_IR_CERR) {
1206         /* Collision Error.  CERR indicates the absence of the
1207            Signal Quality Error Test message after a packet
1208            transmission. */
1209         lp->mace_stats.cerr++;
1210       }
1211       if (status & MACE_IR_RCVCCO) {
1212         /* Receive Collision Count Overflow; */
1213         lp->mace_stats.rcvcco++;
1214       }
1215       if (status & MACE_IR_RNTPCO) {
1216         /* Runt Packet Count Overflow */
1217         lp->mace_stats.rntpco++;
1218       }
1219       if (status & MACE_IR_MPCO) {
1220         /* Missed Packet Count Overflow */
1221         lp->mace_stats.mpco++;
1222       }
1223     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1224
1225   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1226
1227   return IRQ_HANDLED;
1228 } /* mace_interrupt */
1229
1230 /* ----------------------------------------------------------------------------
1231 mace_rx
1232         Receives packets.
1233 ---------------------------------------------------------------------------- */
1234 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1235 {
1236   mace_private *lp = netdev_priv(dev);
1237   kio_addr_t ioaddr = dev->base_addr;
1238   unsigned char rx_framecnt;
1239   unsigned short rx_status;
1240
1241   while (
1242     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1243     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1244     (RxCnt--)
1245   ) {
1246     rx_status = inw(ioaddr + AM2150_RCV);
1247
1248     DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1249           " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1250
1251     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1252       lp->linux_stats.rx_errors++;
1253       if (rx_status & MACE_RCVFS_OFLO) {
1254         lp->mace_stats.oflo++;
1255       }
1256       if (rx_status & MACE_RCVFS_CLSN) {
1257         lp->mace_stats.clsn++;
1258       }
1259       if (rx_status & MACE_RCVFS_FRAM) {
1260         lp->mace_stats.fram++;
1261       }
1262       if (rx_status & MACE_RCVFS_FCS) {
1263         lp->mace_stats.fcs++;
1264       }
1265     } else {
1266       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1267         /* Auto Strip is off, always subtract 4 */
1268       struct sk_buff *skb;
1269
1270       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1271         /* runt packet count */
1272       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1273         /* rcv collision count */
1274
1275       DEBUG(3, "    receiving packet size 0x%X rx_status"
1276             " 0x%X.\n", pkt_len, rx_status);
1277
1278       skb = dev_alloc_skb(pkt_len+2);
1279
1280       if (skb != NULL) {
1281         skb->dev = dev;
1282
1283         skb_reserve(skb, 2);
1284         insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1285         if (pkt_len & 1)
1286             *(skb->tail-1) = inb(ioaddr + AM2150_RCV);
1287         skb->protocol = eth_type_trans(skb, dev);
1288
1289         netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1290
1291         dev->last_rx = jiffies;
1292         lp->linux_stats.rx_packets++;
1293         lp->linux_stats.rx_bytes += skb->len;
1294         outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1295         continue;
1296       } else {
1297         DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1298               " %d.\n", dev->name, pkt_len);
1299         lp->linux_stats.rx_dropped++;
1300       }
1301     }
1302     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1303   } /* while */
1304
1305   return 0;
1306 } /* mace_rx */
1307
1308 /* ----------------------------------------------------------------------------
1309 pr_linux_stats
1310 ---------------------------------------------------------------------------- */
1311 static void pr_linux_stats(struct net_device_stats *pstats)
1312 {
1313   DEBUG(2, "pr_linux_stats\n");
1314   DEBUG(2, " rx_packets=%-7ld        tx_packets=%ld\n",
1315         (long)pstats->rx_packets, (long)pstats->tx_packets);
1316   DEBUG(2, " rx_errors=%-7ld         tx_errors=%ld\n",
1317         (long)pstats->rx_errors, (long)pstats->tx_errors);
1318   DEBUG(2, " rx_dropped=%-7ld        tx_dropped=%ld\n",
1319         (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1320   DEBUG(2, " multicast=%-7ld         collisions=%ld\n",
1321         (long)pstats->multicast, (long)pstats->collisions);
1322
1323   DEBUG(2, " rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1324         (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1325   DEBUG(2, " rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1326         (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1327   DEBUG(2, " rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1328         (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1329
1330   DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1331         (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1332   DEBUG(2, " tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1333         (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1334   DEBUG(2, " tx_window_errors=%ld\n",
1335         (long)pstats->tx_window_errors);
1336 } /* pr_linux_stats */
1337
1338 /* ----------------------------------------------------------------------------
1339 pr_mace_stats
1340 ---------------------------------------------------------------------------- */
1341 static void pr_mace_stats(mace_statistics *pstats)
1342 {
1343   DEBUG(2, "pr_mace_stats\n");
1344
1345   DEBUG(2, " xmtsv=%-7d             uflo=%d\n",
1346         pstats->xmtsv, pstats->uflo);
1347   DEBUG(2, " lcol=%-7d              more=%d\n",
1348         pstats->lcol, pstats->more);
1349   DEBUG(2, " one=%-7d               defer=%d\n",
1350         pstats->one, pstats->defer);
1351   DEBUG(2, " lcar=%-7d              rtry=%d\n",
1352         pstats->lcar, pstats->rtry);
1353
1354   /* MACE_XMTRC */
1355   DEBUG(2, " exdef=%-7d             xmtrc=%d\n",
1356         pstats->exdef, pstats->xmtrc);
1357
1358   /* RFS1--Receive Status (RCVSTS) */
1359   DEBUG(2, " oflo=%-7d              clsn=%d\n",
1360         pstats->oflo, pstats->clsn);
1361   DEBUG(2, " fram=%-7d              fcs=%d\n",
1362         pstats->fram, pstats->fcs);
1363
1364   /* RFS2--Runt Packet Count (RNTPC) */
1365   /* RFS3--Receive Collision Count (RCVCC) */
1366   DEBUG(2, " rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1367         pstats->rfs_rntpc, pstats->rfs_rcvcc);
1368
1369   /* MACE_IR */
1370   DEBUG(2, " jab=%-7d               babl=%d\n",
1371         pstats->jab, pstats->babl);
1372   DEBUG(2, " cerr=%-7d              rcvcco=%d\n",
1373         pstats->cerr, pstats->rcvcco);
1374   DEBUG(2, " rntpco=%-7d            mpco=%d\n",
1375         pstats->rntpco, pstats->mpco);
1376
1377   /* MACE_MPC */
1378   DEBUG(2, " mpc=%d\n", pstats->mpc);
1379
1380   /* MACE_RNTPC */
1381   DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1382
1383   /* MACE_RCVCC */
1384   DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1385
1386 } /* pr_mace_stats */
1387
1388 /* ----------------------------------------------------------------------------
1389 update_stats
1390         Update statistics.  We change to register window 1, so this
1391         should be run single-threaded if the device is active. This is
1392         expected to be a rare operation, and it's simpler for the rest
1393         of the driver to assume that window 0 is always valid rather
1394         than use a special window-state variable.
1395
1396         oflo & uflo should _never_ occur since it would mean the Xilinx
1397         was not able to transfer data between the MACE FIFO and the
1398         card's SRAM fast enough.  If this happens, something is
1399         seriously wrong with the hardware.
1400 ---------------------------------------------------------------------------- */
1401 static void update_stats(kio_addr_t ioaddr, struct net_device *dev)
1402 {
1403   mace_private *lp = netdev_priv(dev);
1404
1405   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1406   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1407   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1408   /* At this point, mace_stats is fully updated for this call.
1409      We may now update the linux_stats. */
1410
1411   /* The MACE has no equivalent for linux_stats field which are commented
1412      out. */
1413
1414   /* lp->linux_stats.multicast; */
1415   lp->linux_stats.collisions =
1416     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1417     /* Collision: The MACE may retry sending a packet 15 times
1418        before giving up.  The retry count is in XMTRC.
1419        Does each retry constitute a collision?
1420        If so, why doesn't the RCVCC record these collisions? */
1421
1422   /* detailed rx_errors: */
1423   lp->linux_stats.rx_length_errors =
1424     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1425   /* lp->linux_stats.rx_over_errors */
1426   lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1427   lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1428   lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1429   lp->linux_stats.rx_missed_errors =
1430     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1431
1432   /* detailed tx_errors */
1433   lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1434   lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1435     /* LCAR usually results from bad cabling. */
1436   lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1437   lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1438   /* lp->linux_stats.tx_window_errors; */
1439
1440   return;
1441 } /* update_stats */
1442
1443 /* ----------------------------------------------------------------------------
1444 mace_get_stats
1445         Gathers ethernet statistics from the MACE chip.
1446 ---------------------------------------------------------------------------- */
1447 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1448 {
1449   mace_private *lp = netdev_priv(dev);
1450
1451   update_stats(dev->base_addr, dev);
1452
1453   DEBUG(1, "%s: updating the statistics.\n", dev->name);
1454   pr_linux_stats(&lp->linux_stats);
1455   pr_mace_stats(&lp->mace_stats);
1456
1457   return &lp->linux_stats;
1458 } /* net_device_stats */
1459
1460 /* ----------------------------------------------------------------------------
1461 updateCRC
1462         Modified from Am79C90 data sheet.
1463 ---------------------------------------------------------------------------- */
1464
1465 #ifdef BROKEN_MULTICAST
1466
1467 static void updateCRC(int *CRC, int bit)
1468 {
1469   int poly[]={
1470     1,1,1,0, 1,1,0,1,
1471     1,0,1,1, 1,0,0,0,
1472     1,0,0,0, 0,0,1,1,
1473     0,0,1,0, 0,0,0,0
1474   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1475         CRC generator polynomial. */
1476
1477   int j;
1478
1479   /* shift CRC and control bit (CRC[32]) */
1480   for (j = 32; j > 0; j--)
1481     CRC[j] = CRC[j-1];
1482   CRC[0] = 0;
1483
1484   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1485   if (bit ^ CRC[32])
1486     for (j = 0; j < 32; j++)
1487       CRC[j] ^= poly[j];
1488 } /* updateCRC */
1489
1490 /* ----------------------------------------------------------------------------
1491 BuildLAF
1492         Build logical address filter.
1493         Modified from Am79C90 data sheet.
1494
1495 Input
1496         ladrf: logical address filter (contents initialized to 0)
1497         adr: ethernet address
1498 ---------------------------------------------------------------------------- */
1499 static void BuildLAF(int *ladrf, int *adr)
1500 {
1501   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1502
1503   int i, byte; /* temporary array indices */
1504   int hashcode; /* the output object */
1505
1506   CRC[32]=0;
1507
1508   for (byte = 0; byte < 6; byte++)
1509     for (i = 0; i < 8; i++)
1510       updateCRC(CRC, (adr[byte] >> i) & 1);
1511
1512   hashcode = 0;
1513   for (i = 0; i < 6; i++)
1514     hashcode = (hashcode << 1) + CRC[i];
1515
1516   byte = hashcode >> 3;
1517   ladrf[byte] |= (1 << (hashcode & 7));
1518
1519 #ifdef PCMCIA_DEBUG
1520   if (pc_debug > 2) {
1521     printk(KERN_DEBUG "    adr =");
1522     for (i = 0; i < 6; i++)
1523       printk(" %02X", adr[i]);
1524     printk("\n" KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63]"
1525            " =", hashcode);
1526     for (i = 0; i < 8; i++)
1527       printk(" %02X", ladrf[i]);
1528     printk("\n");
1529   }
1530 #endif
1531 } /* BuildLAF */
1532
1533 /* ----------------------------------------------------------------------------
1534 restore_multicast_list
1535         Restores the multicast filter for MACE chip to the last
1536         set_multicast_list() call.
1537
1538 Input
1539         multicast_num_addrs
1540         multicast_ladrf[]
1541 ---------------------------------------------------------------------------- */
1542 static void restore_multicast_list(struct net_device *dev)
1543 {
1544   mace_private *lp = netdev_priv(dev);
1545   int num_addrs = lp->multicast_num_addrs;
1546   int *ladrf = lp->multicast_ladrf;
1547   kio_addr_t ioaddr = dev->base_addr;
1548   int i;
1549
1550   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1551         dev->name, num_addrs);
1552
1553   if (num_addrs > 0) {
1554
1555     DEBUG(1, "Attempt to restore multicast list detected.\n");
1556
1557     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1558     /* Poll ADDRCHG bit */
1559     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1560       ;
1561     /* Set LADRF register */
1562     for (i = 0; i < MACE_LADRF_LEN; i++)
1563       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1564
1565     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1566     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1567
1568   } else if (num_addrs < 0) {
1569
1570     /* Promiscuous mode: receive all packets */
1571     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1572     mace_write(lp, ioaddr, MACE_MACCC,
1573       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1574     );
1575
1576   } else {
1577
1578     /* Normal mode */
1579     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1580     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1581
1582   }
1583 } /* restore_multicast_list */
1584
1585 /* ----------------------------------------------------------------------------
1586 set_multicast_list
1587         Set or clear the multicast filter for this adaptor.
1588
1589 Input
1590         num_addrs == -1 Promiscuous mode, receive all packets
1591         num_addrs == 0  Normal mode, clear multicast list
1592         num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1593                         best-effort filtering.
1594 Output
1595         multicast_num_addrs
1596         multicast_ladrf[]
1597 ---------------------------------------------------------------------------- */
1598
1599 static void set_multicast_list(struct net_device *dev)
1600 {
1601   mace_private *lp = netdev_priv(dev);
1602   int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1603   int i;
1604   struct dev_mc_list *dmi = dev->mc_list;
1605
1606 #ifdef PCMCIA_DEBUG
1607   if (pc_debug > 1) {
1608     static int old;
1609     if (dev->mc_count != old) {
1610       old = dev->mc_count;
1611       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1612             dev->name, old);
1613     }
1614   }
1615 #endif
1616
1617   /* Set multicast_num_addrs. */
1618   lp->multicast_num_addrs = dev->mc_count;
1619
1620   /* Set multicast_ladrf. */
1621   if (num_addrs > 0) {
1622     /* Calculate multicast logical address filter */
1623     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1624     for (i = 0; i < dev->mc_count; i++) {
1625       memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1626       dmi = dmi->next;
1627       BuildLAF(lp->multicast_ladrf, adr);
1628     }
1629   }
1630
1631   restore_multicast_list(dev);
1632
1633 } /* set_multicast_list */
1634
1635 #endif /* BROKEN_MULTICAST */
1636
1637 static void restore_multicast_list(struct net_device *dev)
1638 {
1639   kio_addr_t ioaddr = dev->base_addr;
1640   mace_private *lp = netdev_priv(dev);
1641
1642   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1643         lp->multicast_num_addrs);
1644
1645   if (dev->flags & IFF_PROMISC) {
1646     /* Promiscuous mode: receive all packets */
1647     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1648     mace_write(lp, ioaddr, MACE_MACCC,
1649       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1650     );
1651   } else {
1652     /* Normal mode */
1653     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1654     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1655   }
1656 } /* restore_multicast_list */
1657
1658 static void set_multicast_list(struct net_device *dev)
1659 {
1660   mace_private *lp = netdev_priv(dev);
1661
1662 #ifdef PCMCIA_DEBUG
1663   if (pc_debug > 1) {
1664     static int old;
1665     if (dev->mc_count != old) {
1666       old = dev->mc_count;
1667       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1668             dev->name, old);
1669     }
1670   }
1671 #endif
1672
1673   lp->multicast_num_addrs = dev->mc_count;
1674   restore_multicast_list(dev);
1675
1676 } /* set_multicast_list */
1677
1678 static struct pcmcia_driver nmclan_cs_driver = {
1679         .owner          = THIS_MODULE,
1680         .drv            = {
1681                 .name   = "nmclan_cs",
1682         },
1683         .attach         = nmclan_attach,
1684         .detach         = nmclan_detach,
1685 };
1686
1687 static int __init init_nmclan_cs(void)
1688 {
1689         return pcmcia_register_driver(&nmclan_cs_driver);
1690 }
1691
1692 static void __exit exit_nmclan_cs(void)
1693 {
1694         pcmcia_unregister_driver(&nmclan_cs_driver);
1695         BUG_ON(dev_list != NULL);
1696 }
1697
1698 module_init(init_nmclan_cs);
1699 module_exit(exit_nmclan_cs);