drivers/scsi/blz1230.c

   1 /* blz1230.c: Driver for Blizzard 1230 SCSI IV Controller.
   2  *
   3  * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
   4  *
   5  * This driver is based on the CyberStorm driver, hence the occasional
   6  * reference to CyberStorm.
   7  */
   8
   9 /* TODO:
  10  *
  11  * 1) Figure out how to make a cleaner merge with the sparc driver with regard
  12  *    to the caches and the Sparc MMU mapping.
  13  * 2) Make as few routines required outside the generic driver. A lot of the
  14  *    routines in this file used to be inline!
  15  */
  16
  17 #include <linux/module.h>
  18
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/types.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/proc_fs.h>
  27 #include <linux/stat.h>
  28 #include <linux/interrupt.h>
  29
  30 #include "scsi.h"
  31 #include <scsi/scsi_host.h>
  32 #include "NCR53C9x.h"
  33
  34 #include <linux/zorro.h>
  35 #include <asm/irq.h>
  36 #include <asm/amigaints.h>
  37 #include <asm/amigahw.h>
  38
  39 #include <asm/pgtable.h>
  40
  41 #define MKIV 1
  42
  43 /* The controller registers can be found in the Z2 config area at these
  44  * offsets:
  45  */
  46 #define BLZ1230_ESP_ADDR 0x8000
  47 #define BLZ1230_DMA_ADDR 0x10000
  48 #define BLZ1230II_ESP_ADDR 0x10000
  49 #define BLZ1230II_DMA_ADDR 0x10021
  50
  51
  52 /* The Blizzard 1230 DMA interface
  53  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  54  * Only two things can be programmed in the Blizzard DMA:
  55  *  1) The data direction is controlled by the status of bit 31 (1 = write)
  56  *  2) The source/dest address (word aligned, shifted one right) in bits 30-0
  57  *
  58  * Program DMA by first latching the highest byte of the address/direction
  59  * (i.e. bits 31-24 of the long word constructed as described in steps 1+2
  60  * above). Then write each byte of the address/direction (starting with the
  61  * top byte, working down) to the DMA address register.
  62  *
  63  * Figure out interrupt status by reading the ESP status byte.
  64  */
  65 struct blz1230_dma_registers {
  66         volatile unsigned char dma_addr;        /* DMA address      [0x0000] */
  67         unsigned char dmapad2[0x7fff];
  68         volatile unsigned char dma_latch;       /* DMA latch        [0x8000] */
  69 };
  70
  71 struct blz1230II_dma_registers {
  72         volatile unsigned char dma_addr;        /* DMA address      [0x0000] */
  73         unsigned char dmapad2[0xf];
  74         volatile unsigned char dma_latch;       /* DMA latch        [0x0010] */
  75 };
  76
  77 #define BLZ1230_DMA_WRITE 0x80000000
  78
  79 static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
  80 static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
  81 static void dma_dump_state(struct NCR_ESP *esp);
  82 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
  83 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
  84 static void dma_ints_off(struct NCR_ESP *esp);
  85 static void dma_ints_on(struct NCR_ESP *esp);
  86 static int  dma_irq_p(struct NCR_ESP *esp);
  87 static int  dma_ports_p(struct NCR_ESP *esp);
  88 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
  89
  90 static volatile unsigned char cmd_buffer[16];
  91                                 /* This is where all commands are put
  92                                  * before they are transferred to the ESP chip
  93                                  * via PIO.
  94                                  */
  95
  96 /***************************************************************** Detection */
  97 int __init blz1230_esp_detect(Scsi_Host_Template *tpnt)
  98 {
  99         struct NCR_ESP *esp;
 100         struct zorro_dev *z = NULL;
 101         unsigned long address;
 102         struct ESP_regs *eregs;
 103         unsigned long board;
 104
 105 #if MKIV
 106 #define REAL_BLZ1230_ID         ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260
 107 #define REAL_BLZ1230_ESP_ADDR   BLZ1230_ESP_ADDR
 108 #define REAL_BLZ1230_DMA_ADDR   BLZ1230_DMA_ADDR
 109 #else
 110 #define REAL_BLZ1230_ID         ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060
 111 #define REAL_BLZ1230_ESP_ADDR   BLZ1230II_ESP_ADDR
 112 #define REAL_BLZ1230_DMA_ADDR   BLZ1230II_DMA_ADDR
 113 #endif
 114
 115         if ((z = zorro_find_device(REAL_BLZ1230_ID, z))) {
 116             board = z->resource.start;
 117             if (request_mem_region(board+REAL_BLZ1230_ESP_ADDR,
 118                                    sizeof(struct ESP_regs), "NCR53C9x")) {
 119                 /* Do some magic to figure out if the blizzard is
 120                  * equipped with a SCSI controller
 121                  */
 122                 address = ZTWO_VADDR(board);
 123                 eregs = (struct ESP_regs *)(address + REAL_BLZ1230_ESP_ADDR);
 124                 esp = esp_allocate(tpnt, (void *)board+REAL_BLZ1230_ESP_ADDR);
 125
 126                 esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7));
 127                 udelay(5);
 128                 if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7))
 129                         goto err_out;
 130
 131                 /* Do command transfer with programmed I/O */
 132                 esp->do_pio_cmds = 1;
 133
 134                 /* Required functions */
 135                 esp->dma_bytes_sent = &dma_bytes_sent;
 136                 esp->dma_can_transfer = &dma_can_transfer;
 137                 esp->dma_dump_state = &dma_dump_state;
 138                 esp->dma_init_read = &dma_init_read;
 139                 esp->dma_init_write = &dma_init_write;
 140                 esp->dma_ints_off = &dma_ints_off;
 141                 esp->dma_ints_on = &dma_ints_on;
 142                 esp->dma_irq_p = &dma_irq_p;
 143                 esp->dma_ports_p = &dma_ports_p;
 144                 esp->dma_setup = &dma_setup;
 145
 146                 /* Optional functions */
 147                 esp->dma_barrier = 0;
 148                 esp->dma_drain = 0;
 149                 esp->dma_invalidate = 0;
 150                 esp->dma_irq_entry = 0;
 151                 esp->dma_irq_exit = 0;
 152                 esp->dma_led_on = 0;
 153                 esp->dma_led_off = 0;
 154                 esp->dma_poll = 0;
 155                 esp->dma_reset = 0;
 156
 157                 /* SCSI chip speed */
 158                 esp->cfreq = 40000000;
 159
 160                 /* The DMA registers on the Blizzard are mapped
 161                  * relative to the device (i.e. in the same Zorro
 162                  * I/O block).
 163                  */
 164                 esp->dregs = (void *)(address + REAL_BLZ1230_DMA_ADDR);
 165
 166                 /* ESP register base */
 167                 esp->eregs = eregs;
 168
 169                 /* Set the command buffer */
 170                 esp->esp_command = cmd_buffer;
 171                 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
 172
 173                 esp->irq = IRQ_AMIGA_PORTS;
 174                 esp->slot = board+REAL_BLZ1230_ESP_ADDR;
 175                 if (request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
 176                                  "Blizzard 1230 SCSI IV", esp->ehost))
 177                         goto err_out;
 178
 179                 /* Figure out our scsi ID on the bus */
 180                 esp->scsi_id = 7;
 181
 182                 /* We don't have a differential SCSI-bus. */
 183                 esp->diff = 0;
 184
 185                 esp_initialize(esp);
 186
 187                 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
 188                 esps_running = esps_in_use;
 189                 return esps_in_use;
 190             }
 191         }
 192         return 0;
 193
 194  err_out:
 195         scsi_unregister(esp->ehost);
 196         esp_deallocate(esp);
 197         release_mem_region(board+REAL_BLZ1230_ESP_ADDR,
 198                            sizeof(struct ESP_regs));
 199         return 0;
 200 }
 201
 202 /************************************************************* DMA Functions */
 203 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
 204 {
 205         /* Since the Blizzard DMA is fully dedicated to the ESP chip,
 206          * the number of bytes sent (to the ESP chip) equals the number
 207          * of bytes in the FIFO - there is no buffering in the DMA controller.
 208          * XXXX Do I read this right? It is from host to ESP, right?
 209          */
 210         return fifo_count;
 211 }
 212
 213 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
 214 {
 215         /* I don't think there's any limit on the Blizzard DMA. So we use what
 216          * the ESP chip can handle (24 bit).
 217          */
 218         unsigned long sz = sp->SCp.this_residual;
 219         if(sz > 0x1000000)
 220                 sz = 0x1000000;
 221         return sz;
 222 }
 223
 224 static void dma_dump_state(struct NCR_ESP *esp)
 225 {
 226         ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
 227                 custom.intreqr, custom.intenar));
 228 }
 229
 230 void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
 231 {
 232 #if MKIV
 233         struct blz1230_dma_registers *dregs =
 234                 (struct blz1230_dma_registers *) (esp->dregs);
 235 #else
 236         struct blz1230II_dma_registers *dregs =
 237                 (struct blz1230II_dma_registers *) (esp->dregs);
 238 #endif
 239
 240         cache_clear(addr, length);
 241
 242         addr >>= 1;
 243         addr &= ~(BLZ1230_DMA_WRITE);
 244
 245         /* First set latch */
 246         dregs->dma_latch = (addr >> 24) & 0xff;
 247
 248         /* Then pump the address to the DMA address register */
 249 #if MKIV
 250         dregs->dma_addr = (addr >> 24) & 0xff;
 251 #endif
 252         dregs->dma_addr = (addr >> 16) & 0xff;
 253         dregs->dma_addr = (addr >>  8) & 0xff;
 254         dregs->dma_addr = (addr      ) & 0xff;
 255 }
 256
 257 void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
 258 {
 259 #if MKIV
 260         struct blz1230_dma_registers *dregs =
 261                 (struct blz1230_dma_registers *) (esp->dregs);
 262 #else
 263         struct blz1230II_dma_registers *dregs =
 264                 (struct blz1230II_dma_registers *) (esp->dregs);
 265 #endif
 266
 267         cache_push(addr, length);
 268
 269         addr >>= 1;
 270         addr |= BLZ1230_DMA_WRITE;
 271
 272         /* First set latch */
 273         dregs->dma_latch = (addr >> 24) & 0xff;
 274
 275         /* Then pump the address to the DMA address register */
 276 #if MKIV
 277         dregs->dma_addr = (addr >> 24) & 0xff;
 278 #endif
 279         dregs->dma_addr = (addr >> 16) & 0xff;
 280         dregs->dma_addr = (addr >>  8) & 0xff;
 281         dregs->dma_addr = (addr      ) & 0xff;
 282 }
 283
 284 static void dma_ints_off(struct NCR_ESP *esp)
 285 {
 286         disable_irq(esp->irq);
 287 }
 288
 289 static void dma_ints_on(struct NCR_ESP *esp)
 290 {
 291         enable_irq(esp->irq);
 292 }
 293
 294 static int dma_irq_p(struct NCR_ESP *esp)
 295 {
 296         return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
 297 }
 298
 299 static int dma_ports_p(struct NCR_ESP *esp)
 300 {
 301         return ((custom.intenar) & IF_PORTS);
 302 }
 303
 304 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
 305 {
 306         /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
 307          * so when (write) is true, it actually means READ!
 308          */
 309         if(write){
 310                 dma_init_read(esp, addr, count);
 311         } else {
 312                 dma_init_write(esp, addr, count);
 313         }
 314 }
 315
 316 #define HOSTS_C
 317
 318 int blz1230_esp_release(struct Scsi_Host *instance)
 319 {
 320 #ifdef MODULE
 321         unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
 322         esp_deallocate((struct NCR_ESP *)instance->hostdata);
 323         esp_release();
 324         release_mem_region(address, sizeof(struct ESP_regs));
 325         free_irq(IRQ_AMIGA_PORTS, esp_intr);
 326 #endif
 327         return 1;
 328 }
 329
 330
 331 static Scsi_Host_Template driver_template = {
 332         .proc_name              = "esp-blz1230",
 333         .proc_info              = esp_proc_info,
 334         .name                   = "Blizzard1230 SCSI IV",
 335         .detect                 = blz1230_esp_detect,
 336         .slave_alloc            = esp_slave_alloc,
 337         .slave_destroy          = esp_slave_destroy,
 338         .release                = blz1230_esp_release,
 339         .queuecommand           = esp_queue,
 340         .eh_abort_handler       = esp_abort,
 341         .eh_bus_reset_handler   = esp_reset,
 342         .can_queue              = 7,
 343         .this_id                = 7,
 344         .sg_tablesize           = SG_ALL,
 345         .cmd_per_lun            = 1,
 346         .use_clustering         = ENABLE_CLUSTERING
 347 };
 348
 349
 350 #include "scsi_module.c"
 351
 352 MODULE_LICENSE("GPL");