drivers/scsi/ips.h

   1 /*****************************************************************************/
   2 /* ips.h -- driver for the Adaptec / IBM ServeRAID controller                */
   3 /*                                                                           */
   4 /* Written By: Keith Mitchell, IBM Corporation                               */
   5 /*             Jack Hammer, Adaptec, Inc.                                    */
   6 /*             David Jeffery, Adaptec, Inc.                                  */
   7 /*                                                                           */
   8 /* Copyright (C) 1999 IBM Corporation                                        */
   9 /* Copyright (C) 2003 Adaptec, Inc.                                          */
  10 /*                                                                           */
  11 /* This program is free software; you can redistribute it and/or modify      */
  12 /* it under the terms of the GNU General Public License as published by      */
  13 /* the Free Software Foundation; either version 2 of the License, or         */
  14 /* (at your option) any later version.                                       */
  15 /*                                                                           */
  16 /* This program is distributed in the hope that it will be useful,           */
  17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
  18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             */
  19 /* GNU General Public License for more details.                              */
  20 /*                                                                           */
  21 /* NO WARRANTY                                                               */
  22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR        */
  23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT      */
  24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,      */
  25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is    */
  26 /* solely responsible for determining the appropriateness of using and       */
  27 /* distributing the Program and assumes all risks associated with its        */
  28 /* exercise of rights under this Agreement, including but not limited to     */
  29 /* the risks and costs of program errors, damage to or loss of data,         */
  30 /* programs or equipment, and unavailability or interruption of operations.  */
  31 /*                                                                           */
  32 /* DISCLAIMER OF LIABILITY                                                   */
  33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY   */
  34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL        */
  35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND   */
  36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR     */
  37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE    */
  38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED  */
  39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES             */
  40 /*                                                                           */
  41 /* You should have received a copy of the GNU General Public License         */
  42 /* along with this program; if not, write to the Free Software               */
  43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */
  44 /*                                                                           */
  45 /* Bugs/Comments/Suggestions should be mailed to:                            */
  46 /*      ipslinux@adaptec.com                                                 */
  47 /*                                                                           */
  48 /*****************************************************************************/
  49
  50 #ifndef _IPS_H_
  51    #define _IPS_H_
  52
  53    #include <asm/uaccess.h>
  54    #include <asm/io.h>
  55
  56    /*
  57     * Some handy macros
  58     */
  59    #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) || defined CONFIG_HIGHIO
  60       #define IPS_HIGHIO
  61    #endif
  62
  63    #define IPS_HA(x)                   ((ips_ha_t *) x->hostdata)
  64    #define IPS_COMMAND_ID(ha, scb)     (int) (scb - ha->scbs)
  65    #define IPS_IS_TROMBONE(ha)         (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
  66                                          (ha->revision_id >= IPS_REVID_TROMBONE32) && \
  67                                          (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0)
  68    #define IPS_IS_CLARINET(ha)         (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
  69                                          (ha->revision_id >= IPS_REVID_CLARINETP1) && \
  70                                          (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0)
  71    #define IPS_IS_MORPHEUS(ha)         (ha->device_id == IPS_DEVICEID_MORPHEUS)
  72    #define IPS_IS_MARCO(ha)            (ha->device_id == IPS_DEVICEID_MARCO)
  73    #define IPS_USE_I2O_DELIVER(ha)     ((IPS_IS_MORPHEUS(ha) || \
  74                                          (IPS_IS_TROMBONE(ha) && \
  75                                           (ips_force_i2o))) ? 1 : 0)
  76    #define IPS_USE_MEMIO(ha)           ((IPS_IS_MORPHEUS(ha) || \
  77                                          ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
  78                                           (ips_force_memio))) ? 1 : 0)
  79
  80     #define IPS_HAS_ENH_SGLIST(ha)    (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
  81     #define IPS_USE_ENH_SGLIST(ha)    ((ha)->flags & IPS_HA_ENH_SG)
  82     #define IPS_SGLIST_SIZE(ha)       (IPS_USE_ENH_SGLIST(ha) ? \
  83                                          sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
  84
  85    #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,4)
  86       #define pci_set_dma_mask(dev,mask) ( mask > 0xffffffff ? 1:0 )
  87       #define scsi_set_pci_device(sh,dev) (0)
  88    #endif
  89
  90    #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
  91
  92       #ifndef irqreturn_t
  93          typedef void irqreturn_t;
  94       #endif
  95
  96       #define IRQ_NONE
  97       #define IRQ_HANDLED
  98       #define IRQ_RETVAL(x)
  99       #define IPS_REGISTER_HOSTS(SHT)      scsi_register_module(MODULE_SCSI_HA,SHT)
 100       #define IPS_UNREGISTER_HOSTS(SHT)    scsi_unregister_module(MODULE_SCSI_HA,SHT)
 101       #define IPS_ADD_HOST(shost,device)
 102       #define IPS_REMOVE_HOST(shost)
 103       #define IPS_SCSI_SET_DEVICE(sh,ha)   scsi_set_pci_device(sh, (ha)->pcidev)
 104       #define IPS_PRINTK(level, pcidev, format, arg...)                 \
 105             printk(level "%s %s:" format , "ips" ,     \
 106             (pcidev)->slot_name , ## arg)
 107       #define scsi_host_alloc(sh,size)         scsi_register(sh,size)
 108       #define scsi_host_put(sh)             scsi_unregister(sh)
 109    #else
 110       #define IPS_REGISTER_HOSTS(SHT)      (!ips_detect(SHT))
 111       #define IPS_UNREGISTER_HOSTS(SHT)
 112       #define IPS_ADD_HOST(shost,device)   do { scsi_add_host(shost,device); scsi_scan_host(shost); } while (0)
 113       #define IPS_REMOVE_HOST(shost)       scsi_remove_host(shost)
 114       #define IPS_SCSI_SET_DEVICE(sh,ha)   scsi_set_device(sh, &(ha)->pcidev->dev)
 115       #define IPS_PRINTK(level, pcidev, format, arg...)                 \
 116             dev_printk(level , &((pcidev)->dev) , format , ## arg)
 117    #endif
 118
 119    #ifndef MDELAY
 120       #define MDELAY mdelay
 121    #endif
 122
 123    #ifndef min
 124       #define min(x,y) ((x) < (y) ? x : y)
 125    #endif
 126
 127    #define pci_dma_hi32(a)         ((a >> 16) >> 16)
 128    #define pci_dma_lo32(a)         (a & 0xffffffff)
 129
 130    #if (BITS_PER_LONG > 32) || (defined CONFIG_HIGHMEM64G && defined IPS_HIGHIO)
 131       #define IPS_ENABLE_DMA64        (1)
 132    #else
 133       #define IPS_ENABLE_DMA64        (0)
 134    #endif
 135
 136    /*
 137     * Adapter address map equates
 138     */
 139    #define IPS_REG_HISR                 0x08    /* Host Interrupt Status Reg   */
 140    #define IPS_REG_CCSAR                0x10    /* Cmd Channel System Addr Reg */
 141    #define IPS_REG_CCCR                 0x14    /* Cmd Channel Control Reg     */
 142    #define IPS_REG_SQHR                 0x20    /* Status Q Head Reg           */
 143    #define IPS_REG_SQTR                 0x24    /* Status Q Tail Reg           */
 144    #define IPS_REG_SQER                 0x28    /* Status Q End Reg            */
 145    #define IPS_REG_SQSR                 0x2C    /* Status Q Start Reg          */
 146    #define IPS_REG_SCPR                 0x05    /* Subsystem control port reg  */
 147    #define IPS_REG_ISPR                 0x06    /* interrupt status port reg   */
 148    #define IPS_REG_CBSP                 0x07    /* CBSP register               */
 149    #define IPS_REG_FLAP                 0x18    /* Flash address port          */
 150    #define IPS_REG_FLDP                 0x1C    /* Flash data port             */
 151    #define IPS_REG_NDAE                 0x38    /* Anaconda 64 NDAE Register   */
 152    #define IPS_REG_I2O_INMSGQ           0x40    /* I2O Inbound Message Queue   */
 153    #define IPS_REG_I2O_OUTMSGQ          0x44    /* I2O Outbound Message Queue  */
 154    #define IPS_REG_I2O_HIR              0x30    /* I2O Interrupt Status        */
 155    #define IPS_REG_I960_IDR             0x20    /* i960 Inbound Doorbell       */
 156    #define IPS_REG_I960_MSG0            0x18    /* i960 Outbound Reg 0         */
 157    #define IPS_REG_I960_MSG1            0x1C    /* i960 Outbound Reg 1         */
 158    #define IPS_REG_I960_OIMR            0x34    /* i960 Oubound Int Mask Reg   */
 159
 160    /*
 161     * Adapter register bit equates
 162     */
 163    #define IPS_BIT_GHI                  0x04    /* HISR General Host Interrupt */
 164    #define IPS_BIT_SQO                  0x02    /* HISR Status Q Overflow      */
 165    #define IPS_BIT_SCE                  0x01    /* HISR Status Channel Enqueue */
 166    #define IPS_BIT_SEM                  0x08    /* CCCR Semaphore Bit          */
 167    #define IPS_BIT_ILE                  0x10    /* CCCR ILE Bit                */
 168    #define IPS_BIT_START_CMD            0x101A  /* CCCR Start Command Channel  */
 169    #define IPS_BIT_START_STOP           0x0002  /* CCCR Start/Stop Bit         */
 170    #define IPS_BIT_RST                  0x80    /* SCPR Reset Bit              */
 171    #define IPS_BIT_EBM                  0x02    /* SCPR Enable Bus Master      */
 172    #define IPS_BIT_EI                   0x80    /* HISR Enable Interrupts      */
 173    #define IPS_BIT_OP                   0x01    /* OP bit in CBSP              */
 174    #define IPS_BIT_I2O_OPQI             0x08    /* General Host Interrupt      */
 175    #define IPS_BIT_I960_MSG0I           0x01    /* Message Register 0 Interrupt*/
 176    #define IPS_BIT_I960_MSG1I           0x02    /* Message Register 1 Interrupt*/
 177
 178    /*
 179     * Adapter Command ID Equates
 180     */
 181    #define IPS_CMD_GET_LD_INFO          0x19
 182    #define IPS_CMD_GET_SUBSYS           0x40
 183    #define IPS_CMD_READ_CONF            0x38
 184    #define IPS_CMD_RW_NVRAM_PAGE        0xBC
 185    #define IPS_CMD_READ                 0x02
 186    #define IPS_CMD_WRITE                0x03
 187    #define IPS_CMD_FFDC                 0xD7
 188    #define IPS_CMD_ENQUIRY              0x05
 189    #define IPS_CMD_FLUSH                0x0A
 190    #define IPS_CMD_READ_SG              0x82
 191    #define IPS_CMD_WRITE_SG             0x83
 192    #define IPS_CMD_DCDB                 0x04
 193    #define IPS_CMD_DCDB_SG              0x84
 194    #define IPS_CMD_EXTENDED_DCDB            0x95
 195    #define IPS_CMD_EXTENDED_DCDB_SG         0x96
 196    #define IPS_CMD_CONFIG_SYNC          0x58
 197    #define IPS_CMD_ERROR_TABLE          0x17
 198    #define IPS_CMD_DOWNLOAD             0x20
 199    #define IPS_CMD_RW_BIOSFW            0x22
 200    #define IPS_CMD_GET_VERSION_INFO     0xC6
 201    #define IPS_CMD_RESET_CHANNEL        0x1A
 202
 203    /*
 204     * Adapter Equates
 205     */
 206    #define IPS_CSL                      0xFF
 207    #define IPS_POCL                     0x30
 208    #define IPS_NORM_STATE               0x00
 209    #define IPS_MAX_ADAPTER_TYPES        3
 210    #define IPS_MAX_ADAPTERS             16
 211    #define IPS_MAX_IOCTL                1
 212    #define IPS_MAX_IOCTL_QUEUE          8
 213    #define IPS_MAX_QUEUE                128
 214    #define IPS_BLKSIZE                  512
 215    #define IPS_MAX_SG                   17
 216    #define IPS_MAX_LD                   8
 217    #define IPS_MAX_CHANNELS             4
 218    #define IPS_MAX_TARGETS              15
 219    #define IPS_MAX_CHUNKS               16
 220    #define IPS_MAX_CMDS                 128
 221    #define IPS_MAX_XFER                 0x10000
 222    #define IPS_NVRAM_P5_SIG             0xFFDDBB99
 223    #define IPS_MAX_POST_BYTES           0x02
 224    #define IPS_MAX_CONFIG_BYTES         0x02
 225    #define IPS_GOOD_POST_STATUS         0x80
 226    #define IPS_SEM_TIMEOUT              2000
 227    #define IPS_IOCTL_COMMAND            0x0D
 228    #define IPS_INTR_ON                  0
 229    #define IPS_INTR_IORL                1
 230    #define IPS_FFDC                     99
 231    #define IPS_ADAPTER_ID               0xF
 232    #define IPS_VENDORID_IBM             0x1014
 233    #define IPS_VENDORID_ADAPTEC         0x9005
 234    #define IPS_DEVICEID_COPPERHEAD      0x002E
 235    #define IPS_DEVICEID_MORPHEUS        0x01BD
 236    #define IPS_DEVICEID_MARCO           0x0250
 237    #define IPS_SUBDEVICEID_4M           0x01BE
 238    #define IPS_SUBDEVICEID_4L           0x01BF
 239    #define IPS_SUBDEVICEID_4MX          0x0208
 240    #define IPS_SUBDEVICEID_4LX          0x020E
 241    #define IPS_SUBDEVICEID_5I2          0x0259
 242    #define IPS_SUBDEVICEID_5I1          0x0258
 243    #define IPS_SUBDEVICEID_6M           0x0279
 244    #define IPS_SUBDEVICEID_6I           0x028C
 245    #define IPS_SUBDEVICEID_7k           0x028E
 246    #define IPS_SUBDEVICEID_7M           0x028F
 247    #define IPS_IOCTL_SIZE               8192
 248    #define IPS_STATUS_SIZE              4
 249    #define IPS_STATUS_Q_SIZE            (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
 250    #define IPS_IMAGE_SIZE               500 * 1024
 251    #define IPS_MEMMAP_SIZE              128
 252    #define IPS_ONE_MSEC                 1
 253    #define IPS_ONE_SEC                  1000
 254
 255    /*
 256     * Geometry Settings
 257     */
 258    #define IPS_COMP_HEADS               128
 259    #define IPS_COMP_SECTORS             32
 260    #define IPS_NORM_HEADS               254
 261    #define IPS_NORM_SECTORS             63
 262
 263    /*
 264     * Adapter Basic Status Codes
 265     */
 266    #define IPS_BASIC_STATUS_MASK        0xFF
 267    #define IPS_GSC_STATUS_MASK          0x0F
 268    #define IPS_CMD_SUCCESS              0x00
 269    #define IPS_CMD_RECOVERED_ERROR      0x01
 270    #define IPS_INVAL_OPCO               0x03
 271    #define IPS_INVAL_CMD_BLK            0x04
 272    #define IPS_INVAL_PARM_BLK           0x05
 273    #define IPS_BUSY                     0x08
 274    #define IPS_CMD_CMPLT_WERROR         0x0C
 275    #define IPS_LD_ERROR                 0x0D
 276    #define IPS_CMD_TIMEOUT              0x0E
 277    #define IPS_PHYS_DRV_ERROR           0x0F
 278
 279    /*
 280     * Adapter Extended Status Equates
 281     */
 282    #define IPS_ERR_SEL_TO               0xF0
 283    #define IPS_ERR_OU_RUN               0xF2
 284    #define IPS_ERR_HOST_RESET           0xF7
 285    #define IPS_ERR_DEV_RESET            0xF8
 286    #define IPS_ERR_RECOVERY             0xFC
 287    #define IPS_ERR_CKCOND               0xFF
 288
 289    /*
 290     * Operating System Defines
 291     */
 292    #define IPS_OS_WINDOWS_NT            0x01
 293    #define IPS_OS_NETWARE               0x02
 294    #define IPS_OS_OPENSERVER            0x03
 295    #define IPS_OS_UNIXWARE              0x04
 296    #define IPS_OS_SOLARIS               0x05
 297    #define IPS_OS_OS2                   0x06
 298    #define IPS_OS_LINUX                 0x07
 299    #define IPS_OS_FREEBSD               0x08
 300
 301    /*
 302     * Adapter Revision ID's
 303     */
 304    #define IPS_REVID_SERVERAID          0x02
 305    #define IPS_REVID_NAVAJO             0x03
 306    #define IPS_REVID_SERVERAID2         0x04
 307    #define IPS_REVID_CLARINETP1         0x05
 308    #define IPS_REVID_CLARINETP2         0x07
 309    #define IPS_REVID_CLARINETP3         0x0D
 310    #define IPS_REVID_TROMBONE32         0x0F
 311    #define IPS_REVID_TROMBONE64         0x10
 312
 313    /*
 314     * NVRAM Page 5 Adapter Defines
 315     */
 316    #define IPS_ADTYPE_SERVERAID         0x01
 317    #define IPS_ADTYPE_SERVERAID2        0x02
 318    #define IPS_ADTYPE_NAVAJO            0x03
 319    #define IPS_ADTYPE_KIOWA             0x04
 320    #define IPS_ADTYPE_SERVERAID3        0x05
 321    #define IPS_ADTYPE_SERVERAID3L       0x06
 322    #define IPS_ADTYPE_SERVERAID4H       0x07
 323    #define IPS_ADTYPE_SERVERAID4M       0x08
 324    #define IPS_ADTYPE_SERVERAID4L       0x09
 325    #define IPS_ADTYPE_SERVERAID4MX      0x0A
 326    #define IPS_ADTYPE_SERVERAID4LX      0x0B
 327    #define IPS_ADTYPE_SERVERAID5I2      0x0C
 328    #define IPS_ADTYPE_SERVERAID5I1      0x0D
 329    #define IPS_ADTYPE_SERVERAID6M       0x0E
 330    #define IPS_ADTYPE_SERVERAID6I       0x0F
 331    #define IPS_ADTYPE_SERVERAID7t       0x10
 332    #define IPS_ADTYPE_SERVERAID7k       0x11
 333    #define IPS_ADTYPE_SERVERAID7M       0x12
 334
 335    /*
 336     * Adapter Command/Status Packet Definitions
 337     */
 338    #define IPS_SUCCESS                  0x01 /* Successfully completed       */
 339    #define IPS_SUCCESS_IMM              0x02 /* Success - Immediately        */
 340    #define IPS_FAILURE                  0x04 /* Completed with Error         */
 341
 342    /*
 343     * Logical Drive Equates
 344     */
 345    #define IPS_LD_OFFLINE               0x02
 346    #define IPS_LD_OKAY                  0x03
 347    #define IPS_LD_FREE                  0x00
 348    #define IPS_LD_SYS                   0x06
 349    #define IPS_LD_CRS                   0x24
 350
 351    /*
 352     * DCDB Table Equates
 353     */
 354    #define IPS_NO_DISCONNECT            0x00
 355    #define IPS_DISCONNECT_ALLOWED       0x80
 356    #define IPS_NO_AUTO_REQSEN           0x40
 357    #define IPS_DATA_NONE                0x00
 358    #define IPS_DATA_UNK                 0x00
 359    #define IPS_DATA_IN                  0x01
 360    #define IPS_DATA_OUT                 0x02
 361    #define IPS_TRANSFER64K              0x08
 362    #define IPS_NOTIMEOUT                0x00
 363    #define IPS_TIMEOUT10                0x10
 364    #define IPS_TIMEOUT60                0x20
 365    #define IPS_TIMEOUT20M               0x30
 366
 367    /*
 368     * SCSI Inquiry Data Flags
 369     */
 370    #define IPS_SCSI_INQ_TYPE_DASD       0x00
 371    #define IPS_SCSI_INQ_TYPE_PROCESSOR  0x03
 372    #define IPS_SCSI_INQ_LU_CONNECTED    0x00
 373    #define IPS_SCSI_INQ_RD_REV2         0x02
 374    #define IPS_SCSI_INQ_REV2            0x02
 375    #define IPS_SCSI_INQ_REV3            0x03
 376    #define IPS_SCSI_INQ_Address16       0x01
 377    #define IPS_SCSI_INQ_Address32       0x02
 378    #define IPS_SCSI_INQ_MedChanger      0x08
 379    #define IPS_SCSI_INQ_MultiPort       0x10
 380    #define IPS_SCSI_INQ_EncServ         0x40
 381    #define IPS_SCSI_INQ_SoftReset       0x01
 382    #define IPS_SCSI_INQ_CmdQue          0x02
 383    #define IPS_SCSI_INQ_Linked          0x08
 384    #define IPS_SCSI_INQ_Sync            0x10
 385    #define IPS_SCSI_INQ_WBus16          0x20
 386    #define IPS_SCSI_INQ_WBus32          0x40
 387    #define IPS_SCSI_INQ_RelAdr          0x80
 388
 389    /*
 390     * SCSI Request Sense Data Flags
 391     */
 392    #define IPS_SCSI_REQSEN_VALID        0x80
 393    #define IPS_SCSI_REQSEN_CURRENT_ERR  0x70
 394    #define IPS_SCSI_REQSEN_NO_SENSE     0x00
 395
 396    /*
 397     * SCSI Mode Page Equates
 398     */
 399    #define IPS_SCSI_MP3_SoftSector      0x01
 400    #define IPS_SCSI_MP3_HardSector      0x02
 401    #define IPS_SCSI_MP3_Removeable      0x04
 402    #define IPS_SCSI_MP3_AllocateSurface 0x08
 403
 404    /*
 405     * HA Flags
 406     */
 407
 408    #define IPS_HA_ENH_SG                0x1
 409
 410    /*
 411     * SCB Flags
 412     */
 413    #define IPS_SCB_MAP_SG               0x00008
 414    #define IPS_SCB_MAP_SINGLE           0X00010
 415
 416    /*
 417     * Passthru stuff
 418     */
 419    #define IPS_COPPUSRCMD              (('C'<<8) | 65)
 420    #define IPS_COPPIOCCMD              (('C'<<8) | 66)
 421    #define IPS_NUMCTRLS                (('C'<<8) | 68)
 422    #define IPS_CTRLINFO                (('C'<<8) | 69)
 423
 424    /* flashing defines */
 425    #define IPS_FW_IMAGE                0x00
 426    #define IPS_BIOS_IMAGE              0x01
 427    #define IPS_WRITE_FW                0x01
 428    #define IPS_WRITE_BIOS              0x02
 429    #define IPS_ERASE_BIOS              0x03
 430    #define IPS_BIOS_HEADER             0xC0
 431
 432    /* time oriented stuff */
 433    #define IPS_IS_LEAP_YEAR(y)           (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
 434    #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
 435
 436    #define IPS_SECS_MIN                 60
 437    #define IPS_SECS_HOUR                3600
 438    #define IPS_SECS_8HOURS              28800
 439    #define IPS_SECS_DAY                 86400
 440    #define IPS_DAYS_NORMAL_YEAR         365
 441    #define IPS_DAYS_LEAP_YEAR           366
 442    #define IPS_EPOCH_YEAR               1970
 443
 444    /*
 445     * Scsi_Host Template
 446     */
 447 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 448    static int ips_proc24_info(char *, char **, off_t, int, int, int);
 449    static void ips_select_queue_depth(struct Scsi_Host *, Scsi_Device *);
 450    static int ips_biosparam(Disk *disk, kdev_t dev, int geom[]);
 451 #else
 452    static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
 453    static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
 454                 sector_t capacity, int geom[]);
 455    static int ips_slave_configure(Scsi_Device *SDptr);
 456 #endif
 457
 458 /*
 459  * Raid Command Formats
 460  */
 461 typedef struct {
 462    uint8_t  op_code;
 463    uint8_t  command_id;
 464    uint8_t  log_drv;
 465    uint8_t  sg_count;
 466    uint32_t lba;
 467    uint32_t sg_addr;
 468    uint16_t sector_count;
 469    uint8_t  segment_4G;
 470    uint8_t  enhanced_sg;
 471    uint32_t ccsar;
 472    uint32_t cccr;
 473 } IPS_IO_CMD, *PIPS_IO_CMD;
 474
 475 typedef struct {
 476    uint8_t  op_code;
 477    uint8_t  command_id;
 478    uint16_t reserved;
 479    uint32_t reserved2;
 480    uint32_t buffer_addr;
 481    uint32_t reserved3;
 482    uint32_t ccsar;
 483    uint32_t cccr;
 484 } IPS_LD_CMD, *PIPS_LD_CMD;
 485
 486 typedef struct {
 487    uint8_t  op_code;
 488    uint8_t  command_id;
 489    uint8_t  reserved;
 490    uint8_t  reserved2;
 491    uint32_t reserved3;
 492    uint32_t buffer_addr;
 493    uint32_t reserved4;
 494 } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
 495
 496 typedef struct {
 497    uint8_t  op_code;
 498    uint8_t  command_id;
 499    uint8_t  channel;
 500    uint8_t  reserved3;
 501    uint8_t  reserved4;
 502    uint8_t  reserved5;
 503    uint8_t  reserved6;
 504    uint8_t  reserved7;
 505    uint8_t  reserved8;
 506    uint8_t  reserved9;
 507    uint8_t  reserved10;
 508    uint8_t  reserved11;
 509    uint8_t  reserved12;
 510    uint8_t  reserved13;
 511    uint8_t  reserved14;
 512    uint8_t  adapter_flag;
 513 } IPS_RESET_CMD, *PIPS_RESET_CMD;
 514
 515 typedef struct {
 516    uint8_t  op_code;
 517    uint8_t  command_id;
 518    uint16_t reserved;
 519    uint32_t reserved2;
 520    uint32_t dcdb_address;
 521    uint16_t reserved3;
 522    uint8_t  segment_4G;
 523    uint8_t  enhanced_sg;
 524    uint32_t ccsar;
 525    uint32_t cccr;
 526 } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
 527
 528 typedef struct {
 529    uint8_t  op_code;
 530    uint8_t  command_id;
 531    uint8_t  channel;
 532    uint8_t  source_target;
 533    uint32_t reserved;
 534    uint32_t reserved2;
 535    uint32_t reserved3;
 536    uint32_t ccsar;
 537    uint32_t cccr;
 538 } IPS_CS_CMD, *PIPS_CS_CMD;
 539
 540 typedef struct {
 541    uint8_t  op_code;
 542    uint8_t  command_id;
 543    uint8_t  log_drv;
 544    uint8_t  control;
 545    uint32_t reserved;
 546    uint32_t reserved2;
 547    uint32_t reserved3;
 548    uint32_t ccsar;
 549    uint32_t cccr;
 550 } IPS_US_CMD, *PIPS_US_CMD;
 551
 552 typedef struct {
 553    uint8_t  op_code;
 554    uint8_t  command_id;
 555    uint8_t  reserved;
 556    uint8_t  state;
 557    uint32_t reserved2;
 558    uint32_t reserved3;
 559    uint32_t reserved4;
 560    uint32_t ccsar;
 561    uint32_t cccr;
 562 } IPS_FC_CMD, *PIPS_FC_CMD;
 563
 564 typedef struct {
 565    uint8_t  op_code;
 566    uint8_t  command_id;
 567    uint8_t  reserved;
 568    uint8_t  desc;
 569    uint32_t reserved2;
 570    uint32_t buffer_addr;
 571    uint32_t reserved3;
 572    uint32_t ccsar;
 573    uint32_t cccr;
 574 } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
 575
 576 typedef struct {
 577    uint8_t  op_code;
 578    uint8_t  command_id;
 579    uint8_t  page;
 580    uint8_t  write;
 581    uint32_t reserved;
 582    uint32_t buffer_addr;
 583    uint32_t reserved2;
 584    uint32_t ccsar;
 585    uint32_t cccr;
 586 } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
 587
 588 typedef struct
 589 {
 590     uint8_t  op_code;
 591     uint8_t  command_id;
 592     uint16_t reserved;
 593     uint32_t count;
 594     uint32_t buffer_addr;
 595     uint32_t reserved2;
 596 } IPS_VERSION_INFO, *PIPS_VERSION_INFO;
 597
 598 typedef struct {
 599    uint8_t  op_code;
 600    uint8_t  command_id;
 601    uint8_t  reset_count;
 602    uint8_t  reset_type;
 603    uint8_t  second;
 604    uint8_t  minute;
 605    uint8_t  hour;
 606    uint8_t  day;
 607    uint8_t  reserved1[4];
 608    uint8_t  month;
 609    uint8_t  yearH;
 610    uint8_t  yearL;
 611    uint8_t  reserved2;
 612 } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
 613
 614 typedef struct {
 615    uint8_t  op_code;
 616    uint8_t  command_id;
 617    uint8_t  type;
 618    uint8_t  direction;
 619    uint32_t count;
 620    uint32_t buffer_addr;
 621    uint8_t  total_packets;
 622    uint8_t  packet_num;
 623    uint16_t reserved;
 624 } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
 625
 626 typedef struct {
 627    uint8_t  op_code;
 628    uint8_t  command_id;
 629    uint8_t  type;
 630    uint8_t  direction;
 631    uint32_t count;
 632    uint32_t buffer_addr;
 633    uint32_t offset;
 634 } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
 635
 636 typedef union {
 637    IPS_IO_CMD         basic_io;
 638    IPS_LD_CMD         logical_info;
 639    IPS_IOCTL_CMD      ioctl_info;
 640    IPS_DCDB_CMD       dcdb;
 641    IPS_CS_CMD         config_sync;
 642    IPS_US_CMD         unlock_stripe;
 643    IPS_FC_CMD         flush_cache;
 644    IPS_STATUS_CMD     status;
 645    IPS_NVRAM_CMD      nvram;
 646    IPS_FFDC_CMD       ffdc;
 647    IPS_FLASHFW_CMD    flashfw;
 648    IPS_FLASHBIOS_CMD  flashbios;
 649    IPS_VERSION_INFO   version_info;
 650    IPS_RESET_CMD      reset;
 651 } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
 652
 653 typedef struct {
 654    uint8_t  logical_id;
 655    uint8_t  reserved;
 656    uint8_t  raid_level;
 657    uint8_t  state;
 658    uint32_t sector_count;
 659 } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
 660
 661 typedef struct {
 662    uint8_t       no_of_log_drive;
 663    uint8_t       reserved[3];
 664    IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
 665 } IPS_LD_INFO, *PIPS_LD_INFO;
 666
 667 typedef struct {
 668    uint8_t   device_address;
 669    uint8_t   cmd_attribute;
 670    uint16_t  transfer_length;
 671    uint32_t  buffer_pointer;
 672    uint8_t   cdb_length;
 673    uint8_t   sense_length;
 674    uint8_t   sg_count;
 675    uint8_t   reserved;
 676    uint8_t   scsi_cdb[12];
 677    uint8_t   sense_info[64];
 678    uint8_t   scsi_status;
 679    uint8_t   reserved2[3];
 680 } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
 681
 682 typedef struct {
 683    uint8_t   device_address;
 684    uint8_t   cmd_attribute;
 685    uint8_t   cdb_length;
 686    uint8_t   reserved_for_LUN;
 687    uint32_t  transfer_length;
 688    uint32_t  buffer_pointer;
 689    uint16_t  sg_count;
 690    uint8_t   sense_length;
 691    uint8_t   scsi_status;
 692    uint32_t  reserved;
 693    uint8_t   scsi_cdb[16];
 694    uint8_t   sense_info[56];
 695 } IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
 696
 697 typedef union {
 698    struct {
 699       volatile uint8_t  reserved;
 700       volatile uint8_t  command_id;
 701       volatile uint8_t  basic_status;
 702       volatile uint8_t  extended_status;
 703    } fields;
 704
 705    volatile uint32_t    value;
 706 } IPS_STATUS, *PIPS_STATUS;
 707
 708 typedef struct {
 709    IPS_STATUS           status[IPS_MAX_CMDS + 1];
 710    volatile PIPS_STATUS p_status_start;
 711    volatile PIPS_STATUS p_status_end;
 712    volatile PIPS_STATUS p_status_tail;
 713    volatile uint32_t    hw_status_start;
 714    volatile uint32_t    hw_status_tail;
 715 } IPS_ADAPTER, *PIPS_ADAPTER;
 716
 717 typedef struct {
 718    uint8_t  ucLogDriveCount;
 719    uint8_t  ucMiscFlag;
 720    uint8_t  ucSLTFlag;
 721    uint8_t  ucBSTFlag;
 722    uint8_t  ucPwrChgCnt;
 723    uint8_t  ucWrongAdrCnt;
 724    uint8_t  ucUnidentCnt;
 725    uint8_t  ucNVramDevChgCnt;
 726    uint8_t  CodeBlkVersion[8];
 727    uint8_t  BootBlkVersion[8];
 728    uint32_t ulDriveSize[IPS_MAX_LD];
 729    uint8_t  ucConcurrentCmdCount;
 730    uint8_t  ucMaxPhysicalDevices;
 731    uint16_t usFlashRepgmCount;
 732    uint8_t  ucDefunctDiskCount;
 733    uint8_t  ucRebuildFlag;
 734    uint8_t  ucOfflineLogDrvCount;
 735    uint8_t  ucCriticalDrvCount;
 736    uint16_t usConfigUpdateCount;
 737    uint8_t  ucBlkFlag;
 738    uint8_t  reserved;
 739    uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
 740 } IPS_ENQ, *PIPS_ENQ;
 741
 742 typedef struct {
 743    uint8_t  ucInitiator;
 744    uint8_t  ucParameters;
 745    uint8_t  ucMiscFlag;
 746    uint8_t  ucState;
 747    uint32_t ulBlockCount;
 748    uint8_t  ucDeviceId[28];
 749 } IPS_DEVSTATE, *PIPS_DEVSTATE;
 750
 751 typedef struct {
 752    uint8_t  ucChn;
 753    uint8_t  ucTgt;
 754    uint16_t ucReserved;
 755    uint32_t ulStartSect;
 756    uint32_t ulNoOfSects;
 757 } IPS_CHUNK, *PIPS_CHUNK;
 758
 759 typedef struct {
 760    uint16_t ucUserField;
 761    uint8_t  ucState;
 762    uint8_t  ucRaidCacheParam;
 763    uint8_t  ucNoOfChunkUnits;
 764    uint8_t  ucStripeSize;
 765    uint8_t  ucParams;
 766    uint8_t  ucReserved;
 767    uint32_t ulLogDrvSize;
 768    IPS_CHUNK chunk[IPS_MAX_CHUNKS];
 769 } IPS_LD, *PIPS_LD;
 770
 771 typedef struct {
 772    uint8_t  board_disc[8];
 773    uint8_t  processor[8];
 774    uint8_t  ucNoChanType;
 775    uint8_t  ucNoHostIntType;
 776    uint8_t  ucCompression;
 777    uint8_t  ucNvramType;
 778    uint32_t ulNvramSize;
 779 } IPS_HARDWARE, *PIPS_HARDWARE;
 780
 781 typedef struct {
 782    uint8_t        ucLogDriveCount;
 783    uint8_t        ucDateD;
 784    uint8_t        ucDateM;
 785    uint8_t        ucDateY;
 786    uint8_t        init_id[4];
 787    uint8_t        host_id[12];
 788    uint8_t        time_sign[8];
 789    uint32_t       UserOpt;
 790    uint16_t       user_field;
 791    uint8_t        ucRebuildRate;
 792    uint8_t        ucReserve;
 793    IPS_HARDWARE   hardware_disc;
 794    IPS_LD         logical_drive[IPS_MAX_LD];
 795    IPS_DEVSTATE   dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
 796    uint8_t        reserved[512];
 797 } IPS_CONF, *PIPS_CONF;
 798
 799 typedef struct {
 800    uint32_t  signature;
 801    uint8_t   reserved1;
 802    uint8_t   adapter_slot;
 803    uint16_t  adapter_type;
 804    uint8_t   ctrl_bios[8];
 805    uint8_t   versioning;                   /* 1 = Versioning Supported, else 0 */
 806    uint8_t   version_mismatch;             /* 1 = Versioning MisMatch,  else 0 */
 807    uint8_t   reserved2;
 808    uint8_t   operating_system;
 809    uint8_t   driver_high[4];
 810    uint8_t   driver_low[4];
 811    uint8_t   BiosCompatibilityID[8];
 812    uint8_t   ReservedForOS2[8];
 813    uint8_t   bios_high[4];                 /* Adapter's Flashed BIOS Version   */
 814    uint8_t   bios_low[4];
 815    uint8_t   adapter_order[16];            /* BIOS Telling us the Sort Order   */
 816    uint8_t   Filler[60];
 817 } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
 818
 819 /*--------------------------------------------------------------------------*/
 820 /* Data returned from a GetVersion Command                                  */
 821 /*--------------------------------------------------------------------------*/
 822
 823                                              /* SubSystem Parameter[4]      */
 824 #define  IPS_GET_VERSION_SUPPORT 0x00018000  /* Mask for Versioning Support */
 825
 826 typedef struct
 827 {
 828    uint32_t  revision;
 829    uint8_t   bootBlkVersion[32];
 830    uint8_t   bootBlkAttributes[4];
 831    uint8_t   codeBlkVersion[32];
 832    uint8_t   biosVersion[32];
 833    uint8_t   biosAttributes[4];
 834    uint8_t   compatibilityId[32];
 835    uint8_t   reserved[4];
 836 } IPS_VERSION_DATA;
 837
 838
 839 typedef struct _IPS_SUBSYS {
 840    uint32_t  param[128];
 841 } IPS_SUBSYS, *PIPS_SUBSYS;
 842
 843 /**
 844  ** SCSI Structures
 845  **/
 846
 847 /*
 848  * Inquiry Data Format
 849  */
 850 typedef struct {
 851    uint8_t   DeviceType;
 852    uint8_t   DeviceTypeQualifier;
 853    uint8_t   Version;
 854    uint8_t   ResponseDataFormat;
 855    uint8_t   AdditionalLength;
 856    uint8_t   Reserved;
 857    uint8_t   Flags[2];
 858    uint8_t   VendorId[8];
 859    uint8_t   ProductId[16];
 860    uint8_t   ProductRevisionLevel[4];
 861    uint8_t   Reserved2;                                  /* Provides NULL terminator to name */
 862 } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
 863
 864 /*
 865  * Read Capacity Data Format
 866  */
 867 typedef struct {
 868    uint32_t lba;
 869    uint32_t len;
 870 } IPS_SCSI_CAPACITY;
 871
 872 /*
 873  * Request Sense Data Format
 874  */
 875 typedef struct {
 876    uint8_t  ResponseCode;
 877    uint8_t  SegmentNumber;
 878    uint8_t  Flags;
 879    uint8_t  Information[4];
 880    uint8_t  AdditionalLength;
 881    uint8_t  CommandSpecific[4];
 882    uint8_t  AdditionalSenseCode;
 883    uint8_t  AdditionalSenseCodeQual;
 884    uint8_t  FRUCode;
 885    uint8_t  SenseKeySpecific[3];
 886 } IPS_SCSI_REQSEN;
 887
 888 /*
 889  * Sense Data Format - Page 3
 890  */
 891 typedef struct {
 892    uint8_t  PageCode;
 893    uint8_t  PageLength;
 894    uint16_t TracksPerZone;
 895    uint16_t AltSectorsPerZone;
 896    uint16_t AltTracksPerZone;
 897    uint16_t AltTracksPerVolume;
 898    uint16_t SectorsPerTrack;
 899    uint16_t BytesPerSector;
 900    uint16_t Interleave;
 901    uint16_t TrackSkew;
 902    uint16_t CylinderSkew;
 903    uint8_t  flags;
 904    uint8_t  reserved[3];
 905 } IPS_SCSI_MODE_PAGE3;
 906
 907 /*
 908  * Sense Data Format - Page 4
 909  */
 910 typedef struct {
 911    uint8_t  PageCode;
 912    uint8_t  PageLength;
 913    uint16_t CylindersHigh;
 914    uint8_t  CylindersLow;
 915    uint8_t  Heads;
 916    uint16_t WritePrecompHigh;
 917    uint8_t  WritePrecompLow;
 918    uint16_t ReducedWriteCurrentHigh;
 919    uint8_t  ReducedWriteCurrentLow;
 920    uint16_t StepRate;
 921    uint16_t LandingZoneHigh;
 922    uint8_t  LandingZoneLow;
 923    uint8_t  flags;
 924    uint8_t  RotationalOffset;
 925    uint8_t  Reserved;
 926    uint16_t MediumRotationRate;
 927    uint8_t  Reserved2[2];
 928 } IPS_SCSI_MODE_PAGE4;
 929
 930 /*
 931  * Sense Data Format - Page 8
 932  */
 933 typedef struct {
 934    uint8_t  PageCode;
 935    uint8_t  PageLength;
 936    uint8_t  flags;
 937    uint8_t  RetentPrio;
 938    uint16_t DisPrefetchLen;
 939    uint16_t MinPrefetchLen;
 940    uint16_t MaxPrefetchLen;
 941    uint16_t MaxPrefetchCeiling;
 942 } IPS_SCSI_MODE_PAGE8;
 943
 944 /*
 945  * Sense Data Format - Block Descriptor (DASD)
 946  */
 947 typedef struct {
 948    uint32_t NumberOfBlocks;
 949    uint8_t  DensityCode;
 950    uint16_t BlockLengthHigh;
 951    uint8_t  BlockLengthLow;
 952 } IPS_SCSI_MODE_PAGE_BLKDESC;
 953
 954 /*
 955  * Sense Data Format - Mode Page Header
 956  */
 957 typedef struct {
 958    uint8_t  DataLength;
 959    uint8_t  MediumType;
 960    uint8_t  Reserved;
 961    uint8_t  BlockDescLength;
 962 } IPS_SCSI_MODE_PAGE_HEADER;
 963
 964 typedef struct {
 965    IPS_SCSI_MODE_PAGE_HEADER  hdr;
 966    IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
 967
 968    union {
 969       IPS_SCSI_MODE_PAGE3 pg3;
 970       IPS_SCSI_MODE_PAGE4 pg4;
 971       IPS_SCSI_MODE_PAGE8 pg8;
 972    } pdata;
 973 } IPS_SCSI_MODE_PAGE_DATA;
 974
 975 /*
 976  * Scatter Gather list format
 977  */
 978 typedef struct ips_sglist {
 979    uint32_t address;
 980    uint32_t length;
 981 } IPS_STD_SG_LIST;
 982
 983 typedef struct ips_enh_sglist {
 984    uint32_t address_lo;
 985    uint32_t address_hi;
 986    uint32_t length;
 987    uint32_t reserved;
 988 } IPS_ENH_SG_LIST;
 989
 990 typedef union {
 991    void             *list;
 992    IPS_STD_SG_LIST  *std_list;
 993    IPS_ENH_SG_LIST  *enh_list;
 994 } IPS_SG_LIST;
 995
 996 typedef struct _IPS_INFOSTR {
 997    char *buffer;
 998    int   length;
 999    int   offset;
1000    int   pos;
1001    int   localpos;
1002 } IPS_INFOSTR;
1003
1004 typedef struct {
1005    char *option_name;
1006    int  *option_flag;
1007    int   option_value;
1008 } IPS_OPTION;
1009
1010 /*
1011  * Status Info
1012  */
1013 typedef struct ips_stat {
1014    uint32_t residue_len;
1015    void     *scb_addr;
1016    uint8_t  padding[12 - sizeof(void *)];
1017 } ips_stat_t;
1018
1019 /*
1020  * SCB Queue Format
1021  */
1022 typedef struct ips_scb_queue {
1023    struct ips_scb *head;
1024    struct ips_scb *tail;
1025    int             count;
1026 } ips_scb_queue_t;
1027
1028 /*
1029  * Wait queue_format
1030  */
1031 typedef struct ips_wait_queue {
1032    Scsi_Cmnd      *head;
1033    Scsi_Cmnd      *tail;
1034    int             count;
1035 } ips_wait_queue_t;
1036
1037 typedef struct ips_copp_wait_item {
1038    Scsi_Cmnd                 *scsi_cmd;
1039    struct ips_copp_wait_item *next;
1040 } ips_copp_wait_item_t;
1041
1042 typedef struct ips_copp_queue {
1043    struct ips_copp_wait_item *head;
1044    struct ips_copp_wait_item *tail;
1045    int                        count;
1046 } ips_copp_queue_t;
1047
1048 /* forward decl for host structure */
1049 struct ips_ha;
1050
1051 typedef struct {
1052    int       (*reset)(struct ips_ha *);
1053    int       (*issue)(struct ips_ha *, struct ips_scb *);
1054    int       (*isinit)(struct ips_ha *);
1055    int       (*isintr)(struct ips_ha *);
1056    int       (*init)(struct ips_ha *);
1057    int       (*erasebios)(struct ips_ha *);
1058    int       (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
1059    int       (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
1060    void      (*statinit)(struct ips_ha *);
1061    int       (*intr)(struct ips_ha *);
1062    void      (*enableint)(struct ips_ha *);
1063    uint32_t (*statupd)(struct ips_ha *);
1064 } ips_hw_func_t;
1065
1066 typedef struct ips_ha {
1067    uint8_t            ha_id[IPS_MAX_CHANNELS+1];
1068    uint32_t           dcdb_active[IPS_MAX_CHANNELS];
1069    uint32_t           io_addr;            /* Base I/O address           */
1070    uint8_t            irq;                /* IRQ for adapter            */
1071    uint8_t            ntargets;           /* Number of targets          */
1072    uint8_t            nbus;               /* Number of buses            */
1073    uint8_t            nlun;               /* Number of Luns             */
1074    uint16_t           ad_type;            /* Adapter type               */
1075    uint16_t           host_num;           /* Adapter number             */
1076    uint32_t           max_xfer;           /* Maximum Xfer size          */
1077    uint32_t           max_cmds;           /* Max concurrent commands    */
1078    uint32_t           num_ioctl;          /* Number of Ioctls           */
1079    ips_stat_t         sp;                 /* Status packer pointer      */
1080    struct ips_scb    *scbs;               /* Array of all CCBS          */
1081    struct ips_scb    *scb_freelist;       /* SCB free list              */
1082    ips_wait_queue_t   scb_waitlist;       /* Pending SCB list           */
1083    ips_copp_queue_t   copp_waitlist;      /* Pending PT list            */
1084    ips_scb_queue_t    scb_activelist;     /* Active SCB list            */
1085    IPS_IO_CMD        *dummy;              /* dummy command              */
1086    IPS_ADAPTER       *adapt;              /* Adapter status area        */
1087    IPS_LD_INFO       *logical_drive_info; /* Adapter Logical Drive Info */
1088    dma_addr_t         logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
1089    IPS_ENQ           *enq;                /* Adapter Enquiry data       */
1090    IPS_CONF          *conf;               /* Adapter config data        */
1091    IPS_NVRAM_P5      *nvram;              /* NVRAM page 5 data          */
1092    IPS_SUBSYS        *subsys;             /* Subsystem parameters       */
1093    char              *ioctl_data;         /* IOCTL data area            */
1094    uint32_t           ioctl_datasize;     /* IOCTL data size            */
1095    uint32_t           cmd_in_progress;    /* Current command in progress*/
1096    int                flags;              /*                            */
1097    uint8_t            waitflag;           /* are we waiting for cmd     */
1098    uint8_t            active;
1099    int                ioctl_reset;        /* IOCTL Requested Reset Flag */
1100    uint16_t           reset_count;        /* number of resets           */
1101    time_t             last_ffdc;          /* last time we sent ffdc info*/
1102    uint8_t            revision_id;        /* Revision level             */
1103    uint16_t           device_id;          /* PCI device ID              */
1104    uint8_t            slot_num;           /* PCI Slot Number            */
1105    uint16_t           subdevice_id;       /* Subsystem device ID        */
1106    int                ioctl_len;          /* size of ioctl buffer       */
1107    dma_addr_t         ioctl_busaddr;      /* dma address of ioctl buffer*/
1108    uint8_t            bios_version[8];    /* BIOS Revision              */
1109    uint32_t           mem_addr;           /* Memory mapped address      */
1110    uint32_t           io_len;             /* Size of IO Address         */
1111    uint32_t           mem_len;            /* Size of memory address     */
1112    char              __iomem *mem_ptr;    /* Memory mapped Ptr          */
1113    char              __iomem *ioremap_ptr;/* ioremapped memory pointer  */
1114    ips_hw_func_t      func;               /* hw function pointers       */
1115    struct pci_dev    *pcidev;             /* PCI device handle          */
1116    char              *flash_data;         /* Save Area for flash data   */
1117    int                flash_len;          /* length of flash buffer     */
1118    u32                flash_datasize;     /* Save Area for flash data size */
1119    dma_addr_t         flash_busaddr;      /* dma address of flash buffer*/
1120    dma_addr_t         enq_busaddr;        /* dma address of enq struct  */
1121    uint8_t            requires_esl;       /* Requires an EraseStripeLock */
1122 } ips_ha_t;
1123
1124 typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1125
1126 /*
1127  * SCB Format
1128  */
1129 typedef struct ips_scb {
1130    IPS_HOST_COMMAND  cmd;
1131    IPS_DCDB_TABLE    dcdb;
1132    uint8_t           target_id;
1133    uint8_t           bus;
1134    uint8_t           lun;
1135    uint8_t           cdb[12];
1136    uint32_t          scb_busaddr;
1137    uint32_t          old_data_busaddr;  // Obsolete, but kept for old utility compatibility
1138    uint32_t          timeout;
1139    uint8_t           basic_status;
1140    uint8_t           extended_status;
1141    uint8_t           breakup;
1142    uint8_t           sg_break;
1143    uint32_t          data_len;
1144    uint32_t          sg_len;
1145    uint32_t          flags;
1146    uint32_t          op_code;
1147    IPS_SG_LIST       sg_list;
1148    Scsi_Cmnd        *scsi_cmd;
1149    struct ips_scb   *q_next;
1150    ips_scb_callback  callback;
1151    uint32_t          sg_busaddr;
1152    int               sg_count;
1153    dma_addr_t        data_busaddr;
1154 } ips_scb_t;
1155
1156 typedef struct ips_scb_pt {
1157    IPS_HOST_COMMAND  cmd;
1158    IPS_DCDB_TABLE    dcdb;
1159    uint8_t           target_id;
1160    uint8_t           bus;
1161    uint8_t           lun;
1162    uint8_t           cdb[12];
1163    uint32_t          scb_busaddr;
1164    uint32_t          data_busaddr;
1165    uint32_t          timeout;
1166    uint8_t           basic_status;
1167    uint8_t           extended_status;
1168    uint16_t          breakup;
1169    uint32_t          data_len;
1170    uint32_t          sg_len;
1171    uint32_t          flags;
1172    uint32_t          op_code;
1173    IPS_SG_LIST      *sg_list;
1174    Scsi_Cmnd        *scsi_cmd;
1175    struct ips_scb   *q_next;
1176    ips_scb_callback  callback;
1177 } ips_scb_pt_t;
1178
1179 /*
1180  * Passthru Command Format
1181  */
1182 typedef struct {
1183    uint8_t       CoppID[4];
1184    uint32_t      CoppCmd;
1185    uint32_t      PtBuffer;
1186    uint8_t      *CmdBuffer;
1187    uint32_t      CmdBSize;
1188    ips_scb_pt_t  CoppCP;
1189    uint32_t      TimeOut;
1190    uint8_t       BasicStatus;
1191    uint8_t       ExtendedStatus;
1192    uint8_t       AdapterType;
1193    uint8_t       reserved;
1194 } ips_passthru_t;
1195
1196 #endif
1197
1198 /* The Version Information below gets created by SED during the build process. */
1199 /* Do not modify the next line; it's what SED is looking for to do the insert. */
1200 /* Version Info                                                                */
1201 /*************************************************************************
1202 *
1203 * VERSION.H -- version numbers and copyright notices in various formats
1204 *
1205 *************************************************************************/
1206
1207 #define IPS_VER_MAJOR 7
1208 #define IPS_VER_MAJOR_STRING "7"
1209 #define IPS_VER_MINOR 10
1210 #define IPS_VER_MINOR_STRING "10"
1211 #define IPS_VER_BUILD 18
1212 #define IPS_VER_BUILD_STRING "18"
1213 #define IPS_VER_STRING "7.10.18"
1214 #define IPS_RELEASE_ID 0x00020000
1215 #define IPS_BUILD_IDENT 731
1216 #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1217 #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1218 #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1219 #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1220
1221 /* Version numbers for various adapters */
1222 #define IPS_VER_SERVERAID1 "2.25.01"
1223 #define IPS_VER_SERVERAID2 "2.88.13"
1224 #define IPS_VER_NAVAJO "2.88.13"
1225 #define IPS_VER_SERVERAID3 "6.10.24"
1226 #define IPS_VER_SERVERAID4H "7.10.11"
1227 #define IPS_VER_SERVERAID4MLx "7.10.18"
1228 #define IPS_VER_SARASOTA "7.10.18"
1229 #define IPS_VER_MARCO "7.10.18"
1230 #define IPS_VER_SEBRING "7.10.18"
1231 #define IPS_VER_KEYWEST "7.10.18"
1232
1233 /* Compatability IDs for various adapters */
1234 #define IPS_COMPAT_UNKNOWN ""
1235 #define IPS_COMPAT_CURRENT "KW710"
1236 #define IPS_COMPAT_SERVERAID1 "2.25.01"
1237 #define IPS_COMPAT_SERVERAID2 "2.88.13"
1238 #define IPS_COMPAT_NAVAJO  "2.88.13"
1239 #define IPS_COMPAT_KIOWA "2.88.13"
1240 #define IPS_COMPAT_SERVERAID3H  "SB610"
1241 #define IPS_COMPAT_SERVERAID3L  "SB610"
1242 #define IPS_COMPAT_SERVERAID4H  "KW710"
1243 #define IPS_COMPAT_SERVERAID4M  "KW710"
1244 #define IPS_COMPAT_SERVERAID4L  "KW710"
1245 #define IPS_COMPAT_SERVERAID4Mx "KW710"
1246 #define IPS_COMPAT_SERVERAID4Lx "KW710"
1247 #define IPS_COMPAT_SARASOTA     "KW710"
1248 #define IPS_COMPAT_MARCO        "KW710"
1249 #define IPS_COMPAT_SEBRING      "KW710"
1250 #define IPS_COMPAT_TAMPA        "KW710"
1251 #define IPS_COMPAT_KEYWEST      "KW710"
1252 #define IPS_COMPAT_BIOS "KW710"
1253
1254 #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1255 #define IPS_COMPAT_ID_LENGTH 8
1256
1257 #define IPS_DEFINE_COMPAT_TABLE(tablename) \
1258    char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1259       IPS_COMPAT_UNKNOWN, \
1260       IPS_COMPAT_SERVERAID1, \
1261       IPS_COMPAT_SERVERAID2, \
1262       IPS_COMPAT_NAVAJO, \
1263       IPS_COMPAT_KIOWA, \
1264       IPS_COMPAT_SERVERAID3H, \
1265       IPS_COMPAT_SERVERAID3L, \
1266       IPS_COMPAT_SERVERAID4H, \
1267       IPS_COMPAT_SERVERAID4M, \
1268       IPS_COMPAT_SERVERAID4L, \
1269       IPS_COMPAT_SERVERAID4Mx, \
1270       IPS_COMPAT_SERVERAID4Lx, \
1271       IPS_COMPAT_SARASOTA,         /* one-channel variety of SARASOTA */  \
1272       IPS_COMPAT_SARASOTA,         /* two-channel variety of SARASOTA */  \
1273       IPS_COMPAT_MARCO, \
1274       IPS_COMPAT_SEBRING, \
1275       IPS_COMPAT_TAMPA, \
1276       IPS_COMPAT_KEYWEST \
1277    }
1278
1279
1280 /*
1281  * Overrides for Emacs so that we almost follow Linus's tabbing style.
1282  * Emacs will notice this stuff at the end of the file and automatically
1283  * adjust the settings for this buffer only.  This must remain at the end
1284  * of the file.
1285  * ---------------------------------------------------------------------------
1286  * Local variables:
1287  * c-indent-level: 2
1288  * c-brace-imaginary-offset: 0
1289  * c-brace-offset: -2
1290  * c-argdecl-indent: 2
1291  * c-label-offset: -2
1292  * c-continued-statement-offset: 2
1293  * c-continued-brace-offset: 0
1294  * indent-tabs-mode: nil
1295  * tab-width: 8
1296  * End:
1297  */