include/asm-sh/mpc1211/m1543c.h

   1 #ifndef __ASM_SH_M1543C_H
   2 #define __ASM_SH_M1543C_H
   3
   4 /*
   5  * linux/include/asm-sh/m1543c.h
   6  * Copyright (C) 2001  Nobuhiro Sakawa
   7  * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
   8  *
   9  * from
  10  *
  11  * linux/include/asm-sh/smc37c93x.h
  12  *
  13  * Copyright (C) 2000  Kazumoto Kojima
  14  *
  15  * SMSC 37C93x Super IO Chip support
  16  */
  17
  18 /* Default base I/O address */
  19 #define FDC_PRIMARY_BASE        0x3f0
  20 #define IDE1_PRIMARY_BASE       0x1f0
  21 #define IDE1_SECONDARY_BASE     0x170
  22 #define PARPORT_PRIMARY_BASE    0x378
  23 #define COM1_PRIMARY_BASE       0x2f8
  24 #define COM2_PRIMARY_BASE       0x3f8
  25 #define COM3_PRIMARY_BASE       0x3e8
  26 #define RTC_PRIMARY_BASE        0x070
  27 #define KBC_PRIMARY_BASE        0x060
  28 #define AUXIO_PRIMARY_BASE      0x000   /* XXX */
  29 #define I8259_M_CR              0x20
  30 #define I8259_M_MR              0x21
  31 #define I8259_S_CR              0xa0
  32 #define I8259_S_MR              0xa1
  33
  34 /* Logical device number */
  35 #define LDN_FDC                 0
  36 #define LDN_IDE1                1
  37 #define LDN_IDE2                2
  38 #define LDN_PARPORT             3
  39 #define LDN_COM1                4
  40 #define LDN_COM2                5
  41 #define LDN_COM3                11
  42 #define LDN_RTC                 6
  43 #define LDN_KBC                 7
  44
  45 /* Configuration port and key */
  46 #define CONFIG_PORT             0x3f0
  47 #define INDEX_PORT              CONFIG_PORT
  48 #define DATA_PORT               0x3f1
  49 #define CONFIG_ENTER1           0x51
  50 #define CONFIG_ENTER2           0x23
  51 #define CONFIG_EXIT             0xbb
  52
  53 /* Configuration index */
  54 #define CURRENT_LDN_INDEX       0x07
  55 #define POWER_CONTROL_INDEX     0x22
  56 #define ACTIVATE_INDEX          0x30
  57 #define IO_BASE_HI_INDEX        0x60
  58 #define IO_BASE_LO_INDEX        0x61
  59 #define IRQ_SELECT_INDEX        0x70
  60 #define PS2_IRQ_INDEX           0x72
  61 #define DMA_SELECT_INDEX        0x74
  62
  63 /* UART stuff. Only for debugging.  */
  64 /* UART Register */
  65
  66 #define UART_RBR        0x0     /* Receiver Buffer Register (Read Only) */
  67 #define UART_THR        0x0     /* Transmitter Holding Register (Write Only) */
  68 #define UART_IER        0x2     /* Interrupt Enable Register */
  69 #define UART_IIR        0x4     /* Interrupt Ident Register (Read Only) */
  70 #define UART_FCR        0x4     /* FIFO Control Register (Write Only) */
  71 #define UART_LCR        0x6     /* Line Control Register */
  72 #define UART_MCR        0x8     /* MODEM Control Register */
  73 #define UART_LSR        0xa     /* Line Status Register */
  74 #define UART_MSR        0xc     /* MODEM Status Register */
  75 #define UART_SCR        0xe     /* Scratch Register */
  76 #define UART_DLL        0x0     /* Divisor Latch (LS) */
  77 #define UART_DLM        0x2     /* Divisor Latch (MS) */
  78
  79 #ifndef __ASSEMBLY__
  80 typedef struct uart_reg {
  81         volatile __u16 rbr;
  82         volatile __u16 ier;
  83         volatile __u16 iir;
  84         volatile __u16 lcr;
  85         volatile __u16 mcr;
  86         volatile __u16 lsr;
  87         volatile __u16 msr;
  88         volatile __u16 scr;
  89 } uart_reg;
  90 #endif /* ! __ASSEMBLY__ */
  91
  92 /* Alias for Write Only Register */
  93
  94 #define thr     rbr
  95 #define tcr     iir
  96
  97 /* Alias for Divisor Latch Register */
  98
  99 #define dll     rbr
 100 #define dlm     ier
 101 #define fcr     iir
 102
 103 /* Interrupt Enable Register */
 104
 105 #define IER_ERDAI       0x0100  /* Enable Received Data Available Interrupt */
 106 #define IER_ETHREI      0x0200  /* Enable Transmitter Holding Register Empty Interrupt */
 107 #define IER_ELSI        0x0400  /* Enable Receiver Line Status Interrupt */
 108 #define IER_EMSI        0x0800  /* Enable MODEM Status Interrupt */
 109
 110 /* Interrupt Ident Register */
 111
 112 #define IIR_IP          0x0100  /* "0" if Interrupt Pending */
 113 #define IIR_IIB0        0x0200  /* Interrupt ID Bit 0 */
 114 #define IIR_IIB1        0x0400  /* Interrupt ID Bit 1 */
 115 #define IIR_IIB2        0x0800  /* Interrupt ID Bit 2 */
 116 #define IIR_FIFO        0xc000  /* FIFOs enabled */
 117
 118 /* FIFO Control Register */
 119
 120 #define FCR_FEN         0x0100  /* FIFO enable */
 121 #define FCR_RFRES       0x0200  /* Receiver FIFO reset */
 122 #define FCR_TFRES       0x0400  /* Transmitter FIFO reset */
 123 #define FCR_DMA         0x0800  /* DMA mode select */
 124 #define FCR_RTL         0x4000  /* Receiver triger (LSB) */
 125 #define FCR_RTM         0x8000  /* Receiver triger (MSB) */
 126
 127 /* Line Control Register */
 128
 129 #define LCR_WLS0        0x0100  /* Word Length Select Bit 0 */
 130 #define LCR_WLS1        0x0200  /* Word Length Select Bit 1 */
 131 #define LCR_STB         0x0400  /* Number of Stop Bits */
 132 #define LCR_PEN         0x0800  /* Parity Enable */
 133 #define LCR_EPS         0x1000  /* Even Parity Select */
 134 #define LCR_SP          0x2000  /* Stick Parity */
 135 #define LCR_SB          0x4000  /* Set Break */
 136 #define LCR_DLAB        0x8000  /* Divisor Latch Access Bit */
 137
 138 /* MODEM Control Register */
 139
 140 #define MCR_DTR         0x0100  /* Data Terminal Ready */
 141 #define MCR_RTS         0x0200  /* Request to Send */
 142 #define MCR_OUT1        0x0400  /* Out 1 */
 143 #define MCR_IRQEN       0x0800  /* IRQ Enable */
 144 #define MCR_LOOP        0x1000  /* Loop */
 145
 146 /* Line Status Register */
 147
 148 #define LSR_DR          0x0100  /* Data Ready */
 149 #define LSR_OE          0x0200  /* Overrun Error */
 150 #define LSR_PE          0x0400  /* Parity Error */
 151 #define LSR_FE          0x0800  /* Framing Error */
 152 #define LSR_BI          0x1000  /* Break Interrupt */
 153 #define LSR_THRE        0x2000  /* Transmitter Holding Register Empty */
 154 #define LSR_TEMT        0x4000  /* Transmitter Empty */
 155 #define LSR_FIFOE       0x8000  /* Receiver FIFO error */
 156
 157 /* MODEM Status Register */
 158
 159 #define MSR_DCTS        0x0100  /* Delta Clear to Send */
 160 #define MSR_DDSR        0x0200  /* Delta Data Set Ready */
 161 #define MSR_TERI        0x0400  /* Trailing Edge Ring Indicator */
 162 #define MSR_DDCD        0x0800  /* Delta Data Carrier Detect */
 163 #define MSR_CTS         0x1000  /* Clear to Send */
 164 #define MSR_DSR         0x2000  /* Data Set Ready */
 165 #define MSR_RI          0x4000  /* Ring Indicator */
 166 #define MSR_DCD         0x8000  /* Data Carrier Detect */
 167
 168 /* Baud Rate Divisor */
 169
 170 #define UART_CLK        (1843200)       /* 1.8432 MHz */
 171 #define UART_BAUD(x)    (UART_CLK / (16 * (x)))
 172
 173 /* RTC register definition */
 174 #define RTC_SECONDS             0
 175 #define RTC_SECONDS_ALARM       1
 176 #define RTC_MINUTES             2
 177 #define RTC_MINUTES_ALARM       3
 178 #define RTC_HOURS               4
 179 #define RTC_HOURS_ALARM         5
 180 #define RTC_DAY_OF_WEEK         6
 181 #define RTC_DAY_OF_MONTH        7
 182 #define RTC_MONTH               8
 183 #define RTC_YEAR                9
 184 #define RTC_FREQ_SELECT         10
 185 # define RTC_UIP 0x80
 186 # define RTC_DIV_CTL 0x70
 187 /* This RTC can work under 32.768KHz clock only.  */
 188 # define RTC_OSC_ENABLE 0x20
 189 # define RTC_OSC_DISABLE 0x00
 190 #define RTC_CONTROL             11
 191 # define RTC_SET 0x80
 192 # define RTC_PIE 0x40
 193 # define RTC_AIE 0x20
 194 # define RTC_UIE 0x10
 195 # define RTC_SQWE 0x08
 196 # define RTC_DM_BINARY 0x04
 197 # define RTC_24H 0x02
 198 # define RTC_DST_EN 0x01
 199
 200 #endif  /* __ASM_SH_M1543C_H */