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Merge branches 'timers-core-for-linus' and 'timers-urgent-for-linus' of git://git...
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
blob3ffe2ecfd5efe37649750c64636c91c042f57a47
1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <media/videobuf2-v4l2.h>
26 #include "s5p_mfc_common.h"
27 #include "s5p_mfc_ctrl.h"
28 #include "s5p_mfc_debug.h"
29 #include "s5p_mfc_dec.h"
30 #include "s5p_mfc_enc.h"
31 #include "s5p_mfc_intr.h"
32 #include "s5p_mfc_opr.h"
33 #include "s5p_mfc_cmd.h"
34 #include "s5p_mfc_pm.h"
35
36 #define S5P_MFC_NAME "s5p-mfc"
37 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
40 int mfc_debug_level;
41 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44 /* Helper functions for interrupt processing */
45
46 /* Remove from hw execution round robin */
47 void clear_work_bit(struct s5p_mfc_ctx *ctx)
48 {
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
52 __clear_bit(ctx->num, &dev->ctx_work_bits);
53 spin_unlock(&dev->condlock);
54 }
55
56 /* Add to hw execution round robin */
57 void set_work_bit(struct s5p_mfc_ctx *ctx)
58 {
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64 }
65
66 /* Remove from hw execution round robin */
67 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68 {
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75 }
76
77 /* Add to hw execution round robin */
78 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79 {
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86 }
87
88 /* Wake up context wait_queue */
89 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91 {
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96 }
97
98 /* Wake up device wait_queue */
99 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101 {
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106 }
107
108 static void s5p_mfc_watchdog(unsigned long arg)
109 {
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
119 * reset the MFC. */
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126 }
127
128 static void s5p_mfc_watchdog_worker(struct work_struct *work)
129 {
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
153 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
154 &ctx->dst_queue, &ctx->vq_dst);
155 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
156 &ctx->src_queue, &ctx->vq_src);
157 clear_work_bit(ctx);
158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162
163 /* De-init MFC */
164 s5p_mfc_deinit_hw(dev);
165
166 /* Double check if there is at least one instance running.
167 * If no instance is in memory than no firmware should be present */
168 if (dev->num_inst > 0) {
169 ret = s5p_mfc_load_firmware(dev);
170 if (ret) {
171 mfc_err("Failed to reload FW\n");
172 goto unlock;
173 }
174 s5p_mfc_clock_on();
175 ret = s5p_mfc_init_hw(dev);
176 if (ret)
177 mfc_err("Failed to reinit FW\n");
178 }
179 unlock:
180 if (mutex_locked)
181 mutex_unlock(&dev->mfc_mutex);
182 }
183
184 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
185 {
186 struct s5p_mfc_buf *dst_buf;
187 struct s5p_mfc_dev *dev = ctx->dev;
188
189 ctx->state = MFCINST_FINISHED;
190 ctx->sequence++;
191 while (!list_empty(&ctx->dst_queue)) {
192 dst_buf = list_entry(ctx->dst_queue.next,
193 struct s5p_mfc_buf, list);
194 mfc_debug(2, "Cleaning up buffer: %d\n",
195 dst_buf->b->vb2_buf.index);
196 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
197 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
198 list_del(&dst_buf->list);
199 dst_buf->flags |= MFC_BUF_FLAG_EOS;
200 ctx->dst_queue_cnt--;
201 dst_buf->b->sequence = (ctx->sequence++);
202
203 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
204 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
205 dst_buf->b->field = V4L2_FIELD_NONE;
206 else
207 dst_buf->b->field = V4L2_FIELD_INTERLACED;
208 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
209
210 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
211 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
212 }
213 }
214
215 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
216 {
217 struct s5p_mfc_dev *dev = ctx->dev;
218 struct s5p_mfc_buf *dst_buf, *src_buf;
219 size_t dec_y_addr;
220 unsigned int frame_type;
221
222 /* Make sure we actually have a new frame before continuing. */
223 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
224 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
225 return;
226 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
227
228 /* Copy timestamp / timecode from decoded src to dst and set
229 appropriate flags. */
230 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
231 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
232 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
233 == dec_y_addr) {
234 dst_buf->b->timecode =
235 src_buf->b->timecode;
236 dst_buf->b->timestamp =
237 src_buf->b->timestamp;
238 dst_buf->b->flags &=
239 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
240 dst_buf->b->flags |=
241 src_buf->b->flags
242 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
243 switch (frame_type) {
244 case S5P_FIMV_DECODE_FRAME_I_FRAME:
245 dst_buf->b->flags |=
246 V4L2_BUF_FLAG_KEYFRAME;
247 break;
248 case S5P_FIMV_DECODE_FRAME_P_FRAME:
249 dst_buf->b->flags |=
250 V4L2_BUF_FLAG_PFRAME;
251 break;
252 case S5P_FIMV_DECODE_FRAME_B_FRAME:
253 dst_buf->b->flags |=
254 V4L2_BUF_FLAG_BFRAME;
255 break;
256 default:
257 /* Don't know how to handle
258 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
259 mfc_debug(2, "Unexpected frame type: %d\n",
260 frame_type);
261 }
262 break;
263 }
264 }
265 }
266
267 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
268 {
269 struct s5p_mfc_dev *dev = ctx->dev;
270 struct s5p_mfc_buf *dst_buf;
271 size_t dspl_y_addr;
272 unsigned int frame_type;
273
274 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
275 if (IS_MFCV6_PLUS(dev))
276 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
277 get_disp_frame_type, ctx);
278 else
279 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
280 get_dec_frame_type, dev);
281
282 /* If frame is same as previous then skip and do not dequeue */
283 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
284 if (!ctx->after_packed_pb)
285 ctx->sequence++;
286 ctx->after_packed_pb = 0;
287 return;
288 }
289 ctx->sequence++;
290 /* The MFC returns address of the buffer, now we have to
291 * check which videobuf does it correspond to */
292 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
293 /* Check if this is the buffer we're looking for */
294 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
295 == dspl_y_addr) {
296 list_del(&dst_buf->list);
297 ctx->dst_queue_cnt--;
298 dst_buf->b->sequence = ctx->sequence;
299 if (s5p_mfc_hw_call(dev->mfc_ops,
300 get_pic_type_top, ctx) ==
301 s5p_mfc_hw_call(dev->mfc_ops,
302 get_pic_type_bot, ctx))
303 dst_buf->b->field = V4L2_FIELD_NONE;
304 else
305 dst_buf->b->field =
306 V4L2_FIELD_INTERLACED;
307 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
308 ctx->luma_size);
309 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
310 ctx->chroma_size);
311 clear_bit(dst_buf->b->vb2_buf.index,
312 &ctx->dec_dst_flag);
313
314 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
315 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
316
317 break;
318 }
319 }
320 }
321
322 /* Handle frame decoding interrupt */
323 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
324 unsigned int reason, unsigned int err)
325 {
326 struct s5p_mfc_dev *dev = ctx->dev;
327 unsigned int dst_frame_status;
328 unsigned int dec_frame_status;
329 struct s5p_mfc_buf *src_buf;
330 unsigned long flags;
331 unsigned int res_change;
332
333 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
334 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
335 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
336 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
337 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
338 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
339 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
340 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
341 if (ctx->state == MFCINST_RES_CHANGE_INIT)
342 ctx->state = MFCINST_RES_CHANGE_FLUSH;
343 if (res_change == S5P_FIMV_RES_INCREASE ||
344 res_change == S5P_FIMV_RES_DECREASE) {
345 ctx->state = MFCINST_RES_CHANGE_INIT;
346 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
347 wake_up_ctx(ctx, reason, err);
348 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
349 s5p_mfc_clock_off();
350 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
351 return;
352 }
353 if (ctx->dpb_flush_flag)
354 ctx->dpb_flush_flag = 0;
355
356 spin_lock_irqsave(&dev->irqlock, flags);
357 /* All frames remaining in the buffer have been extracted */
358 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
359 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
360 static const struct v4l2_event ev_src_ch = {
361 .type = V4L2_EVENT_SOURCE_CHANGE,
362 .u.src_change.changes =
363 V4L2_EVENT_SRC_CH_RESOLUTION,
364 };
365
366 s5p_mfc_handle_frame_all_extracted(ctx);
367 ctx->state = MFCINST_RES_CHANGE_END;
368 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
369
370 goto leave_handle_frame;
371 } else {
372 s5p_mfc_handle_frame_all_extracted(ctx);
373 }
374 }
375
376 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
377 s5p_mfc_handle_frame_copy_time(ctx);
378
379 /* A frame has been decoded and is in the buffer */
380 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
381 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
382 s5p_mfc_handle_frame_new(ctx, err);
383 } else {
384 mfc_debug(2, "No frame decode\n");
385 }
386 /* Mark source buffer as complete */
387 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
388 && !list_empty(&ctx->src_queue)) {
389 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
390 list);
391 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
392 get_consumed_stream, dev);
393 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
394 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
395 ctx->consumed_stream + STUFF_BYTE <
396 src_buf->b->vb2_buf.planes[0].bytesused) {
397 /* Run MFC again on the same buffer */
398 mfc_debug(2, "Running again the same buffer\n");
399 ctx->after_packed_pb = 1;
400 } else {
401 mfc_debug(2, "MFC needs next buffer\n");
402 ctx->consumed_stream = 0;
403 if (src_buf->flags & MFC_BUF_FLAG_EOS)
404 ctx->state = MFCINST_FINISHING;
405 list_del(&src_buf->list);
406 ctx->src_queue_cnt--;
407 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
408 vb2_buffer_done(&src_buf->b->vb2_buf,
409 VB2_BUF_STATE_ERROR);
410 else
411 vb2_buffer_done(&src_buf->b->vb2_buf,
412 VB2_BUF_STATE_DONE);
413 }
414 }
415 leave_handle_frame:
416 spin_unlock_irqrestore(&dev->irqlock, flags);
417 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
418 || ctx->dst_queue_cnt < ctx->pb_count)
419 clear_work_bit(ctx);
420 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
421 wake_up_ctx(ctx, reason, err);
422 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
423 s5p_mfc_clock_off();
424 /* if suspending, wake up device and do not try_run again*/
425 if (test_bit(0, &dev->enter_suspend))
426 wake_up_dev(dev, reason, err);
427 else
428 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
429 }
430
431 /* Error handling for interrupt */
432 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
433 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
434 {
435 unsigned long flags;
436
437 mfc_err("Interrupt Error: %08x\n", err);
438
439 if (ctx != NULL) {
440 /* Error recovery is dependent on the state of context */
441 switch (ctx->state) {
442 case MFCINST_RES_CHANGE_INIT:
443 case MFCINST_RES_CHANGE_FLUSH:
444 case MFCINST_RES_CHANGE_END:
445 case MFCINST_FINISHING:
446 case MFCINST_FINISHED:
447 case MFCINST_RUNNING:
448 /* It is highly probable that an error occurred
449 * while decoding a frame */
450 clear_work_bit(ctx);
451 ctx->state = MFCINST_ERROR;
452 /* Mark all dst buffers as having an error */
453 spin_lock_irqsave(&dev->irqlock, flags);
454 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
455 &ctx->dst_queue, &ctx->vq_dst);
456 /* Mark all src buffers as having an error */
457 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
458 &ctx->src_queue, &ctx->vq_src);
459 spin_unlock_irqrestore(&dev->irqlock, flags);
460 wake_up_ctx(ctx, reason, err);
461 break;
462 default:
463 clear_work_bit(ctx);
464 ctx->state = MFCINST_ERROR;
465 wake_up_ctx(ctx, reason, err);
466 break;
467 }
468 }
469 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
470 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
471 s5p_mfc_clock_off();
472 wake_up_dev(dev, reason, err);
473 return;
474 }
475
476 /* Header parsing interrupt handling */
477 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
478 unsigned int reason, unsigned int err)
479 {
480 struct s5p_mfc_dev *dev;
481
482 if (ctx == NULL)
483 return;
484 dev = ctx->dev;
485 if (ctx->c_ops->post_seq_start) {
486 if (ctx->c_ops->post_seq_start(ctx))
487 mfc_err("post_seq_start() failed\n");
488 } else {
489 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
490 dev);
491 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
492 dev);
493
494 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
495
496 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
497 dev);
498 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
499 dev);
500 if (ctx->img_width == 0 || ctx->img_height == 0)
501 ctx->state = MFCINST_ERROR;
502 else
503 ctx->state = MFCINST_HEAD_PARSED;
504
505 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
506 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
507 !list_empty(&ctx->src_queue)) {
508 struct s5p_mfc_buf *src_buf;
509 src_buf = list_entry(ctx->src_queue.next,
510 struct s5p_mfc_buf, list);
511 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
512 dev) <
513 src_buf->b->vb2_buf.planes[0].bytesused)
514 ctx->head_processed = 0;
515 else
516 ctx->head_processed = 1;
517 } else {
518 ctx->head_processed = 1;
519 }
520 }
521 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
522 clear_work_bit(ctx);
523 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
524 s5p_mfc_clock_off();
525 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
526 wake_up_ctx(ctx, reason, err);
527 }
528
529 /* Header parsing interrupt handling */
530 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
531 unsigned int reason, unsigned int err)
532 {
533 struct s5p_mfc_buf *src_buf;
534 struct s5p_mfc_dev *dev;
535 unsigned long flags;
536
537 if (ctx == NULL)
538 return;
539 dev = ctx->dev;
540 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
541 ctx->int_type = reason;
542 ctx->int_err = err;
543 ctx->int_cond = 1;
544 clear_work_bit(ctx);
545 if (err == 0) {
546 ctx->state = MFCINST_RUNNING;
547 if (!ctx->dpb_flush_flag && ctx->head_processed) {
548 spin_lock_irqsave(&dev->irqlock, flags);
549 if (!list_empty(&ctx->src_queue)) {
550 src_buf = list_entry(ctx->src_queue.next,
551 struct s5p_mfc_buf, list);
552 list_del(&src_buf->list);
553 ctx->src_queue_cnt--;
554 vb2_buffer_done(&src_buf->b->vb2_buf,
555 VB2_BUF_STATE_DONE);
556 }
557 spin_unlock_irqrestore(&dev->irqlock, flags);
558 } else {
559 ctx->dpb_flush_flag = 0;
560 }
561 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
562
563 s5p_mfc_clock_off();
564
565 wake_up(&ctx->queue);
566 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
567 } else {
568 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
569
570 s5p_mfc_clock_off();
571
572 wake_up(&ctx->queue);
573 }
574 }
575
576 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
577 {
578 struct s5p_mfc_dev *dev = ctx->dev;
579 struct s5p_mfc_buf *mb_entry;
580
581 mfc_debug(2, "Stream completed\n");
582
583 ctx->state = MFCINST_FINISHED;
584
585 spin_lock(&dev->irqlock);
586 if (!list_empty(&ctx->dst_queue)) {
587 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
588 list);
589 list_del(&mb_entry->list);
590 ctx->dst_queue_cnt--;
591 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
592 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
593 }
594 spin_unlock(&dev->irqlock);
595
596 clear_work_bit(ctx);
597
598 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
599
600 s5p_mfc_clock_off();
601 wake_up(&ctx->queue);
602 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
603 }
604
605 /* Interrupt processing */
606 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
607 {
608 struct s5p_mfc_dev *dev = priv;
609 struct s5p_mfc_ctx *ctx;
610 unsigned int reason;
611 unsigned int err;
612
613 mfc_debug_enter();
614 /* Reset the timeout watchdog */
615 atomic_set(&dev->watchdog_cnt, 0);
616 ctx = dev->ctx[dev->curr_ctx];
617 /* Get the reason of interrupt and the error code */
618 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
619 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
620 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
621 switch (reason) {
622 case S5P_MFC_R2H_CMD_ERR_RET:
623 /* An error has occurred */
624 if (ctx->state == MFCINST_RUNNING &&
625 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
626 dev->warn_start)
627 s5p_mfc_handle_frame(ctx, reason, err);
628 else
629 s5p_mfc_handle_error(dev, ctx, reason, err);
630 clear_bit(0, &dev->enter_suspend);
631 break;
632
633 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
634 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
635 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
636 if (ctx->c_ops->post_frame_start) {
637 if (ctx->c_ops->post_frame_start(ctx))
638 mfc_err("post_frame_start() failed\n");
639
640 if (ctx->state == MFCINST_FINISHING &&
641 list_empty(&ctx->ref_queue)) {
642 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
643 s5p_mfc_handle_stream_complete(ctx);
644 break;
645 }
646 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
647 wake_up_ctx(ctx, reason, err);
648 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
649 s5p_mfc_clock_off();
650 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
651 } else {
652 s5p_mfc_handle_frame(ctx, reason, err);
653 }
654 break;
655
656 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
657 s5p_mfc_handle_seq_done(ctx, reason, err);
658 break;
659
660 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
661 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
662 ctx->state = MFCINST_GOT_INST;
663 clear_work_bit(ctx);
664 wake_up(&ctx->queue);
665 goto irq_cleanup_hw;
666
667 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
668 clear_work_bit(ctx);
669 ctx->inst_no = MFC_NO_INSTANCE_SET;
670 ctx->state = MFCINST_FREE;
671 wake_up(&ctx->queue);
672 goto irq_cleanup_hw;
673
674 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
675 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
676 case S5P_MFC_R2H_CMD_SLEEP_RET:
677 case S5P_MFC_R2H_CMD_WAKEUP_RET:
678 if (ctx)
679 clear_work_bit(ctx);
680 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
681 wake_up_dev(dev, reason, err);
682 clear_bit(0, &dev->hw_lock);
683 clear_bit(0, &dev->enter_suspend);
684 break;
685
686 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
687 s5p_mfc_handle_init_buffers(ctx, reason, err);
688 break;
689
690 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
691 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
692 ctx->int_type = reason;
693 ctx->int_err = err;
694 s5p_mfc_handle_stream_complete(ctx);
695 break;
696
697 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
698 clear_work_bit(ctx);
699 ctx->state = MFCINST_RUNNING;
700 wake_up(&ctx->queue);
701 goto irq_cleanup_hw;
702
703 default:
704 mfc_debug(2, "Unknown int reason\n");
705 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
706 }
707 mfc_debug_leave();
708 return IRQ_HANDLED;
709 irq_cleanup_hw:
710 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
711 ctx->int_type = reason;
712 ctx->int_err = err;
713 ctx->int_cond = 1;
714 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
715 mfc_err("Failed to unlock hw\n");
716
717 s5p_mfc_clock_off();
718
719 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
720 mfc_debug(2, "Exit via irq_cleanup_hw\n");
721 return IRQ_HANDLED;
722 }
723
724 /* Open an MFC node */
725 static int s5p_mfc_open(struct file *file)
726 {
727 struct video_device *vdev = video_devdata(file);
728 struct s5p_mfc_dev *dev = video_drvdata(file);
729 struct s5p_mfc_ctx *ctx = NULL;
730 struct vb2_queue *q;
731 int ret = 0;
732
733 mfc_debug_enter();
734 if (mutex_lock_interruptible(&dev->mfc_mutex))
735 return -ERESTARTSYS;
736 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
737 /* Allocate memory for context */
738 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
739 if (!ctx) {
740 mfc_err("Not enough memory\n");
741 ret = -ENOMEM;
742 goto err_alloc;
743 }
744 v4l2_fh_init(&ctx->fh, vdev);
745 file->private_data = &ctx->fh;
746 v4l2_fh_add(&ctx->fh);
747 ctx->dev = dev;
748 INIT_LIST_HEAD(&ctx->src_queue);
749 INIT_LIST_HEAD(&ctx->dst_queue);
750 ctx->src_queue_cnt = 0;
751 ctx->dst_queue_cnt = 0;
752 /* Get context number */
753 ctx->num = 0;
754 while (dev->ctx[ctx->num]) {
755 ctx->num++;
756 if (ctx->num >= MFC_NUM_CONTEXTS) {
757 mfc_err("Too many open contexts\n");
758 ret = -EBUSY;
759 goto err_no_ctx;
760 }
761 }
762 /* Mark context as idle */
763 clear_work_bit_irqsave(ctx);
764 dev->ctx[ctx->num] = ctx;
765 if (vdev == dev->vfd_dec) {
766 ctx->type = MFCINST_DECODER;
767 ctx->c_ops = get_dec_codec_ops();
768 s5p_mfc_dec_init(ctx);
769 /* Setup ctrl handler */
770 ret = s5p_mfc_dec_ctrls_setup(ctx);
771 if (ret) {
772 mfc_err("Failed to setup mfc controls\n");
773 goto err_ctrls_setup;
774 }
775 } else if (vdev == dev->vfd_enc) {
776 ctx->type = MFCINST_ENCODER;
777 ctx->c_ops = get_enc_codec_ops();
778 /* only for encoder */
779 INIT_LIST_HEAD(&ctx->ref_queue);
780 ctx->ref_queue_cnt = 0;
781 s5p_mfc_enc_init(ctx);
782 /* Setup ctrl handler */
783 ret = s5p_mfc_enc_ctrls_setup(ctx);
784 if (ret) {
785 mfc_err("Failed to setup mfc controls\n");
786 goto err_ctrls_setup;
787 }
788 } else {
789 ret = -ENOENT;
790 goto err_bad_node;
791 }
792 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
793 ctx->inst_no = MFC_NO_INSTANCE_SET;
794 /* Load firmware if this is the first instance */
795 if (dev->num_inst == 1) {
796 dev->watchdog_timer.expires = jiffies +
797 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
798 add_timer(&dev->watchdog_timer);
799 ret = s5p_mfc_power_on();
800 if (ret < 0) {
801 mfc_err("power on failed\n");
802 goto err_pwr_enable;
803 }
804 s5p_mfc_clock_on();
805 ret = s5p_mfc_load_firmware(dev);
806 if (ret) {
807 s5p_mfc_clock_off();
808 goto err_load_fw;
809 }
810 /* Init the FW */
811 ret = s5p_mfc_init_hw(dev);
812 s5p_mfc_clock_off();
813 if (ret)
814 goto err_init_hw;
815 }
816 /* Init videobuf2 queue for CAPTURE */
817 q = &ctx->vq_dst;
818 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
819 q->drv_priv = &ctx->fh;
820 q->lock = &dev->mfc_mutex;
821 if (vdev == dev->vfd_dec) {
822 q->io_modes = VB2_MMAP;
823 q->ops = get_dec_queue_ops();
824 } else if (vdev == dev->vfd_enc) {
825 q->io_modes = VB2_MMAP | VB2_USERPTR;
826 q->ops = get_enc_queue_ops();
827 } else {
828 ret = -ENOENT;
829 goto err_queue_init;
830 }
831 q->mem_ops = &vb2_dma_contig_memops;
832 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
833 ret = vb2_queue_init(q);
834 if (ret) {
835 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
836 goto err_queue_init;
837 }
838 /* Init videobuf2 queue for OUTPUT */
839 q = &ctx->vq_src;
840 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
841 q->io_modes = VB2_MMAP;
842 q->drv_priv = &ctx->fh;
843 q->lock = &dev->mfc_mutex;
844 if (vdev == dev->vfd_dec) {
845 q->io_modes = VB2_MMAP;
846 q->ops = get_dec_queue_ops();
847 } else if (vdev == dev->vfd_enc) {
848 q->io_modes = VB2_MMAP | VB2_USERPTR;
849 q->ops = get_enc_queue_ops();
850 } else {
851 ret = -ENOENT;
852 goto err_queue_init;
853 }
854 /* One way to indicate end-of-stream for MFC is to set the
855 * bytesused == 0. However by default videobuf2 handles bytesused
856 * equal to 0 as a special case and changes its value to the size
857 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
858 * will keep the value of bytesused intact.
859 */
860 q->allow_zero_bytesused = 1;
861 q->mem_ops = &vb2_dma_contig_memops;
862 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
863 ret = vb2_queue_init(q);
864 if (ret) {
865 mfc_err("Failed to initialize videobuf2 queue(output)\n");
866 goto err_queue_init;
867 }
868 init_waitqueue_head(&ctx->queue);
869 mutex_unlock(&dev->mfc_mutex);
870 mfc_debug_leave();
871 return ret;
872 /* Deinit when failure occurred */
873 err_queue_init:
874 if (dev->num_inst == 1)
875 s5p_mfc_deinit_hw(dev);
876 err_init_hw:
877 err_load_fw:
878 err_pwr_enable:
879 if (dev->num_inst == 1) {
880 if (s5p_mfc_power_off() < 0)
881 mfc_err("power off failed\n");
882 del_timer_sync(&dev->watchdog_timer);
883 }
884 err_ctrls_setup:
885 s5p_mfc_dec_ctrls_delete(ctx);
886 err_bad_node:
887 dev->ctx[ctx->num] = NULL;
888 err_no_ctx:
889 v4l2_fh_del(&ctx->fh);
890 v4l2_fh_exit(&ctx->fh);
891 kfree(ctx);
892 err_alloc:
893 dev->num_inst--;
894 mutex_unlock(&dev->mfc_mutex);
895 mfc_debug_leave();
896 return ret;
897 }
898
899 /* Release MFC context */
900 static int s5p_mfc_release(struct file *file)
901 {
902 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
903 struct s5p_mfc_dev *dev = ctx->dev;
904
905 mfc_debug_enter();
906 mutex_lock(&dev->mfc_mutex);
907 s5p_mfc_clock_on();
908 vb2_queue_release(&ctx->vq_src);
909 vb2_queue_release(&ctx->vq_dst);
910 /* Mark context as idle */
911 clear_work_bit_irqsave(ctx);
912 /* If instance was initialised and not yet freed,
913 * return instance and free resources */
914 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
915 mfc_debug(2, "Has to free instance\n");
916 s5p_mfc_close_mfc_inst(dev, ctx);
917 }
918 /* hardware locking scheme */
919 if (dev->curr_ctx == ctx->num)
920 clear_bit(0, &dev->hw_lock);
921 dev->num_inst--;
922 if (dev->num_inst == 0) {
923 mfc_debug(2, "Last instance\n");
924 s5p_mfc_deinit_hw(dev);
925 del_timer_sync(&dev->watchdog_timer);
926 if (s5p_mfc_power_off() < 0)
927 mfc_err("Power off failed\n");
928 }
929 mfc_debug(2, "Shutting down clock\n");
930 s5p_mfc_clock_off();
931 dev->ctx[ctx->num] = NULL;
932 s5p_mfc_dec_ctrls_delete(ctx);
933 v4l2_fh_del(&ctx->fh);
934 v4l2_fh_exit(&ctx->fh);
935 kfree(ctx);
936 mfc_debug_leave();
937 mutex_unlock(&dev->mfc_mutex);
938 return 0;
939 }
940
941 /* Poll */
942 static unsigned int s5p_mfc_poll(struct file *file,
943 struct poll_table_struct *wait)
944 {
945 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
946 struct s5p_mfc_dev *dev = ctx->dev;
947 struct vb2_queue *src_q, *dst_q;
948 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
949 unsigned int rc = 0;
950 unsigned long flags;
951
952 mutex_lock(&dev->mfc_mutex);
953 src_q = &ctx->vq_src;
954 dst_q = &ctx->vq_dst;
955 /*
956 * There has to be at least one buffer queued on each queued_list, which
957 * means either in driver already or waiting for driver to claim it
958 * and start processing.
959 */
960 if ((!src_q->streaming || list_empty(&src_q->queued_list))
961 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
962 rc = POLLERR;
963 goto end;
964 }
965 mutex_unlock(&dev->mfc_mutex);
966 poll_wait(file, &ctx->fh.wait, wait);
967 poll_wait(file, &src_q->done_wq, wait);
968 poll_wait(file, &dst_q->done_wq, wait);
969 mutex_lock(&dev->mfc_mutex);
970 if (v4l2_event_pending(&ctx->fh))
971 rc |= POLLPRI;
972 spin_lock_irqsave(&src_q->done_lock, flags);
973 if (!list_empty(&src_q->done_list))
974 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
975 done_entry);
976 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
977 || src_vb->state == VB2_BUF_STATE_ERROR))
978 rc |= POLLOUT | POLLWRNORM;
979 spin_unlock_irqrestore(&src_q->done_lock, flags);
980 spin_lock_irqsave(&dst_q->done_lock, flags);
981 if (!list_empty(&dst_q->done_list))
982 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
983 done_entry);
984 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
985 || dst_vb->state == VB2_BUF_STATE_ERROR))
986 rc |= POLLIN | POLLRDNORM;
987 spin_unlock_irqrestore(&dst_q->done_lock, flags);
988 end:
989 mutex_unlock(&dev->mfc_mutex);
990 return rc;
991 }
992
993 /* Mmap */
994 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
995 {
996 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
997 struct s5p_mfc_dev *dev = ctx->dev;
998 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
999 int ret;
1000
1001 if (mutex_lock_interruptible(&dev->mfc_mutex))
1002 return -ERESTARTSYS;
1003 if (offset < DST_QUEUE_OFF_BASE) {
1004 mfc_debug(2, "mmaping source\n");
1005 ret = vb2_mmap(&ctx->vq_src, vma);
1006 } else { /* capture */
1007 mfc_debug(2, "mmaping destination\n");
1008 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1009 ret = vb2_mmap(&ctx->vq_dst, vma);
1010 }
1011 mutex_unlock(&dev->mfc_mutex);
1012 return ret;
1013 }
1014
1015 /* v4l2 ops */
1016 static const struct v4l2_file_operations s5p_mfc_fops = {
1017 .owner = THIS_MODULE,
1018 .open = s5p_mfc_open,
1019 .release = s5p_mfc_release,
1020 .poll = s5p_mfc_poll,
1021 .unlocked_ioctl = video_ioctl2,
1022 .mmap = s5p_mfc_mmap,
1023 };
1024
1025 static int match_child(struct device *dev, void *data)
1026 {
1027 if (!dev_name(dev))
1028 return 0;
1029 return !strcmp(dev_name(dev), (char *)data);
1030 }
1031
1032 static void *mfc_get_drv_data(struct platform_device *pdev);
1033
1034 static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1035 {
1036 unsigned int mem_info[2] = { };
1037
1038 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1039 sizeof(struct device), GFP_KERNEL);
1040 if (!dev->mem_dev_l) {
1041 mfc_err("Not enough memory\n");
1042 return -ENOMEM;
1043 }
1044 device_initialize(dev->mem_dev_l);
1045 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1046 "samsung,mfc-l", mem_info, 2);
1047 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1048 mem_info[0], mem_info[1],
1049 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1050 mfc_err("Failed to declare coherent memory for\n"
1051 "MFC device\n");
1052 return -ENOMEM;
1053 }
1054
1055 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1056 sizeof(struct device), GFP_KERNEL);
1057 if (!dev->mem_dev_r) {
1058 mfc_err("Not enough memory\n");
1059 return -ENOMEM;
1060 }
1061 device_initialize(dev->mem_dev_r);
1062 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1063 "samsung,mfc-r", mem_info, 2);
1064 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1065 mem_info[0], mem_info[1],
1066 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1067 pr_err("Failed to declare coherent memory for\n"
1068 "MFC device\n");
1069 return -ENOMEM;
1070 }
1071 return 0;
1072 }
1073
1074 /* MFC probe function */
1075 static int s5p_mfc_probe(struct platform_device *pdev)
1076 {
1077 struct s5p_mfc_dev *dev;
1078 struct video_device *vfd;
1079 struct resource *res;
1080 int ret;
1081
1082 pr_debug("%s++\n", __func__);
1083 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1084 if (!dev) {
1085 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1086 return -ENOMEM;
1087 }
1088
1089 spin_lock_init(&dev->irqlock);
1090 spin_lock_init(&dev->condlock);
1091 dev->plat_dev = pdev;
1092 if (!dev->plat_dev) {
1093 dev_err(&pdev->dev, "No platform data specified\n");
1094 return -ENODEV;
1095 }
1096
1097 dev->variant = mfc_get_drv_data(pdev);
1098
1099 ret = s5p_mfc_init_pm(dev);
1100 if (ret < 0) {
1101 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1102 return ret;
1103 }
1104
1105 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1106
1107 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1108 if (IS_ERR(dev->regs_base))
1109 return PTR_ERR(dev->regs_base);
1110
1111 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1112 if (res == NULL) {
1113 dev_err(&pdev->dev, "failed to get irq resource\n");
1114 ret = -ENOENT;
1115 goto err_res;
1116 }
1117 dev->irq = res->start;
1118 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1119 0, pdev->name, dev);
1120 if (ret) {
1121 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1122 goto err_res;
1123 }
1124
1125 if (pdev->dev.of_node) {
1126 ret = s5p_mfc_alloc_memdevs(dev);
1127 if (ret < 0)
1128 goto err_res;
1129 } else {
1130 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1131 "s5p-mfc-l", match_child);
1132 if (!dev->mem_dev_l) {
1133 mfc_err("Mem child (L) device get failed\n");
1134 ret = -ENODEV;
1135 goto err_res;
1136 }
1137 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1138 "s5p-mfc-r", match_child);
1139 if (!dev->mem_dev_r) {
1140 mfc_err("Mem child (R) device get failed\n");
1141 ret = -ENODEV;
1142 goto err_res;
1143 }
1144 }
1145
1146 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1147 if (IS_ERR(dev->alloc_ctx[0])) {
1148 ret = PTR_ERR(dev->alloc_ctx[0]);
1149 goto err_res;
1150 }
1151 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1152 if (IS_ERR(dev->alloc_ctx[1])) {
1153 ret = PTR_ERR(dev->alloc_ctx[1]);
1154 goto err_mem_init_ctx_1;
1155 }
1156
1157 mutex_init(&dev->mfc_mutex);
1158
1159 ret = s5p_mfc_alloc_firmware(dev);
1160 if (ret)
1161 goto err_alloc_fw;
1162
1163 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1164 if (ret)
1165 goto err_v4l2_dev_reg;
1166 init_waitqueue_head(&dev->queue);
1167
1168 /* decoder */
1169 vfd = video_device_alloc();
1170 if (!vfd) {
1171 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1172 ret = -ENOMEM;
1173 goto err_dec_alloc;
1174 }
1175 vfd->fops = &s5p_mfc_fops;
1176 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1177 vfd->release = video_device_release;
1178 vfd->lock = &dev->mfc_mutex;
1179 vfd->v4l2_dev = &dev->v4l2_dev;
1180 vfd->vfl_dir = VFL_DIR_M2M;
1181 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1182 dev->vfd_dec = vfd;
1183 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1184 if (ret) {
1185 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1186 video_device_release(vfd);
1187 goto err_dec_reg;
1188 }
1189 v4l2_info(&dev->v4l2_dev,
1190 "decoder registered as /dev/video%d\n", vfd->num);
1191 video_set_drvdata(vfd, dev);
1192
1193 /* encoder */
1194 vfd = video_device_alloc();
1195 if (!vfd) {
1196 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1197 ret = -ENOMEM;
1198 goto err_enc_alloc;
1199 }
1200 vfd->fops = &s5p_mfc_fops;
1201 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1202 vfd->release = video_device_release;
1203 vfd->lock = &dev->mfc_mutex;
1204 vfd->v4l2_dev = &dev->v4l2_dev;
1205 vfd->vfl_dir = VFL_DIR_M2M;
1206 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1207 dev->vfd_enc = vfd;
1208 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1209 if (ret) {
1210 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1211 video_device_release(vfd);
1212 goto err_enc_reg;
1213 }
1214 v4l2_info(&dev->v4l2_dev,
1215 "encoder registered as /dev/video%d\n", vfd->num);
1216 video_set_drvdata(vfd, dev);
1217 platform_set_drvdata(pdev, dev);
1218
1219 dev->hw_lock = 0;
1220 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1221 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1222 atomic_set(&dev->watchdog_cnt, 0);
1223 init_timer(&dev->watchdog_timer);
1224 dev->watchdog_timer.data = (unsigned long)dev;
1225 dev->watchdog_timer.function = s5p_mfc_watchdog;
1226
1227 /* Initialize HW ops and commands based on MFC version */
1228 s5p_mfc_init_hw_ops(dev);
1229 s5p_mfc_init_hw_cmds(dev);
1230 s5p_mfc_init_regs(dev);
1231
1232 pr_debug("%s--\n", __func__);
1233 return 0;
1234
1235 /* Deinit MFC if probe had failed */
1236 err_enc_reg:
1237 video_device_release(dev->vfd_enc);
1238 err_enc_alloc:
1239 video_unregister_device(dev->vfd_dec);
1240 err_dec_reg:
1241 video_device_release(dev->vfd_dec);
1242 err_dec_alloc:
1243 v4l2_device_unregister(&dev->v4l2_dev);
1244 err_v4l2_dev_reg:
1245 s5p_mfc_release_firmware(dev);
1246 err_alloc_fw:
1247 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1248 err_mem_init_ctx_1:
1249 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1250 err_res:
1251 s5p_mfc_final_pm(dev);
1252
1253 pr_debug("%s-- with error\n", __func__);
1254 return ret;
1255
1256 }
1257
1258 /* Remove the driver */
1259 static int s5p_mfc_remove(struct platform_device *pdev)
1260 {
1261 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1262
1263 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1264
1265 del_timer_sync(&dev->watchdog_timer);
1266 flush_workqueue(dev->watchdog_workqueue);
1267 destroy_workqueue(dev->watchdog_workqueue);
1268
1269 video_unregister_device(dev->vfd_enc);
1270 video_unregister_device(dev->vfd_dec);
1271 v4l2_device_unregister(&dev->v4l2_dev);
1272 s5p_mfc_release_firmware(dev);
1273 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1274 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1275 if (pdev->dev.of_node) {
1276 put_device(dev->mem_dev_l);
1277 put_device(dev->mem_dev_r);
1278 }
1279
1280 s5p_mfc_final_pm(dev);
1281 return 0;
1282 }
1283
1284 #ifdef CONFIG_PM_SLEEP
1285
1286 static int s5p_mfc_suspend(struct device *dev)
1287 {
1288 struct platform_device *pdev = to_platform_device(dev);
1289 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1290 int ret;
1291
1292 if (m_dev->num_inst == 0)
1293 return 0;
1294
1295 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1296 mfc_err("Error: going to suspend for a second time\n");
1297 return -EIO;
1298 }
1299
1300 /* Check if we're processing then wait if it necessary. */
1301 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1302 /* Try and lock the HW */
1303 /* Wait on the interrupt waitqueue */
1304 ret = wait_event_interruptible_timeout(m_dev->queue,
1305 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1306 if (ret == 0) {
1307 mfc_err("Waiting for hardware to finish timed out\n");
1308 clear_bit(0, &m_dev->enter_suspend);
1309 return -EIO;
1310 }
1311 }
1312
1313 ret = s5p_mfc_sleep(m_dev);
1314 if (ret) {
1315 clear_bit(0, &m_dev->enter_suspend);
1316 clear_bit(0, &m_dev->hw_lock);
1317 }
1318 return ret;
1319 }
1320
1321 static int s5p_mfc_resume(struct device *dev)
1322 {
1323 struct platform_device *pdev = to_platform_device(dev);
1324 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1325
1326 if (m_dev->num_inst == 0)
1327 return 0;
1328 return s5p_mfc_wakeup(m_dev);
1329 }
1330 #endif
1331
1332 #ifdef CONFIG_PM
1333 static int s5p_mfc_runtime_suspend(struct device *dev)
1334 {
1335 struct platform_device *pdev = to_platform_device(dev);
1336 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1337
1338 atomic_set(&m_dev->pm.power, 0);
1339 return 0;
1340 }
1341
1342 static int s5p_mfc_runtime_resume(struct device *dev)
1343 {
1344 struct platform_device *pdev = to_platform_device(dev);
1345 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1346
1347 atomic_set(&m_dev->pm.power, 1);
1348 return 0;
1349 }
1350 #endif
1351
1352 /* Power management */
1353 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1354 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1355 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1356 NULL)
1357 };
1358
1359 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1360 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1361 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1362 .dsc = DESC_BUF_SIZE,
1363 .shm = SHARED_BUF_SIZE,
1364 };
1365
1366 static struct s5p_mfc_buf_size buf_size_v5 = {
1367 .fw = MAX_FW_SIZE,
1368 .cpb = MAX_CPB_SIZE,
1369 .priv = &mfc_buf_size_v5,
1370 };
1371
1372 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1373 .base = MFC_BASE_ALIGN_ORDER,
1374 };
1375
1376 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1377 .version = MFC_VERSION,
1378 .version_bit = MFC_V5_BIT,
1379 .port_num = MFC_NUM_PORTS,
1380 .buf_size = &buf_size_v5,
1381 .buf_align = &mfc_buf_align_v5,
1382 .fw_name[0] = "s5p-mfc.fw",
1383 };
1384
1385 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1386 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1387 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1388 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1389 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1390 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1391 };
1392
1393 static struct s5p_mfc_buf_size buf_size_v6 = {
1394 .fw = MAX_FW_SIZE_V6,
1395 .cpb = MAX_CPB_SIZE_V6,
1396 .priv = &mfc_buf_size_v6,
1397 };
1398
1399 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1400 .base = 0,
1401 };
1402
1403 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1404 .version = MFC_VERSION_V6,
1405 .version_bit = MFC_V6_BIT,
1406 .port_num = MFC_NUM_PORTS_V6,
1407 .buf_size = &buf_size_v6,
1408 .buf_align = &mfc_buf_align_v6,
1409 .fw_name[0] = "s5p-mfc-v6.fw",
1410 /*
1411 * v6-v2 firmware contains bug fixes and interface change
1412 * for init buffer command
1413 */
1414 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1415 };
1416
1417 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1418 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1419 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1420 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1421 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1422 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1423 };
1424
1425 static struct s5p_mfc_buf_size buf_size_v7 = {
1426 .fw = MAX_FW_SIZE_V7,
1427 .cpb = MAX_CPB_SIZE_V7,
1428 .priv = &mfc_buf_size_v7,
1429 };
1430
1431 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1432 .base = 0,
1433 };
1434
1435 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1436 .version = MFC_VERSION_V7,
1437 .version_bit = MFC_V7_BIT,
1438 .port_num = MFC_NUM_PORTS_V7,
1439 .buf_size = &buf_size_v7,
1440 .buf_align = &mfc_buf_align_v7,
1441 .fw_name[0] = "s5p-mfc-v7.fw",
1442 };
1443
1444 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1445 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1446 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1447 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1448 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1449 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1450 };
1451
1452 static struct s5p_mfc_buf_size buf_size_v8 = {
1453 .fw = MAX_FW_SIZE_V8,
1454 .cpb = MAX_CPB_SIZE_V8,
1455 .priv = &mfc_buf_size_v8,
1456 };
1457
1458 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1459 .base = 0,
1460 };
1461
1462 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1463 .version = MFC_VERSION_V8,
1464 .version_bit = MFC_V8_BIT,
1465 .port_num = MFC_NUM_PORTS_V8,
1466 .buf_size = &buf_size_v8,
1467 .buf_align = &mfc_buf_align_v8,
1468 .fw_name[0] = "s5p-mfc-v8.fw",
1469 };
1470
1471 static const struct platform_device_id mfc_driver_ids[] = {
1472 {
1473 .name = "s5p-mfc",
1474 .driver_data = (unsigned long)&mfc_drvdata_v5,
1475 }, {
1476 .name = "s5p-mfc-v5",
1477 .driver_data = (unsigned long)&mfc_drvdata_v5,
1478 }, {
1479 .name = "s5p-mfc-v6",
1480 .driver_data = (unsigned long)&mfc_drvdata_v6,
1481 }, {
1482 .name = "s5p-mfc-v7",
1483 .driver_data = (unsigned long)&mfc_drvdata_v7,
1484 }, {
1485 .name = "s5p-mfc-v8",
1486 .driver_data = (unsigned long)&mfc_drvdata_v8,
1487 },
1488 {},
1489 };
1490 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1491
1492 static const struct of_device_id exynos_mfc_match[] = {
1493 {
1494 .compatible = "samsung,mfc-v5",
1495 .data = &mfc_drvdata_v5,
1496 }, {
1497 .compatible = "samsung,mfc-v6",
1498 .data = &mfc_drvdata_v6,
1499 }, {
1500 .compatible = "samsung,mfc-v7",
1501 .data = &mfc_drvdata_v7,
1502 }, {
1503 .compatible = "samsung,mfc-v8",
1504 .data = &mfc_drvdata_v8,
1505 },
1506 {},
1507 };
1508 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1509
1510 static void *mfc_get_drv_data(struct platform_device *pdev)
1511 {
1512 struct s5p_mfc_variant *driver_data = NULL;
1513
1514 if (pdev->dev.of_node) {
1515 const struct of_device_id *match;
1516 match = of_match_node(exynos_mfc_match,
1517 pdev->dev.of_node);
1518 if (match)
1519 driver_data = (struct s5p_mfc_variant *)match->data;
1520 } else {
1521 driver_data = (struct s5p_mfc_variant *)
1522 platform_get_device_id(pdev)->driver_data;
1523 }
1524 return driver_data;
1525 }
1526
1527 static struct platform_driver s5p_mfc_driver = {
1528 .probe = s5p_mfc_probe,
1529 .remove = s5p_mfc_remove,
1530 .id_table = mfc_driver_ids,
1531 .driver = {
1532 .name = S5P_MFC_NAME,
1533 .pm = &s5p_mfc_pm_ops,
1534 .of_match_table = exynos_mfc_match,
1535 },
1536 };
1537
1538 module_platform_driver(s5p_mfc_driver);
1539
1540 MODULE_LICENSE("GPL");
1541 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1542 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1543
Linux with added FPC-III support