drivers/pinctrl/sh-pfc/gpio.c

   1 /*
   2  * SuperH Pin Function Controller GPIO driver.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #include <linux/device.h>
  13 #include <linux/gpio.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/slab.h>
  18 #include <linux/spinlock.h>
  19
  20 #include "core.h"
  21
  22 struct sh_pfc_gpio_data_reg {
  23         const struct pinmux_data_reg *info;
  24         u32 shadow;
  25 };
  26
  27 struct sh_pfc_gpio_pin {
  28         u8 dbit;
  29         u8 dreg;
  30 };
  31
  32 struct sh_pfc_chip {
  33         struct sh_pfc                   *pfc;
  34         struct gpio_chip                gpio_chip;
  35
  36         struct sh_pfc_window            *mem;
  37         struct sh_pfc_gpio_data_reg     *regs;
  38         struct sh_pfc_gpio_pin          *pins;
  39 };
  40
  41 static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
  42 {
  43         return container_of(gc, struct sh_pfc_chip, gpio_chip);
  44 }
  45
  46 static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
  47 {
  48         return gpio_to_pfc_chip(gc)->pfc;
  49 }
  50
  51 static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
  52                               struct sh_pfc_gpio_data_reg **reg,
  53                               unsigned int *bit)
  54 {
  55         int idx = sh_pfc_get_pin_index(chip->pfc, offset);
  56         struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
  57
  58         *reg = &chip->regs[gpio_pin->dreg];
  59         *bit = gpio_pin->dbit;
  60 }
  61
  62 static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
  63                               const struct pinmux_data_reg *dreg)
  64 {
  65         phys_addr_t address = dreg->reg;
  66         void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
  67
  68         return sh_pfc_read_raw_reg(mem, dreg->reg_width);
  69 }
  70
  71 static void gpio_write_data_reg(struct sh_pfc_chip *chip,
  72                                 const struct pinmux_data_reg *dreg, u32 value)
  73 {
  74         phys_addr_t address = dreg->reg;
  75         void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
  76
  77         sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
  78 }
  79
  80 static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
  81 {
  82         struct sh_pfc *pfc = chip->pfc;
  83         struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
  84         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
  85         const struct pinmux_data_reg *dreg;
  86         unsigned int bit;
  87         unsigned int i;
  88
  89         for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
  90                 for (bit = 0; bit < dreg->reg_width; bit++) {
  91                         if (dreg->enum_ids[bit] == pin->enum_id) {
  92                                 gpio_pin->dreg = i;
  93                                 gpio_pin->dbit = bit;
  94                                 return;
  95                         }
  96                 }
  97         }
  98
  99         BUG();
 100 }
 101
 102 static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
 103 {
 104         struct sh_pfc *pfc = chip->pfc;
 105         const struct pinmux_data_reg *dreg;
 106         unsigned int i;
 107
 108         /* Count the number of data registers, allocate memory and initialize
 109          * them.
 110          */
 111         for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
 112                 ;
 113
 114         chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
 115                                   GFP_KERNEL);
 116         if (chip->regs == NULL)
 117                 return -ENOMEM;
 118
 119         for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
 120                 chip->regs[i].info = dreg;
 121                 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
 122         }
 123
 124         for (i = 0; i < pfc->info->nr_pins; i++) {
 125                 if (pfc->info->pins[i].enum_id == 0)
 126                         continue;
 127
 128                 gpio_setup_data_reg(chip, i);
 129         }
 130
 131         return 0;
 132 }
 133
 134 /* -----------------------------------------------------------------------------
 135  * Pin GPIOs
 136  */
 137
 138 static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
 139 {
 140         struct sh_pfc *pfc = gpio_to_pfc(gc);
 141         int idx = sh_pfc_get_pin_index(pfc, offset);
 142
 143         if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
 144                 return -EINVAL;
 145
 146         return pinctrl_request_gpio(offset);
 147 }
 148
 149 static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
 150 {
 151         return pinctrl_free_gpio(offset);
 152 }
 153
 154 static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
 155                                int value)
 156 {
 157         struct sh_pfc_gpio_data_reg *reg;
 158         unsigned int bit;
 159         unsigned int pos;
 160
 161         gpio_get_data_reg(chip, offset, &reg, &bit);
 162
 163         pos = reg->info->reg_width - (bit + 1);
 164
 165         if (value)
 166                 reg->shadow |= BIT(pos);
 167         else
 168                 reg->shadow &= ~BIT(pos);
 169
 170         gpio_write_data_reg(chip, reg->info, reg->shadow);
 171 }
 172
 173 static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
 174 {
 175         return pinctrl_gpio_direction_input(offset);
 176 }
 177
 178 static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
 179                                     int value)
 180 {
 181         gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
 182
 183         return pinctrl_gpio_direction_output(offset);
 184 }
 185
 186 static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
 187 {
 188         struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
 189         struct sh_pfc_gpio_data_reg *reg;
 190         unsigned int bit;
 191         unsigned int pos;
 192
 193         gpio_get_data_reg(chip, offset, &reg, &bit);
 194
 195         pos = reg->info->reg_width - (bit + 1);
 196
 197         return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
 198 }
 199
 200 static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
 201 {
 202         gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
 203 }
 204
 205 static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
 206 {
 207         struct sh_pfc *pfc = gpio_to_pfc(gc);
 208         unsigned int i, k;
 209
 210         for (i = 0; i < pfc->info->gpio_irq_size; i++) {
 211                 const short *gpios = pfc->info->gpio_irq[i].gpios;
 212
 213                 for (k = 0; gpios[k] >= 0; k++) {
 214                         if (gpios[k] == offset)
 215                                 goto found;
 216                 }
 217         }
 218
 219         return -ENOSYS;
 220
 221 found:
 222         return pfc->irqs[i];
 223 }
 224
 225 static int gpio_pin_setup(struct sh_pfc_chip *chip)
 226 {
 227         struct sh_pfc *pfc = chip->pfc;
 228         struct gpio_chip *gc = &chip->gpio_chip;
 229         int ret;
 230
 231         chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins *
 232                                   sizeof(*chip->pins), GFP_KERNEL);
 233         if (chip->pins == NULL)
 234                 return -ENOMEM;
 235
 236         ret = gpio_setup_data_regs(chip);
 237         if (ret < 0)
 238                 return ret;
 239
 240         gc->request = gpio_pin_request;
 241         gc->free = gpio_pin_free;
 242         gc->direction_input = gpio_pin_direction_input;
 243         gc->get = gpio_pin_get;
 244         gc->direction_output = gpio_pin_direction_output;
 245         gc->set = gpio_pin_set;
 246         gc->to_irq = gpio_pin_to_irq;
 247
 248         gc->label = pfc->info->name;
 249         gc->dev = pfc->dev;
 250         gc->owner = THIS_MODULE;
 251         gc->base = 0;
 252         gc->ngpio = pfc->nr_gpio_pins;
 253
 254         return 0;
 255 }
 256
 257 /* -----------------------------------------------------------------------------
 258  * Function GPIOs
 259  */
 260
 261 #ifdef CONFIG_SUPERH
 262 static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
 263 {
 264         static bool __print_once;
 265         struct sh_pfc *pfc = gpio_to_pfc(gc);
 266         unsigned int mark = pfc->info->func_gpios[offset].enum_id;
 267         unsigned long flags;
 268         int ret;
 269
 270         if (!__print_once) {
 271                 dev_notice(pfc->dev,
 272                            "Use of GPIO API for function requests is deprecated."
 273                            " Convert to pinctrl\n");
 274                 __print_once = true;
 275         }
 276
 277         if (mark == 0)
 278                 return -EINVAL;
 279
 280         spin_lock_irqsave(&pfc->lock, flags);
 281         ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
 282         spin_unlock_irqrestore(&pfc->lock, flags);
 283
 284         return ret;
 285 }
 286
 287 static int gpio_function_setup(struct sh_pfc_chip *chip)
 288 {
 289         struct sh_pfc *pfc = chip->pfc;
 290         struct gpio_chip *gc = &chip->gpio_chip;
 291
 292         gc->request = gpio_function_request;
 293
 294         gc->label = pfc->info->name;
 295         gc->owner = THIS_MODULE;
 296         gc->base = pfc->nr_gpio_pins;
 297         gc->ngpio = pfc->info->nr_func_gpios;
 298
 299         return 0;
 300 }
 301 #endif
 302
 303 /* -----------------------------------------------------------------------------
 304  * Register/unregister
 305  */
 306
 307 static struct sh_pfc_chip *
 308 sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
 309                     struct sh_pfc_window *mem)
 310 {
 311         struct sh_pfc_chip *chip;
 312         int ret;
 313
 314         chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
 315         if (unlikely(!chip))
 316                 return ERR_PTR(-ENOMEM);
 317
 318         chip->mem = mem;
 319         chip->pfc = pfc;
 320
 321         ret = setup(chip);
 322         if (ret < 0)
 323                 return ERR_PTR(ret);
 324
 325         ret = gpiochip_add(&chip->gpio_chip);
 326         if (unlikely(ret < 0))
 327                 return ERR_PTR(ret);
 328
 329         dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
 330                  chip->gpio_chip.label, chip->gpio_chip.base,
 331                  chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
 332
 333         return chip;
 334 }
 335
 336 int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 337 {
 338         struct sh_pfc_chip *chip;
 339         phys_addr_t address;
 340         unsigned int i;
 341
 342         if (pfc->info->data_regs == NULL)
 343                 return 0;
 344
 345         /* Find the memory window that contain the GPIO registers. Boards that
 346          * register a separate GPIO device will not supply a memory resource
 347          * that covers the data registers. In that case don't try to handle
 348          * GPIOs.
 349          */
 350         address = pfc->info->data_regs[0].reg;
 351         for (i = 0; i < pfc->num_windows; ++i) {
 352                 struct sh_pfc_window *window = &pfc->windows[i];
 353
 354                 if (address >= window->phys &&
 355                     address < window->phys + window->size)
 356                         break;
 357         }
 358
 359         if (i == pfc->num_windows)
 360                 return 0;
 361
 362         /* If we have IRQ resources make sure their number is correct. */
 363         if (pfc->num_irqs != pfc->info->gpio_irq_size) {
 364                 dev_err(pfc->dev, "invalid number of IRQ resources\n");
 365                 return -EINVAL;
 366         }
 367
 368         /* Register the real GPIOs chip. */
 369         chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
 370         if (IS_ERR(chip))
 371                 return PTR_ERR(chip);
 372
 373         pfc->gpio = chip;
 374
 375         if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
 376                 return 0;
 377
 378 #ifdef CONFIG_SUPERH
 379         /*
 380          * Register the GPIO to pin mappings. As pins with GPIO ports
 381          * must come first in the ranges, skip the pins without GPIO
 382          * ports by stopping at the first range that contains such a
 383          * pin.
 384          */
 385         for (i = 0; i < pfc->nr_ranges; ++i) {
 386                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 387                 int ret;
 388
 389                 if (range->start >= pfc->nr_gpio_pins)
 390                         break;
 391
 392                 ret = gpiochip_add_pin_range(&chip->gpio_chip,
 393                         dev_name(pfc->dev), range->start, range->start,
 394                         range->end - range->start + 1);
 395                 if (ret < 0)
 396                         return ret;
 397         }
 398
 399         /* Register the function GPIOs chip. */
 400         if (pfc->info->nr_func_gpios == 0)
 401                 return 0;
 402
 403         chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
 404         if (IS_ERR(chip))
 405                 return PTR_ERR(chip);
 406
 407         pfc->func = chip;
 408 #endif /* CONFIG_SUPERH */
 409
 410         return 0;
 411 }
 412
 413 int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
 414 {
 415         gpiochip_remove(&pfc->gpio->gpio_chip);
 416 #ifdef CONFIG_SUPERH
 417         gpiochip_remove(&pfc->func->gpio_chip);
 418 #endif
 419         return 0;
 420 }