drivers/pinctrl/sh-pfc/pfc-r8a7791.c

   1 /*
   2  * r8a7791 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2
   8  * as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12
  13 #include "core.h"
  14 #include "sh_pfc.h"
  15
  16 #define PORT_GP_26(bank, fn, sfx)                                       \
  17         PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
  18         PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
  19         PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
  20         PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
  21         PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
  22         PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
  23         PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
  24         PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
  25         PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
  26         PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
  27         PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
  28         PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
  29         PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
  30
  31 #define CPU_ALL_PORT(fn, sfx)                                           \
  32         PORT_GP_32(0, fn, sfx),                                         \
  33         PORT_GP_26(1, fn, sfx),                                         \
  34         PORT_GP_32(2, fn, sfx),                                         \
  35         PORT_GP_32(3, fn, sfx),                                         \
  36         PORT_GP_32(4, fn, sfx),                                         \
  37         PORT_GP_32(5, fn, sfx),                                         \
  38         PORT_GP_32(6, fn, sfx),                                         \
  39         PORT_GP_26(7, fn, sfx)
  40
  41 enum {
  42         PINMUX_RESERVED = 0,
  43
  44         PINMUX_DATA_BEGIN,
  45         GP_ALL(DATA),
  46         PINMUX_DATA_END,
  47
  48         PINMUX_FUNCTION_BEGIN,
  49         GP_ALL(FN),
  50
  51         /* GPSR0 */
  52         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  53         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  54         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  55         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  56         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  57         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  58
  59         /* GPSR1 */
  60         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  61         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  62         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  63         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  64         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  65         FN_IP3_21_20,
  66
  67         /* GPSR2 */
  68         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  69         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  70         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  71         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  72         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  73         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  74         FN_IP6_5_3, FN_IP6_7_6,
  75
  76         /* GPSR3 */
  77         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  78         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  79         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  80         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  81         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  82         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  83         FN_IP9_18_17,
  84
  85         /* GPSR4 */
  86         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  87         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  88         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  89         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  90         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  91         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  92         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  93         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  94
  95         /* GPSR5 */
  96         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  97         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  98         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  99         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
 100         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
 101         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
 102         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
 103
 104         /* GPSR6 */
 105         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
 106         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
 107         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
 108         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
 109         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
 110         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
 111         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
 112         FN_USB1_OVC, FN_DU0_DOTCLKIN,
 113
 114         /* GPSR7 */
 115         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 116         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 117         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 118         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 119         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 120         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 121
 122         /* IPSR0 */
 123         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 124         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 125         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
 126         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 127         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 128         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 129
 130         /* IPSR1 */
 131         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
 132         FN_A9, FN_MSIOF1_SS2, FN_SDA0,
 133         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 134         FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
 135         FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
 136         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 137         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 138         FN_A15, FN_BPFCLK_C,
 139         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 140         FN_A17, FN_DACK2_B, FN_SDA0_C,
 141         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 142
 143         /* IPSR2 */
 144         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 145         FN_A20, FN_SPCLK,
 146         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 147         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 148         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 149         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 150         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 151         FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
 152         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
 153         FN_EX_CS1_N, FN_MSIOF2_SCK,
 154         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 155         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 156
 157         /* IPSR3 */
 158         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 159         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 160         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 161         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 162         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 163         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 164         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 165         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 166         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 167         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 168         FN_DACK0, FN_DRACK0, FN_REMOCON,
 169         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 170         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 171         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 172         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 173
 174         /* IPSR4 */
 175         FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
 176         FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
 177         FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 178         FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
 179         FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 180         FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
 181         FN_GLO_Q1_D, FN_HCTS1_N_E,
 182         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 183         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 184         FN_SSI_SCK4, FN_GLO_SS_D,
 185         FN_SSI_WS4, FN_GLO_RFON_D,
 186         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 187         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 188         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 189
 190         /* IPSR5 */
 191         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 192         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 193         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 194         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 195         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 196         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 197         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 198         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 199         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 200         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 201         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 202         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 203         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 204         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 205         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 206
 207         /* IPSR6 */
 208         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 209         FN_SCIF_CLK, FN_BPFCLK_E,
 210         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 211         FN_SCIFA2_RXD, FN_FMIN_E,
 212         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 213         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 214         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 215         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 216         FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 217         FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 218         FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
 219         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
 220         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 221         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 222
 223         /* IPSR7 */
 224         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 225         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 226         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 227         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 228         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 229         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 230         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 231         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 232         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 233         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 234         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 235         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 236         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 237         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 238         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 239         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 240         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 241         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 242
 243         /* IPSR8 */
 244         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 245         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 246         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 247         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 248         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 249         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 250         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 251         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 252         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 253         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 254         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 255         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 256         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 257         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 258         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 259         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 260         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 261
 262         /* IPSR9 */
 263         FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
 264         FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 265         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 266         FN_DU1_DOTCLKOUT0, FN_QCLK,
 267         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 268         FN_TX3_B, FN_SCL2_B, FN_PWM4,
 269         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 270         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 271         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 272         FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
 273         FN_DU1_DISP, FN_QPOLA,
 274         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 275         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 276         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 277         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 278         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 279         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 280         FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
 281         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 282
 283         /* IPSR10 */
 284         FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
 285         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 286         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
 287         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 288         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
 289         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 290         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 291         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 292         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 293         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 294         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 295         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 296         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 297         FN_TS_SDATA0_C, FN_ATACS11_N,
 298         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 299         FN_TS_SCK0_C, FN_ATAG1_N,
 300         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 301         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 302         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
 303
 304         /* IPSR11 */
 305         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
 306         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
 307         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 308         FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 309         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 310         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 311         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 312         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 313         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 314         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 315         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 316         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 317         FN_VI1_DATA7, FN_AVB_MDC,
 318         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
 319         FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
 320
 321         /* IPSR12 */
 322         FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
 323         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
 324         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 325         FN_SCL2_D, FN_MSIOF1_RXD_E,
 326         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
 327         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 328         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 329         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 330         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 331         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 332         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 333         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 334         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 335         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 336         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 337         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 338         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 339
 340         /* IPSR13 */
 341         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 342         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 343         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 344         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 345         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 346         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 347         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 348         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 349         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 350         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 351         FN_SCIFA5_TXD_B, FN_TX3_C,
 352         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 353         FN_SCIFA5_RXD_B, FN_RX3_C,
 354         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 355         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 356         FN_SD1_DATA3, FN_IERX_B,
 357         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
 358
 359         /* IPSR14 */
 360         FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
 361         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 362         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 363         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 364         FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 365         FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 366         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 367         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 368         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 369         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 370         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 371         FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
 372         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 373         FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
 374
 375         /* IPSR15 */
 376         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 377         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 378         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 379         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 380         FN_PWM5_B, FN_SCIFA3_TXD_C,
 381         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 382         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 383         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 384         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 385         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 386         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 387         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 388         FN_TCLK2, FN_VI1_DATA3_C,
 389         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 390         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 391
 392         /* IPSR16 */
 393         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 394         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 395         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
 396         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 397         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 398
 399         /* MOD_SEL */
 400         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 401         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 402         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 403         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 404         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 405         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 406         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 407         FN_SEL_QSP_0, FN_SEL_QSP_1,
 408         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 409         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 410         FN_SEL_HSCIF1_4,
 411         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 412         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 413         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 414         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 415         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 416
 417         /* MOD_SEL2 */
 418         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 419         FN_SEL_SCIF0_4,
 420         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 421         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 422         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 423         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 424         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 425         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 426         FN_SEL_ADG_0, FN_SEL_ADG_1,
 427         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 428         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 429         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 430         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 431         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 432         FN_SEL_SIM_0, FN_SEL_SIM_1,
 433         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 434
 435         /* MOD_SEL3 */
 436         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 437         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 438         FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
 439         FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
 440         FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
 441         FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
 442         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 443         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 444         FN_SEL_MMC_0, FN_SEL_MMC_1,
 445         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 446         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 447         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
 448         FN_SEL_IIC1_4,
 449         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 450
 451         /* MOD_SEL4 */
 452         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 453         FN_SEL_SOF1_4,
 454         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 455         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 456         FN_SEL_RAD_0, FN_SEL_RAD_1,
 457         FN_SEL_RCN_0, FN_SEL_RCN_1,
 458         FN_SEL_RSP_0, FN_SEL_RSP_1,
 459         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 460         FN_SEL_SCIF2_4,
 461         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 462         FN_SEL_SOF2_4,
 463         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 464         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 465         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 466         PINMUX_FUNCTION_END,
 467
 468         PINMUX_MARK_BEGIN,
 469
 470         EX_CS0_N_MARK, RD_N_MARK,
 471
 472         AUDIO_CLKA_MARK,
 473
 474         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 475         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 476         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 477
 478         SD1_CLK_MARK,
 479
 480         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 481         DU0_DOTCLKIN_MARK,
 482
 483         /* IPSR0 */
 484         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 485         D6_MARK, D7_MARK, D8_MARK,
 486         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 487         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
 488         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 489         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 490         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 491
 492         /* IPSR1 */
 493         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
 494         A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
 495         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 496         A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
 497         A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
 498         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 499         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 500         A15_MARK, BPFCLK_C_MARK,
 501         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 502         A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
 503         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 504
 505         /* IPSR2 */
 506         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 507         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 508         A20_MARK, SPCLK_MARK,
 509         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 510         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 511         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 512         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 513         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 514         RX1_MARK, SCIFA1_RXD_MARK,
 515         CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
 516         CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
 517         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 518         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 519         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 520         ATAG0_N_MARK, EX_WAIT1_MARK,
 521
 522         /* IPSR3 */
 523         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 524         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 525         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 526         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 527         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 528         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 529         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 530         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 531         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 532         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 533         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 534         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 535         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 536         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 537         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 538         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 539         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 540         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 541
 542         /* IPSR4 */
 543         SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
 544         SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
 545         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 546         SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
 547         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 548         SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
 549         SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
 550         SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 551         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 552         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 553         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 554         SSI_SCK4_MARK, GLO_SS_D_MARK,
 555         SSI_WS4_MARK, GLO_RFON_D_MARK,
 556         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 557         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 558         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 559
 560         /* IPSR5 */
 561         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 562         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 563         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 564         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 565         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 566         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 567         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 568         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 569         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 570         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 571         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 572         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 573         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 574         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 575         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 576
 577         /* IPSR6 */
 578         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 579         SCIF_CLK_MARK, BPFCLK_E_MARK,
 580         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 581         SCIFA2_RXD_MARK, FMIN_E_MARK,
 582         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 583         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 584         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 585         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 586         IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 587         IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
 588         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 589         IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
 590         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 591         SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
 592         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 593         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 594         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 595         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 596
 597         /* IPSR7 */
 598         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 599         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 600         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 601         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 602         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 603         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 604         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 605         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 606         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 607         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 608         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 609         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 610         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 611         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 612         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 613         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 614         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 615         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 616
 617         /* IPSR8 */
 618         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 619         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 620         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 621         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 622         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 623         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 624         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 625         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 626         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 627         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 628         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 629         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 630         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 631         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 632         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 633         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 634         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 635         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 636
 637         /* IPSR9 */
 638         DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 639         DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
 640         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 641         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 642         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 643         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 644         TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
 645         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 646         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 647         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 648         CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
 649         DU1_DISP_MARK, QPOLA_MARK,
 650         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 651         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 652         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 653         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 654         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 655         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 656         VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
 657         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 658
 659         /* IPSR10 */
 660         VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
 661         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 662         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
 663         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 664         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
 665         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 666         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 667         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 668         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 669         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 670         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 671         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 672         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 673         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 674         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 675         TS_SCK0_C_MARK, ATAG1_N_MARK,
 676         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 677         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 678         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
 679
 680         /* IPSR11 */
 681         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
 682         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
 683         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 684         SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 685         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 686         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 687         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 688         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 689         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 690         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 691         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 692         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 693         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 694         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 695         VI1_DATA7_MARK, AVB_MDC_MARK,
 696         ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
 697         ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
 698
 699         /* IPSR12 */
 700         ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
 701         ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
 702         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 703         SCL2_D_MARK, MSIOF1_RXD_E_MARK,
 704         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 705         SDA2_D_MARK, MSIOF1_SCK_E_MARK,
 706         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 707         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 708         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 709         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 710         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 711         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 712         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 713         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 714         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 715         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 716         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 717         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 718
 719         /* IPSR13 */
 720         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 721         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 722         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 723         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 724         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 725         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 726         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 727         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 728         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 729         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 730         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 731         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 732         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 733         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 734         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 735         SD1_DATA3_MARK, IERX_B_MARK,
 736         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
 737
 738         /* IPSR14 */
 739         SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
 740         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 741         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 742         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 743         SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
 744         SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
 745         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 746         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 747         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 748         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 749         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 750         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 751         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 752         VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
 753         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 754         VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
 755
 756         /* IPSR15 */
 757         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 758         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 759         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 760         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 761         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 762         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 763         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 764         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 765         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 766         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 767         TCLK1_MARK, VI1_DATA1_C_MARK,
 768         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 769         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 770         TCLK2_MARK, VI1_DATA3_C_MARK,
 771         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 772         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 773         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 774         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 775
 776         /* IPSR16 */
 777         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 778         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 779         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 780         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 781         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
 782         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 783         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 784         PINMUX_MARK_END,
 785 };
 786
 787 static const u16 pinmux_data[] = {
 788         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 789
 790         PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
 791         PINMUX_DATA(RD_N_MARK, FN_RD_N),
 792         PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
 793         PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
 794         PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
 795         PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
 796         PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
 797         PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
 798         PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
 799         PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
 800         PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
 801         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 802         PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
 803         PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
 804         PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
 805         PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
 806         PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
 807
 808         /* IPSR0 */
 809         PINMUX_IPSR_DATA(IP0_0, D0),
 810         PINMUX_IPSR_DATA(IP0_1, D1),
 811         PINMUX_IPSR_DATA(IP0_2, D2),
 812         PINMUX_IPSR_DATA(IP0_3, D3),
 813         PINMUX_IPSR_DATA(IP0_4, D4),
 814         PINMUX_IPSR_DATA(IP0_5, D5),
 815         PINMUX_IPSR_DATA(IP0_6, D6),
 816         PINMUX_IPSR_DATA(IP0_7, D7),
 817         PINMUX_IPSR_DATA(IP0_8, D8),
 818         PINMUX_IPSR_DATA(IP0_9, D9),
 819         PINMUX_IPSR_DATA(IP0_10, D10),
 820         PINMUX_IPSR_DATA(IP0_11, D11),
 821         PINMUX_IPSR_DATA(IP0_12, D12),
 822         PINMUX_IPSR_DATA(IP0_13, D13),
 823         PINMUX_IPSR_DATA(IP0_14, D14),
 824         PINMUX_IPSR_DATA(IP0_15, D15),
 825         PINMUX_IPSR_DATA(IP0_18_16, A0),
 826         PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 827         PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 828         PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2),
 829         PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
 830         PINMUX_IPSR_DATA(IP0_20_19, A1),
 831         PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 832         PINMUX_IPSR_DATA(IP0_22_21, A2),
 833         PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 834         PINMUX_IPSR_DATA(IP0_24_23, A3),
 835         PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 836         PINMUX_IPSR_DATA(IP0_26_25, A4),
 837         PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 838         PINMUX_IPSR_DATA(IP0_28_27, A5),
 839         PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 840         PINMUX_IPSR_DATA(IP0_30_29, A6),
 841         PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 842
 843         /* IPSR1 */
 844         PINMUX_IPSR_DATA(IP1_1_0, A7),
 845         PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 846         PINMUX_IPSR_DATA(IP1_3_2, A8),
 847         PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 848         PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0),
 849         PINMUX_IPSR_DATA(IP1_5_4, A9),
 850         PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 851         PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0),
 852         PINMUX_IPSR_DATA(IP1_7_6, A10),
 853         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 854         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 855         PINMUX_IPSR_DATA(IP1_10_8, A11),
 856         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 857         PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3),
 858         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 859         PINMUX_IPSR_DATA(IP1_13_11, A12),
 860         PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
 861         PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3),
 862         PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 863         PINMUX_IPSR_DATA(IP1_16_14, A13),
 864         PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 865         PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
 866         PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 867         PINMUX_IPSR_DATA(IP1_19_17, A14),
 868         PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 869         PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
 870         PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
 871         PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 872         PINMUX_IPSR_DATA(IP1_22_20, A15),
 873         PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
 874         PINMUX_IPSR_DATA(IP1_25_23, A16),
 875         PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
 876         PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
 877         PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 878         PINMUX_IPSR_DATA(IP1_28_26, A17),
 879         PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
 880         PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2),
 881         PINMUX_IPSR_DATA(IP1_31_29, A18),
 882         PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
 883         PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 884         PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 885
 886         /* IPSR2 */
 887         PINMUX_IPSR_DATA(IP2_2_0, A19),
 888         PINMUX_IPSR_DATA(IP2_2_0, DACK1),
 889         PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 890         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 891         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
 892         PINMUX_IPSR_DATA(IP2_2_0, A20),
 893         PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
 894         PINMUX_IPSR_DATA(IP2_6_5, A21),
 895         PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 896         PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 897         PINMUX_IPSR_DATA(IP2_9_7, A22),
 898         PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
 899         PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
 900         PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
 901         PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 902         PINMUX_IPSR_DATA(IP2_12_10, A23),
 903         PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
 904         PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
 905         PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
 906         PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 907         PINMUX_IPSR_DATA(IP2_15_13, A24),
 908         PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
 909         PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
 910         PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
 911         PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 912         PINMUX_IPSR_DATA(IP2_18_16, A25),
 913         PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
 914         PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
 915         PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
 916         PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
 917         PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 918         PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
 919         PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 920         PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0),
 921         PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
 922         PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 923         PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0),
 924         PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
 925         PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 926         PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
 927         PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 928         PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 929         PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
 930         PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 931         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 932         PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
 933         PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
 934
 935         /* IPSR3 */
 936         PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
 937         PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
 938         PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 939         PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
 940         PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
 941         PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
 942         PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 943         PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 944         PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 945         PINMUX_IPSR_DATA(IP3_5_3, PWM1),
 946         PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
 947         PINMUX_IPSR_DATA(IP3_8_6, BS_N),
 948         PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
 949         PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 950         PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 951         PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 952         PINMUX_IPSR_DATA(IP3_8_6, PWM2),
 953         PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
 954         PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
 955         PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 956         PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
 957         PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 958         PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
 959         PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
 960         PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 961         PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 962         PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
 963         PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 964         PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 965         PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 966         PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
 967         PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 968         PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 969         PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
 970         PINMUX_IPSR_DATA(IP3_19_18, PWM3),
 971         PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
 972         PINMUX_IPSR_DATA(IP3_21_20, DACK0),
 973         PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
 974         PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
 975         PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
 976         PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 977         PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 978         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 979         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 980         PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
 981         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 982         PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 983         PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 984         PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 985         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 986         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 987         PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 988         PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 989         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 990         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 991         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 992
 993         /* IPSR4 */
 994         PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
 995         PINMUX_IPSR_MSEL(IP4_1_0, SCL0_B, SEL_IIC0_1),
 996         PINMUX_IPSR_MSEL(IP4_1_0, SCL7_B, SEL_IIC7_1),
 997         PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
 998         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
 999         PINMUX_IPSR_MSEL(IP4_4_2, SDA0_B, SEL_IIC0_1),
1000         PINMUX_IPSR_MSEL(IP4_4_2, SDA7_B, SEL_IIC7_1),
1001         PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1002         PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1003         PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1004         PINMUX_IPSR_MSEL(IP4_7_5, SCL1_B, SEL_IIC1_1),
1005         PINMUX_IPSR_MSEL(IP4_7_5, SCL8_B, SEL_IIC8_1),
1006         PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1007         PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1008         PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1009         PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1),
1010         PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1),
1011         PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1012         PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
1013         PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
1014         PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1015         PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1016         PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1017         PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
1018         PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1019         PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1020         PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1021         PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1022         PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1023         PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1024         PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1025         PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1026         PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1027         PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1028         PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1029         PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1030         PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1031         PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1032         PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1033         PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1034         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1035         PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1036         PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1037         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1038         PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1039
1040         /* IPSR5 */
1041         PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1042         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1043         PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1044         PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1045         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1046         PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1047         PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1048         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1049         PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1050         PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1051         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1052         PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1053         PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1054         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1055         PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1056         PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1057         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1058         PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1059         PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1060         PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1061         PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1062         PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1063         PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1064         PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1065         PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1066         PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1067         PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1068         PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1069         PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1070         PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1071         PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1072         PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1073         PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1074         PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1075         PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1076         PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1077         PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1078         PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1079         PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1080         PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1081         PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1082         PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1083         PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1084         PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1085         PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1086         PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1087         PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1088         PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1089         PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1090
1091         /* IPSR6 */
1092         PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1093         PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1094         PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1095         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1096         PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1097         PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1098         PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1099         PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1100         PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1101         PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1102         PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1103         PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1104         PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1105         PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
1106         PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1107         PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1108         PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1109         PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1110         PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1111         PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1112         PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1113         PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1114         PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1115         PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1116         PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1117         PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2),
1118         PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1119         PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1120         PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1121         PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1122         PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2),
1123         PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1124         PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1125         PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1126         PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1127         PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4),
1128         PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1129         PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1130         PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1131         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1132         PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4),
1133         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1134         PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1135         PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1136         PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1137         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1138         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1139         PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1140         PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1141         PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1142         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1143         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1144
1145         /* IPSR7 */
1146         PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1147         PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1148         PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1149         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1150         PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1151         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1152         PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1153         PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1154         PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1155         PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1156         PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1157         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1158         PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1159         PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1160         PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1161         PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1162         PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1163         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1164         PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1165         PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1166         PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1167         PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1168         PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1169         PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1170         PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1171         PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1172         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1173         PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1174         PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1175         PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1176         PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1177         PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1178         PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1179         PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1180         PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1181         PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1182         PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1183         PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1184         PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1185         PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1186         PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1187         PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1188         PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1189         PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1190         PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1191         PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1192         PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1193         PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1194         PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1195         PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1196         PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1197         PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1198         PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1199         PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1200
1201         /* IPSR8 */
1202         PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1203         PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1204         PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1205         PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1206         PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1207         PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1208         PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1209         PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1210         PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1211         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1212         PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1213         PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1214         PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1215         PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1216         PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1217         PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1218         PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1219         PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1220         PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1221         PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1222         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1223         PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1224         PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1225         PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1226         PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1227         PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1228         PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1229         PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1230         PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1231         PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1232         PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1233         PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1234         PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1235         PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1236         PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1237         PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1238         PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1239         PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1240         PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1241         PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1242         PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1243         PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1244         PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1245         PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1246         PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1247         PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1248         PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1249         PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1250         PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1251         PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1252         PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1253         PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1254         PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1255         PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1256         PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1257         PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1258
1259         /* IPSR9 */
1260         PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1261         PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1262         PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2),
1263         PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1264         PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1265         PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1266         PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1267         PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2),
1268         PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1269         PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1270         PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1271         PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1272         PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1273         PINMUX_IPSR_DATA(IP9_7, QCLK),
1274         PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1275         PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1276         PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1277         PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1278         PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1),
1279         PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1280         PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1281         PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1282         PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1283         PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1284         PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1285         PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1286         PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1287         PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1288         PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1),
1289         PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1290         PINMUX_IPSR_DATA(IP9_16, QPOLA),
1291         PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1292         PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1293         PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1294         PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1295         PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1296         PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1297         PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1298         PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1299         PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1300         PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1301         PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1302         PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1303         PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1304         PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1305         PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1306         PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1307         PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1308         PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1309         PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1310         PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1311         PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1312         PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1313         PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1314         PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0),
1315         PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1316         PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0),
1317         PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1318         PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1319         PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1320
1321         /* IPSR10 */
1322         PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1323         PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0),
1324         PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1325         PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0),
1326         PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1327         PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1328         PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1329         PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1330         PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1331         PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1332         PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1),
1333         PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1334         PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1335         PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1336         PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1337         PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1338         PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1339         PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1),
1340         PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1341         PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1342         PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1343         PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1344         PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1345         PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1346         PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1347         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1348         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1349         PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1350         PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1351         PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1352         PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1353         PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1354         PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1355         PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1356         PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1357         PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1358         PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1359         PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1360         PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1361         PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1362         PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1363         PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1364         PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1365         PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1366         PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1367         PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1368         PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1369         PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1370         PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1371         PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1372         PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1373         PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1374         PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1375         PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1376         PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1377         PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1378         PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1379         PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1380         PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1381         PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1382         PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1383         PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1384         PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3),
1385
1386         /* IPSR11 */
1387         PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1388         PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1389         PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1390         PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1391         PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3),
1392         PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1393         PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1394         PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1395         PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1396         PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1),
1397         PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1398         PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1399         PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1400         PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1401         PINMUX_IPSR_MSEL(IP11_8_6, SDA4_B, SEL_IIC4_1),
1402         PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1403         PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1404         PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1405         PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1406         PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1407         PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1408         PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1409         PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1410         PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1411         PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1412         PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1413         PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1414         PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1415         PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1416         PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1417         PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1418         PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1419         PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1420         PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1421         PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1422         PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1423         PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1424         PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1425         PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1426         PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1427         PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1428         PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1429         PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1430         PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1431         PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1432         PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1433         PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1434         PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1435         PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1436         PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1437         PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1438         PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1439         PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1440         PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2),
1441         PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1442         PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1443         PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2),
1444
1445         /* IPSR12 */
1446         PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1447         PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1448         PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0),
1449         PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0),
1450         PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1451         PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1452         PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0),
1453         PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0),
1454         PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1455         PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1456         PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1457         PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3),
1458         PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1459         PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1460         PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1461         PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1462         PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3),
1463         PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1464         PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1465         PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1466         PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1467         PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1468         PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1469         PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1470         PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1471         PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1472         PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1473         PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1474         PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1475         PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1476         PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1477         PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1478         PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1479         PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1480         PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1481         PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1482         PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1483         PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1484         PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1485         PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1486         PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1487         PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1488         PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1489         PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1490         PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1491         PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1492         PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1493         PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1494         PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1495         PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1496         PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1497
1498         /* IPSR13 */
1499         PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1500         PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1501         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1502         PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1503         PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1504         PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1505         PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1506         PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1507         PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1508         PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1509         PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1510         PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1511         PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1512         PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1513         PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1514         PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1515         PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1516         PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1517         PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1518         PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1519         PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1520         PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1521         PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1522         PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1523         PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1524         PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1525         PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1526         PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1527         PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1528         PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1529         PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1530         PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1531         PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1532         PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1533         PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1534         PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1535         PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1536         PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1537         PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1538         PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1539         PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1540         PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1541         PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1542         PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1543         PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1544         PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1545         PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1546         PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1547         PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1548         PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1549         PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1550         PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1551         PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1552         PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1553         PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1554         PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2),
1555
1556         /* IPSR14 */
1557         PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1558         PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1559         PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2),
1560         PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1561         PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1562         PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1563         PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1564         PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1565         PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1566         PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1567         PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1568         PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1569         PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1570         PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1571         PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1572         PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1573         PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1574         PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2),
1575         PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1576         PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1577         PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1578         PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1579         PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2),
1580         PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1581         PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1582         PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1583         PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1584         PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1585         PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1586         PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1587         PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1588         PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1589         PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1590         PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1591         PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1592         PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1593         PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1594         PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1595         PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1596         PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1597         PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1598         PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1599         PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1600         PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1601         PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1602         PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1603         PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1604         PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1605         PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2),
1606         PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1607         PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1608         PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1609         PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1610         PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1611         PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1612         PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2),
1613         PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1614
1615         /* IPSR15 */
1616         PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1617         PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1618         PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1619         PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1620         PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1621         PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1622         PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1623         PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1624         PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1625         PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1626         PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1627         PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1628         PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1629         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1630         PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1631         PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1632         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1633         PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1634         PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1635         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1636         PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1637         PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1638         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1639         PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1640         PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1641         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1642         PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1643         PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1644         PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1645         PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1646         PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1647         PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1648         PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1649         PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1650         PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1651         PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1652         PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1653         PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1654         PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1655         PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1656         PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1657         PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1658         PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1659         PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1660         PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1661         PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1662         PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1663         PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1664         PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1665         PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1666         PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1667
1668         /* IPSR16 */
1669         PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1670         PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1671         PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1672         PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1673         PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1674         PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1675         PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1676         PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1677         PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1678         PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1679         PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1680         PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1681         PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK),
1682         PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1683         PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1684         PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1685         PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1686         PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1687         PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1688         PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1689         PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1690         PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1691 };
1692
1693 static const struct sh_pfc_pin pinmux_pins[] = {
1694         PINMUX_GPIO_GP_ALL(),
1695 };
1696
1697 /* - Audio Clock ------------------------------------------------------------ */
1698 static const unsigned int audio_clk_a_pins[] = {
1699         /* CLK */
1700         RCAR_GP_PIN(2, 28),
1701 };
1702
1703 static const unsigned int audio_clk_a_mux[] = {
1704         AUDIO_CLKA_MARK,
1705 };
1706
1707 static const unsigned int audio_clk_b_pins[] = {
1708         /* CLK */
1709         RCAR_GP_PIN(2, 29),
1710 };
1711
1712 static const unsigned int audio_clk_b_mux[] = {
1713         AUDIO_CLKB_MARK,
1714 };
1715
1716 static const unsigned int audio_clk_b_b_pins[] = {
1717         /* CLK */
1718         RCAR_GP_PIN(7, 20),
1719 };
1720
1721 static const unsigned int audio_clk_b_b_mux[] = {
1722         AUDIO_CLKB_B_MARK,
1723 };
1724
1725 static const unsigned int audio_clk_c_pins[] = {
1726         /* CLK */
1727         RCAR_GP_PIN(2, 30),
1728 };
1729
1730 static const unsigned int audio_clk_c_mux[] = {
1731         AUDIO_CLKC_MARK,
1732 };
1733
1734 static const unsigned int audio_clkout_pins[] = {
1735         /* CLK */
1736         RCAR_GP_PIN(2, 31),
1737 };
1738
1739 static const unsigned int audio_clkout_mux[] = {
1740         AUDIO_CLKOUT_MARK,
1741 };
1742
1743 /* - CAN -------------------------------------------------------------------- */
1744
1745 static const unsigned int can0_data_pins[] = {
1746         /* TX, RX */
1747         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1748 };
1749
1750 static const unsigned int can0_data_mux[] = {
1751         CAN0_TX_MARK, CAN0_RX_MARK,
1752 };
1753
1754 static const unsigned int can0_data_b_pins[] = {
1755         /* TX, RX */
1756         RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1757 };
1758
1759 static const unsigned int can0_data_b_mux[] = {
1760         CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1761 };
1762
1763 static const unsigned int can0_data_c_pins[] = {
1764         /* TX, RX */
1765         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1766 };
1767
1768 static const unsigned int can0_data_c_mux[] = {
1769         CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1770 };
1771
1772 static const unsigned int can0_data_d_pins[] = {
1773         /* TX, RX */
1774         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1775 };
1776
1777 static const unsigned int can0_data_d_mux[] = {
1778         CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1779 };
1780
1781 static const unsigned int can0_data_e_pins[] = {
1782         /* TX, RX */
1783         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1784 };
1785
1786 static const unsigned int can0_data_e_mux[] = {
1787         CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1788 };
1789
1790 static const unsigned int can0_data_f_pins[] = {
1791         /* TX, RX */
1792         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1793 };
1794
1795 static const unsigned int can0_data_f_mux[] = {
1796         CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1797 };
1798
1799 static const unsigned int can1_data_pins[] = {
1800         /* TX, RX */
1801          RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1802 };
1803
1804 static const unsigned int can1_data_mux[] = {
1805         CAN1_TX_MARK, CAN1_RX_MARK,
1806 };
1807
1808 static const unsigned int can1_data_b_pins[] = {
1809         /* TX, RX */
1810         RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1811 };
1812
1813 static const unsigned int can1_data_b_mux[] = {
1814         CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1815 };
1816
1817 static const unsigned int can1_data_c_pins[] = {
1818         /* TX, RX */
1819         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1820 };
1821
1822 static const unsigned int can1_data_c_mux[] = {
1823         CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1824 };
1825
1826 static const unsigned int can1_data_d_pins[] = {
1827         /* TX, RX */
1828          RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1829 };
1830
1831 static const unsigned int can1_data_d_mux[] = {
1832         CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1833 };
1834
1835 static const unsigned int can_clk_pins[] = {
1836         /* CLK */
1837         RCAR_GP_PIN(7, 2),
1838 };
1839
1840 static const unsigned int can_clk_mux[] = {
1841         CAN_CLK_MARK,
1842 };
1843
1844 static const unsigned int can_clk_b_pins[] = {
1845         /* CLK */
1846         RCAR_GP_PIN(5, 21),
1847 };
1848
1849 static const unsigned int can_clk_b_mux[] = {
1850         CAN_CLK_B_MARK,
1851 };
1852
1853 static const unsigned int can_clk_c_pins[] = {
1854         /* CLK */
1855         RCAR_GP_PIN(4, 30),
1856 };
1857
1858 static const unsigned int can_clk_c_mux[] = {
1859         CAN_CLK_C_MARK,
1860 };
1861
1862 static const unsigned int can_clk_d_pins[] = {
1863         /* CLK */
1864         RCAR_GP_PIN(7, 19),
1865 };
1866
1867 static const unsigned int can_clk_d_mux[] = {
1868         CAN_CLK_D_MARK,
1869 };
1870
1871 /* - DU --------------------------------------------------------------------- */
1872 static const unsigned int du_rgb666_pins[] = {
1873         /* R[7:2], G[7:2], B[7:2] */
1874         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1875         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1876         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1877         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1878         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1879         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1880 };
1881 static const unsigned int du_rgb666_mux[] = {
1882         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1883         DU1_DR3_MARK, DU1_DR2_MARK,
1884         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1885         DU1_DG3_MARK, DU1_DG2_MARK,
1886         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1887         DU1_DB3_MARK, DU1_DB2_MARK,
1888 };
1889 static const unsigned int du_rgb888_pins[] = {
1890         /* R[7:0], G[7:0], B[7:0] */
1891         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1892         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1893         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
1894         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1895         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1896         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
1897         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1898         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1899         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1900 };
1901 static const unsigned int du_rgb888_mux[] = {
1902         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1903         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1904         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1905         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1906         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1907         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1908 };
1909 static const unsigned int du_clk_out_0_pins[] = {
1910         /* CLKOUT */
1911         RCAR_GP_PIN(3, 25),
1912 };
1913 static const unsigned int du_clk_out_0_mux[] = {
1914         DU1_DOTCLKOUT0_MARK
1915 };
1916 static const unsigned int du_clk_out_1_pins[] = {
1917         /* CLKOUT */
1918         RCAR_GP_PIN(3, 26),
1919 };
1920 static const unsigned int du_clk_out_1_mux[] = {
1921         DU1_DOTCLKOUT1_MARK
1922 };
1923 static const unsigned int du_sync_pins[] = {
1924         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1925         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1926 };
1927 static const unsigned int du_sync_mux[] = {
1928         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1929 };
1930 static const unsigned int du_oddf_pins[] = {
1931         /* EXDISP/EXODDF/EXCDE */
1932         RCAR_GP_PIN(3, 29),
1933 };
1934 static const unsigned int du_oddf_mux[] = {
1935         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1936 };
1937 static const unsigned int du_cde_pins[] = {
1938         /* CDE */
1939         RCAR_GP_PIN(3, 31),
1940 };
1941 static const unsigned int du_cde_mux[] = {
1942         DU1_CDE_MARK,
1943 };
1944 static const unsigned int du_disp_pins[] = {
1945         /* DISP */
1946         RCAR_GP_PIN(3, 30),
1947 };
1948 static const unsigned int du_disp_mux[] = {
1949         DU1_DISP_MARK,
1950 };
1951 static const unsigned int du0_clk_in_pins[] = {
1952         /* CLKIN */
1953         RCAR_GP_PIN(6, 31),
1954 };
1955 static const unsigned int du0_clk_in_mux[] = {
1956         DU0_DOTCLKIN_MARK
1957 };
1958 static const unsigned int du1_clk_in_pins[] = {
1959         /* CLKIN */
1960         RCAR_GP_PIN(3, 24),
1961 };
1962 static const unsigned int du1_clk_in_mux[] = {
1963         DU1_DOTCLKIN_MARK
1964 };
1965 static const unsigned int du1_clk_in_b_pins[] = {
1966         /* CLKIN */
1967         RCAR_GP_PIN(7, 19),
1968 };
1969 static const unsigned int du1_clk_in_b_mux[] = {
1970         DU1_DOTCLKIN_B_MARK,
1971 };
1972 static const unsigned int du1_clk_in_c_pins[] = {
1973         /* CLKIN */
1974         RCAR_GP_PIN(7, 20),
1975 };
1976 static const unsigned int du1_clk_in_c_mux[] = {
1977         DU1_DOTCLKIN_C_MARK,
1978 };
1979 /* - ETH -------------------------------------------------------------------- */
1980 static const unsigned int eth_link_pins[] = {
1981         /* LINK */
1982         RCAR_GP_PIN(5, 18),
1983 };
1984 static const unsigned int eth_link_mux[] = {
1985         ETH_LINK_MARK,
1986 };
1987 static const unsigned int eth_magic_pins[] = {
1988         /* MAGIC */
1989         RCAR_GP_PIN(5, 22),
1990 };
1991 static const unsigned int eth_magic_mux[] = {
1992         ETH_MAGIC_MARK,
1993 };
1994 static const unsigned int eth_mdio_pins[] = {
1995         /* MDC, MDIO */
1996         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1997 };
1998 static const unsigned int eth_mdio_mux[] = {
1999         ETH_MDC_MARK, ETH_MDIO_MARK,
2000 };
2001 static const unsigned int eth_rmii_pins[] = {
2002         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2003         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2004         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2005         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2006 };
2007 static const unsigned int eth_rmii_mux[] = {
2008         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2009         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2010 };
2011
2012 /* - HSCIF0 ----------------------------------------------------------------- */
2013 static const unsigned int hscif0_data_pins[] = {
2014         /* RX, TX */
2015         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2016 };
2017 static const unsigned int hscif0_data_mux[] = {
2018         HRX0_MARK, HTX0_MARK,
2019 };
2020 static const unsigned int hscif0_clk_pins[] = {
2021         /* SCK */
2022         RCAR_GP_PIN(7, 2),
2023 };
2024 static const unsigned int hscif0_clk_mux[] = {
2025         HSCK0_MARK,
2026 };
2027 static const unsigned int hscif0_ctrl_pins[] = {
2028         /* RTS, CTS */
2029         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2030 };
2031 static const unsigned int hscif0_ctrl_mux[] = {
2032         HRTS0_N_MARK, HCTS0_N_MARK,
2033 };
2034 static const unsigned int hscif0_data_b_pins[] = {
2035         /* RX, TX */
2036         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2037 };
2038 static const unsigned int hscif0_data_b_mux[] = {
2039         HRX0_B_MARK, HTX0_B_MARK,
2040 };
2041 static const unsigned int hscif0_ctrl_b_pins[] = {
2042         /* RTS, CTS */
2043         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2044 };
2045 static const unsigned int hscif0_ctrl_b_mux[] = {
2046         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2047 };
2048 static const unsigned int hscif0_data_c_pins[] = {
2049         /* RX, TX */
2050         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2051 };
2052 static const unsigned int hscif0_data_c_mux[] = {
2053         HRX0_C_MARK, HTX0_C_MARK,
2054 };
2055 static const unsigned int hscif0_clk_c_pins[] = {
2056         /* SCK */
2057         RCAR_GP_PIN(5, 31),
2058 };
2059 static const unsigned int hscif0_clk_c_mux[] = {
2060         HSCK0_C_MARK,
2061 };
2062 /* - HSCIF1 ----------------------------------------------------------------- */
2063 static const unsigned int hscif1_data_pins[] = {
2064         /* RX, TX */
2065         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2066 };
2067 static const unsigned int hscif1_data_mux[] = {
2068         HRX1_MARK, HTX1_MARK,
2069 };
2070 static const unsigned int hscif1_clk_pins[] = {
2071         /* SCK */
2072         RCAR_GP_PIN(7, 7),
2073 };
2074 static const unsigned int hscif1_clk_mux[] = {
2075         HSCK1_MARK,
2076 };
2077 static const unsigned int hscif1_ctrl_pins[] = {
2078         /* RTS, CTS */
2079         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2080 };
2081 static const unsigned int hscif1_ctrl_mux[] = {
2082         HRTS1_N_MARK, HCTS1_N_MARK,
2083 };
2084 static const unsigned int hscif1_data_b_pins[] = {
2085         /* RX, TX */
2086         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2087 };
2088 static const unsigned int hscif1_data_b_mux[] = {
2089         HRX1_B_MARK, HTX1_B_MARK,
2090 };
2091 static const unsigned int hscif1_data_c_pins[] = {
2092         /* RX, TX */
2093         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2094 };
2095 static const unsigned int hscif1_data_c_mux[] = {
2096         HRX1_C_MARK, HTX1_C_MARK,
2097 };
2098 static const unsigned int hscif1_clk_c_pins[] = {
2099         /* SCK */
2100         RCAR_GP_PIN(7, 16),
2101 };
2102 static const unsigned int hscif1_clk_c_mux[] = {
2103         HSCK1_C_MARK,
2104 };
2105 static const unsigned int hscif1_ctrl_c_pins[] = {
2106         /* RTS, CTS */
2107         RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2108 };
2109 static const unsigned int hscif1_ctrl_c_mux[] = {
2110         HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2111 };
2112 static const unsigned int hscif1_data_d_pins[] = {
2113         /* RX, TX */
2114         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2115 };
2116 static const unsigned int hscif1_data_d_mux[] = {
2117         HRX1_D_MARK, HTX1_D_MARK,
2118 };
2119 static const unsigned int hscif1_data_e_pins[] = {
2120         /* RX, TX */
2121         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2122 };
2123 static const unsigned int hscif1_data_e_mux[] = {
2124         HRX1_C_MARK, HTX1_C_MARK,
2125 };
2126 static const unsigned int hscif1_clk_e_pins[] = {
2127         /* SCK */
2128         RCAR_GP_PIN(2, 6),
2129 };
2130 static const unsigned int hscif1_clk_e_mux[] = {
2131         HSCK1_E_MARK,
2132 };
2133 static const unsigned int hscif1_ctrl_e_pins[] = {
2134         /* RTS, CTS */
2135         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2136 };
2137 static const unsigned int hscif1_ctrl_e_mux[] = {
2138         HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2139 };
2140 /* - HSCIF2 ----------------------------------------------------------------- */
2141 static const unsigned int hscif2_data_pins[] = {
2142         /* RX, TX */
2143         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2144 };
2145 static const unsigned int hscif2_data_mux[] = {
2146         HRX2_MARK, HTX2_MARK,
2147 };
2148 static const unsigned int hscif2_clk_pins[] = {
2149         /* SCK */
2150         RCAR_GP_PIN(4, 15),
2151 };
2152 static const unsigned int hscif2_clk_mux[] = {
2153         HSCK2_MARK,
2154 };
2155 static const unsigned int hscif2_ctrl_pins[] = {
2156         /* RTS, CTS */
2157         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2158 };
2159 static const unsigned int hscif2_ctrl_mux[] = {
2160         HRTS2_N_MARK, HCTS2_N_MARK,
2161 };
2162 static const unsigned int hscif2_data_b_pins[] = {
2163         /* RX, TX */
2164         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2165 };
2166 static const unsigned int hscif2_data_b_mux[] = {
2167         HRX2_B_MARK, HTX2_B_MARK,
2168 };
2169 static const unsigned int hscif2_ctrl_b_pins[] = {
2170         /* RTS, CTS */
2171         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2172 };
2173 static const unsigned int hscif2_ctrl_b_mux[] = {
2174         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2175 };
2176 static const unsigned int hscif2_data_c_pins[] = {
2177         /* RX, TX */
2178         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2179 };
2180 static const unsigned int hscif2_data_c_mux[] = {
2181         HRX2_C_MARK, HTX2_C_MARK,
2182 };
2183 static const unsigned int hscif2_clk_c_pins[] = {
2184         /* SCK */
2185         RCAR_GP_PIN(5, 31),
2186 };
2187 static const unsigned int hscif2_clk_c_mux[] = {
2188         HSCK2_C_MARK,
2189 };
2190 static const unsigned int hscif2_data_d_pins[] = {
2191         /* RX, TX */
2192         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2193 };
2194 static const unsigned int hscif2_data_d_mux[] = {
2195         HRX2_B_MARK, HTX2_D_MARK,
2196 };
2197 /* - I2C0 ------------------------------------------------------------------- */
2198 static const unsigned int i2c0_pins[] = {
2199         /* SCL, SDA */
2200         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2201 };
2202 static const unsigned int i2c0_mux[] = {
2203         SCL0_MARK, SDA0_MARK,
2204 };
2205 static const unsigned int i2c0_b_pins[] = {
2206         /* SCL, SDA */
2207         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2208 };
2209 static const unsigned int i2c0_b_mux[] = {
2210         SCL0_B_MARK, SDA0_B_MARK,
2211 };
2212 static const unsigned int i2c0_c_pins[] = {
2213         /* SCL, SDA */
2214         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2215 };
2216 static const unsigned int i2c0_c_mux[] = {
2217         SCL0_C_MARK, SDA0_C_MARK,
2218 };
2219 /* - I2C1 ------------------------------------------------------------------- */
2220 static const unsigned int i2c1_pins[] = {
2221         /* SCL, SDA */
2222         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2223 };
2224 static const unsigned int i2c1_mux[] = {
2225         SCL1_MARK, SDA1_MARK,
2226 };
2227 static const unsigned int i2c1_b_pins[] = {
2228         /* SCL, SDA */
2229         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2230 };
2231 static const unsigned int i2c1_b_mux[] = {
2232         SCL1_B_MARK, SDA1_B_MARK,
2233 };
2234 static const unsigned int i2c1_c_pins[] = {
2235         /* SCL, SDA */
2236         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2237 };
2238 static const unsigned int i2c1_c_mux[] = {
2239         SCL1_C_MARK, SDA1_C_MARK,
2240 };
2241 static const unsigned int i2c1_d_pins[] = {
2242         /* SCL, SDA */
2243         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2244 };
2245 static const unsigned int i2c1_d_mux[] = {
2246         SCL1_D_MARK, SDA1_D_MARK,
2247 };
2248 static const unsigned int i2c1_e_pins[] = {
2249         /* SCL, SDA */
2250         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2251 };
2252 static const unsigned int i2c1_e_mux[] = {
2253         SCL1_E_MARK, SDA1_E_MARK,
2254 };
2255 /* - I2C2 ------------------------------------------------------------------- */
2256 static const unsigned int i2c2_pins[] = {
2257         /* SCL, SDA */
2258         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2259 };
2260 static const unsigned int i2c2_mux[] = {
2261         SCL2_MARK, SDA2_MARK,
2262 };
2263 static const unsigned int i2c2_b_pins[] = {
2264         /* SCL, SDA */
2265         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2266 };
2267 static const unsigned int i2c2_b_mux[] = {
2268         SCL2_B_MARK, SDA2_B_MARK,
2269 };
2270 static const unsigned int i2c2_c_pins[] = {
2271         /* SCL, SDA */
2272         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2273 };
2274 static const unsigned int i2c2_c_mux[] = {
2275         SCL2_C_MARK, SDA2_C_MARK,
2276 };
2277 static const unsigned int i2c2_d_pins[] = {
2278         /* SCL, SDA */
2279         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2280 };
2281 static const unsigned int i2c2_d_mux[] = {
2282         SCL2_D_MARK, SDA2_D_MARK,
2283 };
2284 /* - I2C3 ------------------------------------------------------------------- */
2285 static const unsigned int i2c3_pins[] = {
2286         /* SCL, SDA */
2287         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2288 };
2289 static const unsigned int i2c3_mux[] = {
2290         SCL3_MARK, SDA3_MARK,
2291 };
2292 static const unsigned int i2c3_b_pins[] = {
2293         /* SCL, SDA */
2294         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2295 };
2296 static const unsigned int i2c3_b_mux[] = {
2297         SCL3_B_MARK, SDA3_B_MARK,
2298 };
2299 static const unsigned int i2c3_c_pins[] = {
2300         /* SCL, SDA */
2301         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2302 };
2303 static const unsigned int i2c3_c_mux[] = {
2304         SCL3_C_MARK, SDA3_C_MARK,
2305 };
2306 static const unsigned int i2c3_d_pins[] = {
2307         /* SCL, SDA */
2308         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2309 };
2310 static const unsigned int i2c3_d_mux[] = {
2311         SCL3_D_MARK, SDA3_D_MARK,
2312 };
2313 /* - I2C4 ------------------------------------------------------------------- */
2314 static const unsigned int i2c4_pins[] = {
2315         /* SCL, SDA */
2316         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2317 };
2318 static const unsigned int i2c4_mux[] = {
2319         SCL4_MARK, SDA4_MARK,
2320 };
2321 static const unsigned int i2c4_b_pins[] = {
2322         /* SCL, SDA */
2323         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2324 };
2325 static const unsigned int i2c4_b_mux[] = {
2326         SCL4_B_MARK, SDA4_B_MARK,
2327 };
2328 static const unsigned int i2c4_c_pins[] = {
2329         /* SCL, SDA */
2330         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2331 };
2332 static const unsigned int i2c4_c_mux[] = {
2333         SCL4_C_MARK, SDA4_C_MARK,
2334 };
2335 /* - I2C7 ------------------------------------------------------------------- */
2336 static const unsigned int i2c7_pins[] = {
2337         /* SCL, SDA */
2338         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2339 };
2340 static const unsigned int i2c7_mux[] = {
2341         SCL7_MARK, SDA7_MARK,
2342 };
2343 static const unsigned int i2c7_b_pins[] = {
2344         /* SCL, SDA */
2345         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2346 };
2347 static const unsigned int i2c7_b_mux[] = {
2348         SCL7_B_MARK, SDA7_B_MARK,
2349 };
2350 static const unsigned int i2c7_c_pins[] = {
2351         /* SCL, SDA */
2352         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2353 };
2354 static const unsigned int i2c7_c_mux[] = {
2355         SCL7_C_MARK, SDA7_C_MARK,
2356 };
2357 /* - I2C8 ------------------------------------------------------------------- */
2358 static const unsigned int i2c8_pins[] = {
2359         /* SCL, SDA */
2360         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2361 };
2362 static const unsigned int i2c8_mux[] = {
2363         SCL8_MARK, SDA8_MARK,
2364 };
2365 static const unsigned int i2c8_b_pins[] = {
2366         /* SCL, SDA */
2367         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2368 };
2369 static const unsigned int i2c8_b_mux[] = {
2370         SCL8_B_MARK, SDA8_B_MARK,
2371 };
2372 static const unsigned int i2c8_c_pins[] = {
2373         /* SCL, SDA */
2374         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2375 };
2376 static const unsigned int i2c8_c_mux[] = {
2377         SCL8_C_MARK, SDA8_C_MARK,
2378 };
2379 /* - INTC ------------------------------------------------------------------- */
2380 static const unsigned int intc_irq0_pins[] = {
2381         /* IRQ */
2382         RCAR_GP_PIN(7, 10),
2383 };
2384 static const unsigned int intc_irq0_mux[] = {
2385         IRQ0_MARK,
2386 };
2387 static const unsigned int intc_irq1_pins[] = {
2388         /* IRQ */
2389         RCAR_GP_PIN(7, 11),
2390 };
2391 static const unsigned int intc_irq1_mux[] = {
2392         IRQ1_MARK,
2393 };
2394 static const unsigned int intc_irq2_pins[] = {
2395         /* IRQ */
2396         RCAR_GP_PIN(7, 12),
2397 };
2398 static const unsigned int intc_irq2_mux[] = {
2399         IRQ2_MARK,
2400 };
2401 static const unsigned int intc_irq3_pins[] = {
2402         /* IRQ */
2403         RCAR_GP_PIN(7, 13),
2404 };
2405 static const unsigned int intc_irq3_mux[] = {
2406         IRQ3_MARK,
2407 };
2408 /* - MLB+ ------------------------------------------------------------------- */
2409 static const unsigned int mlb_3pin_pins[] = {
2410         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2411 };
2412 static const unsigned int mlb_3pin_mux[] = {
2413         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2414 };
2415 /* - MMCIF ------------------------------------------------------------------ */
2416 static const unsigned int mmc_data1_pins[] = {
2417         /* D[0] */
2418         RCAR_GP_PIN(6, 18),
2419 };
2420 static const unsigned int mmc_data1_mux[] = {
2421         MMC_D0_MARK,
2422 };
2423 static const unsigned int mmc_data4_pins[] = {
2424         /* D[0:3] */
2425         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2426         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2427 };
2428 static const unsigned int mmc_data4_mux[] = {
2429         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2430 };
2431 static const unsigned int mmc_data8_pins[] = {
2432         /* D[0:7] */
2433         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2434         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2435         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2436         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2437 };
2438 static const unsigned int mmc_data8_mux[] = {
2439         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2440         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2441 };
2442 static const unsigned int mmc_ctrl_pins[] = {
2443         /* CLK, CMD */
2444         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2445 };
2446 static const unsigned int mmc_ctrl_mux[] = {
2447         MMC_CLK_MARK, MMC_CMD_MARK,
2448 };
2449 /* - MSIOF0 ----------------------------------------------------------------- */
2450 static const unsigned int msiof0_clk_pins[] = {
2451         /* SCK */
2452         RCAR_GP_PIN(6, 24),
2453 };
2454 static const unsigned int msiof0_clk_mux[] = {
2455         MSIOF0_SCK_MARK,
2456 };
2457 static const unsigned int msiof0_sync_pins[] = {
2458         /* SYNC */
2459         RCAR_GP_PIN(6, 25),
2460 };
2461 static const unsigned int msiof0_sync_mux[] = {
2462         MSIOF0_SYNC_MARK,
2463 };
2464 static const unsigned int msiof0_ss1_pins[] = {
2465         /* SS1 */
2466         RCAR_GP_PIN(6, 28),
2467 };
2468 static const unsigned int msiof0_ss1_mux[] = {
2469         MSIOF0_SS1_MARK,
2470 };
2471 static const unsigned int msiof0_ss2_pins[] = {
2472         /* SS2 */
2473         RCAR_GP_PIN(6, 29),
2474 };
2475 static const unsigned int msiof0_ss2_mux[] = {
2476         MSIOF0_SS2_MARK,
2477 };
2478 static const unsigned int msiof0_rx_pins[] = {
2479         /* RXD */
2480         RCAR_GP_PIN(6, 27),
2481 };
2482 static const unsigned int msiof0_rx_mux[] = {
2483         MSIOF0_RXD_MARK,
2484 };
2485 static const unsigned int msiof0_tx_pins[] = {
2486         /* TXD */
2487         RCAR_GP_PIN(6, 26),
2488 };
2489 static const unsigned int msiof0_tx_mux[] = {
2490         MSIOF0_TXD_MARK,
2491 };
2492
2493 static const unsigned int msiof0_clk_b_pins[] = {
2494         /* SCK */
2495         RCAR_GP_PIN(0, 16),
2496 };
2497 static const unsigned int msiof0_clk_b_mux[] = {
2498         MSIOF0_SCK_B_MARK,
2499 };
2500 static const unsigned int msiof0_sync_b_pins[] = {
2501         /* SYNC */
2502         RCAR_GP_PIN(0, 17),
2503 };
2504 static const unsigned int msiof0_sync_b_mux[] = {
2505         MSIOF0_SYNC_B_MARK,
2506 };
2507 static const unsigned int msiof0_ss1_b_pins[] = {
2508         /* SS1 */
2509         RCAR_GP_PIN(0, 18),
2510 };
2511 static const unsigned int msiof0_ss1_b_mux[] = {
2512         MSIOF0_SS1_B_MARK,
2513 };
2514 static const unsigned int msiof0_ss2_b_pins[] = {
2515         /* SS2 */
2516         RCAR_GP_PIN(0, 19),
2517 };
2518 static const unsigned int msiof0_ss2_b_mux[] = {
2519         MSIOF0_SS2_B_MARK,
2520 };
2521 static const unsigned int msiof0_rx_b_pins[] = {
2522         /* RXD */
2523         RCAR_GP_PIN(0, 21),
2524 };
2525 static const unsigned int msiof0_rx_b_mux[] = {
2526         MSIOF0_RXD_B_MARK,
2527 };
2528 static const unsigned int msiof0_tx_b_pins[] = {
2529         /* TXD */
2530         RCAR_GP_PIN(0, 20),
2531 };
2532 static const unsigned int msiof0_tx_b_mux[] = {
2533         MSIOF0_TXD_B_MARK,
2534 };
2535
2536 static const unsigned int msiof0_clk_c_pins[] = {
2537         /* SCK */
2538         RCAR_GP_PIN(5, 26),
2539 };
2540 static const unsigned int msiof0_clk_c_mux[] = {
2541         MSIOF0_SCK_C_MARK,
2542 };
2543 static const unsigned int msiof0_sync_c_pins[] = {
2544         /* SYNC */
2545         RCAR_GP_PIN(5, 25),
2546 };
2547 static const unsigned int msiof0_sync_c_mux[] = {
2548         MSIOF0_SYNC_C_MARK,
2549 };
2550 static const unsigned int msiof0_ss1_c_pins[] = {
2551         /* SS1 */
2552         RCAR_GP_PIN(5, 27),
2553 };
2554 static const unsigned int msiof0_ss1_c_mux[] = {
2555         MSIOF0_SS1_C_MARK,
2556 };
2557 static const unsigned int msiof0_ss2_c_pins[] = {
2558         /* SS2 */
2559         RCAR_GP_PIN(5, 28),
2560 };
2561 static const unsigned int msiof0_ss2_c_mux[] = {
2562         MSIOF0_SS2_C_MARK,
2563 };
2564 static const unsigned int msiof0_rx_c_pins[] = {
2565         /* RXD */
2566         RCAR_GP_PIN(5, 29),
2567 };
2568 static const unsigned int msiof0_rx_c_mux[] = {
2569         MSIOF0_RXD_C_MARK,
2570 };
2571 static const unsigned int msiof0_tx_c_pins[] = {
2572         /* TXD */
2573         RCAR_GP_PIN(5, 30),
2574 };
2575 static const unsigned int msiof0_tx_c_mux[] = {
2576         MSIOF0_TXD_C_MARK,
2577 };
2578 /* - MSIOF1 ----------------------------------------------------------------- */
2579 static const unsigned int msiof1_clk_pins[] = {
2580         /* SCK */
2581         RCAR_GP_PIN(0, 22),
2582 };
2583 static const unsigned int msiof1_clk_mux[] = {
2584         MSIOF1_SCK_MARK,
2585 };
2586 static const unsigned int msiof1_sync_pins[] = {
2587         /* SYNC */
2588         RCAR_GP_PIN(0, 23),
2589 };
2590 static const unsigned int msiof1_sync_mux[] = {
2591         MSIOF1_SYNC_MARK,
2592 };
2593 static const unsigned int msiof1_ss1_pins[] = {
2594         /* SS1 */
2595         RCAR_GP_PIN(0, 24),
2596 };
2597 static const unsigned int msiof1_ss1_mux[] = {
2598         MSIOF1_SS1_MARK,
2599 };
2600 static const unsigned int msiof1_ss2_pins[] = {
2601         /* SS2 */
2602         RCAR_GP_PIN(0, 25),
2603 };
2604 static const unsigned int msiof1_ss2_mux[] = {
2605         MSIOF1_SS2_MARK,
2606 };
2607 static const unsigned int msiof1_rx_pins[] = {
2608         /* RXD */
2609         RCAR_GP_PIN(0, 27),
2610 };
2611 static const unsigned int msiof1_rx_mux[] = {
2612         MSIOF1_RXD_MARK,
2613 };
2614 static const unsigned int msiof1_tx_pins[] = {
2615         /* TXD */
2616         RCAR_GP_PIN(0, 26),
2617 };
2618 static const unsigned int msiof1_tx_mux[] = {
2619         MSIOF1_TXD_MARK,
2620 };
2621
2622 static const unsigned int msiof1_clk_b_pins[] = {
2623         /* SCK */
2624         RCAR_GP_PIN(2, 29),
2625 };
2626 static const unsigned int msiof1_clk_b_mux[] = {
2627         MSIOF1_SCK_B_MARK,
2628 };
2629 static const unsigned int msiof1_sync_b_pins[] = {
2630         /* SYNC */
2631         RCAR_GP_PIN(2, 30),
2632 };
2633 static const unsigned int msiof1_sync_b_mux[] = {
2634         MSIOF1_SYNC_B_MARK,
2635 };
2636 static const unsigned int msiof1_ss1_b_pins[] = {
2637         /* SS1 */
2638         RCAR_GP_PIN(2, 31),
2639 };
2640 static const unsigned int msiof1_ss1_b_mux[] = {
2641         MSIOF1_SS1_B_MARK,
2642 };
2643 static const unsigned int msiof1_ss2_b_pins[] = {
2644         /* SS2 */
2645         RCAR_GP_PIN(7, 16),
2646 };
2647 static const unsigned int msiof1_ss2_b_mux[] = {
2648         MSIOF1_SS2_B_MARK,
2649 };
2650 static const unsigned int msiof1_rx_b_pins[] = {
2651         /* RXD */
2652         RCAR_GP_PIN(7, 18),
2653 };
2654 static const unsigned int msiof1_rx_b_mux[] = {
2655         MSIOF1_RXD_B_MARK,
2656 };
2657 static const unsigned int msiof1_tx_b_pins[] = {
2658         /* TXD */
2659         RCAR_GP_PIN(7, 17),
2660 };
2661 static const unsigned int msiof1_tx_b_mux[] = {
2662         MSIOF1_TXD_B_MARK,
2663 };
2664
2665 static const unsigned int msiof1_clk_c_pins[] = {
2666         /* SCK */
2667         RCAR_GP_PIN(2, 15),
2668 };
2669 static const unsigned int msiof1_clk_c_mux[] = {
2670         MSIOF1_SCK_C_MARK,
2671 };
2672 static const unsigned int msiof1_sync_c_pins[] = {
2673         /* SYNC */
2674         RCAR_GP_PIN(2, 16),
2675 };
2676 static const unsigned int msiof1_sync_c_mux[] = {
2677         MSIOF1_SYNC_C_MARK,
2678 };
2679 static const unsigned int msiof1_rx_c_pins[] = {
2680         /* RXD */
2681         RCAR_GP_PIN(2, 18),
2682 };
2683 static const unsigned int msiof1_rx_c_mux[] = {
2684         MSIOF1_RXD_C_MARK,
2685 };
2686 static const unsigned int msiof1_tx_c_pins[] = {
2687         /* TXD */
2688         RCAR_GP_PIN(2, 17),
2689 };
2690 static const unsigned int msiof1_tx_c_mux[] = {
2691         MSIOF1_TXD_C_MARK,
2692 };
2693
2694 static const unsigned int msiof1_clk_d_pins[] = {
2695         /* SCK */
2696         RCAR_GP_PIN(0, 28),
2697 };
2698 static const unsigned int msiof1_clk_d_mux[] = {
2699         MSIOF1_SCK_D_MARK,
2700 };
2701 static const unsigned int msiof1_sync_d_pins[] = {
2702         /* SYNC */
2703         RCAR_GP_PIN(0, 30),
2704 };
2705 static const unsigned int msiof1_sync_d_mux[] = {
2706         MSIOF1_SYNC_D_MARK,
2707 };
2708 static const unsigned int msiof1_ss1_d_pins[] = {
2709         /* SS1 */
2710         RCAR_GP_PIN(0, 29),
2711 };
2712 static const unsigned int msiof1_ss1_d_mux[] = {
2713         MSIOF1_SS1_D_MARK,
2714 };
2715 static const unsigned int msiof1_rx_d_pins[] = {
2716         /* RXD */
2717         RCAR_GP_PIN(0, 27),
2718 };
2719 static const unsigned int msiof1_rx_d_mux[] = {
2720         MSIOF1_RXD_D_MARK,
2721 };
2722 static const unsigned int msiof1_tx_d_pins[] = {
2723         /* TXD */
2724         RCAR_GP_PIN(0, 26),
2725 };
2726 static const unsigned int msiof1_tx_d_mux[] = {
2727         MSIOF1_TXD_D_MARK,
2728 };
2729
2730 static const unsigned int msiof1_clk_e_pins[] = {
2731         /* SCK */
2732         RCAR_GP_PIN(5, 18),
2733 };
2734 static const unsigned int msiof1_clk_e_mux[] = {
2735         MSIOF1_SCK_E_MARK,
2736 };
2737 static const unsigned int msiof1_sync_e_pins[] = {
2738         /* SYNC */
2739         RCAR_GP_PIN(5, 19),
2740 };
2741 static const unsigned int msiof1_sync_e_mux[] = {
2742         MSIOF1_SYNC_E_MARK,
2743 };
2744 static const unsigned int msiof1_rx_e_pins[] = {
2745         /* RXD */
2746         RCAR_GP_PIN(5, 17),
2747 };
2748 static const unsigned int msiof1_rx_e_mux[] = {
2749         MSIOF1_RXD_E_MARK,
2750 };
2751 static const unsigned int msiof1_tx_e_pins[] = {
2752         /* TXD */
2753         RCAR_GP_PIN(5, 20),
2754 };
2755 static const unsigned int msiof1_tx_e_mux[] = {
2756         MSIOF1_TXD_E_MARK,
2757 };
2758 /* - MSIOF2 ----------------------------------------------------------------- */
2759 static const unsigned int msiof2_clk_pins[] = {
2760         /* SCK */
2761         RCAR_GP_PIN(1, 13),
2762 };
2763 static const unsigned int msiof2_clk_mux[] = {
2764         MSIOF2_SCK_MARK,
2765 };
2766 static const unsigned int msiof2_sync_pins[] = {
2767         /* SYNC */
2768         RCAR_GP_PIN(1, 14),
2769 };
2770 static const unsigned int msiof2_sync_mux[] = {
2771         MSIOF2_SYNC_MARK,
2772 };
2773 static const unsigned int msiof2_ss1_pins[] = {
2774         /* SS1 */
2775         RCAR_GP_PIN(1, 17),
2776 };
2777 static const unsigned int msiof2_ss1_mux[] = {
2778         MSIOF2_SS1_MARK,
2779 };
2780 static const unsigned int msiof2_ss2_pins[] = {
2781         /* SS2 */
2782         RCAR_GP_PIN(1, 18),
2783 };
2784 static const unsigned int msiof2_ss2_mux[] = {
2785         MSIOF2_SS2_MARK,
2786 };
2787 static const unsigned int msiof2_rx_pins[] = {
2788         /* RXD */
2789         RCAR_GP_PIN(1, 16),
2790 };
2791 static const unsigned int msiof2_rx_mux[] = {
2792         MSIOF2_RXD_MARK,
2793 };
2794 static const unsigned int msiof2_tx_pins[] = {
2795         /* TXD */
2796         RCAR_GP_PIN(1, 15),
2797 };
2798 static const unsigned int msiof2_tx_mux[] = {
2799         MSIOF2_TXD_MARK,
2800 };
2801
2802 static const unsigned int msiof2_clk_b_pins[] = {
2803         /* SCK */
2804         RCAR_GP_PIN(3, 0),
2805 };
2806 static const unsigned int msiof2_clk_b_mux[] = {
2807         MSIOF2_SCK_B_MARK,
2808 };
2809 static const unsigned int msiof2_sync_b_pins[] = {
2810         /* SYNC */
2811         RCAR_GP_PIN(3, 1),
2812 };
2813 static const unsigned int msiof2_sync_b_mux[] = {
2814         MSIOF2_SYNC_B_MARK,
2815 };
2816 static const unsigned int msiof2_ss1_b_pins[] = {
2817         /* SS1 */
2818         RCAR_GP_PIN(3, 8),
2819 };
2820 static const unsigned int msiof2_ss1_b_mux[] = {
2821         MSIOF2_SS1_B_MARK,
2822 };
2823 static const unsigned int msiof2_ss2_b_pins[] = {
2824         /* SS2 */
2825         RCAR_GP_PIN(3, 9),
2826 };
2827 static const unsigned int msiof2_ss2_b_mux[] = {
2828         MSIOF2_SS2_B_MARK,
2829 };
2830 static const unsigned int msiof2_rx_b_pins[] = {
2831         /* RXD */
2832         RCAR_GP_PIN(3, 17),
2833 };
2834 static const unsigned int msiof2_rx_b_mux[] = {
2835         MSIOF2_RXD_B_MARK,
2836 };
2837 static const unsigned int msiof2_tx_b_pins[] = {
2838         /* TXD */
2839         RCAR_GP_PIN(3, 16),
2840 };
2841 static const unsigned int msiof2_tx_b_mux[] = {
2842         MSIOF2_TXD_B_MARK,
2843 };
2844
2845 static const unsigned int msiof2_clk_c_pins[] = {
2846         /* SCK */
2847         RCAR_GP_PIN(2, 2),
2848 };
2849 static const unsigned int msiof2_clk_c_mux[] = {
2850         MSIOF2_SCK_C_MARK,
2851 };
2852 static const unsigned int msiof2_sync_c_pins[] = {
2853         /* SYNC */
2854         RCAR_GP_PIN(2, 3),
2855 };
2856 static const unsigned int msiof2_sync_c_mux[] = {
2857         MSIOF2_SYNC_C_MARK,
2858 };
2859 static const unsigned int msiof2_rx_c_pins[] = {
2860         /* RXD */
2861         RCAR_GP_PIN(2, 5),
2862 };
2863 static const unsigned int msiof2_rx_c_mux[] = {
2864         MSIOF2_RXD_C_MARK,
2865 };
2866 static const unsigned int msiof2_tx_c_pins[] = {
2867         /* TXD */
2868         RCAR_GP_PIN(2, 4),
2869 };
2870 static const unsigned int msiof2_tx_c_mux[] = {
2871         MSIOF2_TXD_C_MARK,
2872 };
2873
2874 static const unsigned int msiof2_clk_d_pins[] = {
2875         /* SCK */
2876         RCAR_GP_PIN(2, 14),
2877 };
2878 static const unsigned int msiof2_clk_d_mux[] = {
2879         MSIOF2_SCK_D_MARK,
2880 };
2881 static const unsigned int msiof2_sync_d_pins[] = {
2882         /* SYNC */
2883         RCAR_GP_PIN(2, 15),
2884 };
2885 static const unsigned int msiof2_sync_d_mux[] = {
2886         MSIOF2_SYNC_D_MARK,
2887 };
2888 static const unsigned int msiof2_ss1_d_pins[] = {
2889         /* SS1 */
2890         RCAR_GP_PIN(2, 17),
2891 };
2892 static const unsigned int msiof2_ss1_d_mux[] = {
2893         MSIOF2_SS1_D_MARK,
2894 };
2895 static const unsigned int msiof2_ss2_d_pins[] = {
2896         /* SS2 */
2897         RCAR_GP_PIN(2, 19),
2898 };
2899 static const unsigned int msiof2_ss2_d_mux[] = {
2900         MSIOF2_SS2_D_MARK,
2901 };
2902 static const unsigned int msiof2_rx_d_pins[] = {
2903         /* RXD */
2904         RCAR_GP_PIN(2, 18),
2905 };
2906 static const unsigned int msiof2_rx_d_mux[] = {
2907         MSIOF2_RXD_D_MARK,
2908 };
2909 static const unsigned int msiof2_tx_d_pins[] = {
2910         /* TXD */
2911         RCAR_GP_PIN(2, 16),
2912 };
2913 static const unsigned int msiof2_tx_d_mux[] = {
2914         MSIOF2_TXD_D_MARK,
2915 };
2916
2917 static const unsigned int msiof2_clk_e_pins[] = {
2918         /* SCK */
2919         RCAR_GP_PIN(7, 15),
2920 };
2921 static const unsigned int msiof2_clk_e_mux[] = {
2922         MSIOF2_SCK_E_MARK,
2923 };
2924 static const unsigned int msiof2_sync_e_pins[] = {
2925         /* SYNC */
2926         RCAR_GP_PIN(7, 16),
2927 };
2928 static const unsigned int msiof2_sync_e_mux[] = {
2929         MSIOF2_SYNC_E_MARK,
2930 };
2931 static const unsigned int msiof2_rx_e_pins[] = {
2932         /* RXD */
2933         RCAR_GP_PIN(7, 14),
2934 };
2935 static const unsigned int msiof2_rx_e_mux[] = {
2936         MSIOF2_RXD_E_MARK,
2937 };
2938 static const unsigned int msiof2_tx_e_pins[] = {
2939         /* TXD */
2940         RCAR_GP_PIN(7, 13),
2941 };
2942 static const unsigned int msiof2_tx_e_mux[] = {
2943         MSIOF2_TXD_E_MARK,
2944 };
2945 /* - PWM -------------------------------------------------------------------- */
2946 static const unsigned int pwm0_pins[] = {
2947         RCAR_GP_PIN(6, 14),
2948 };
2949 static const unsigned int pwm0_mux[] = {
2950         PWM0_MARK,
2951 };
2952 static const unsigned int pwm0_b_pins[] = {
2953         RCAR_GP_PIN(5, 30),
2954 };
2955 static const unsigned int pwm0_b_mux[] = {
2956         PWM0_B_MARK,
2957 };
2958 static const unsigned int pwm1_pins[] = {
2959         RCAR_GP_PIN(1, 17),
2960 };
2961 static const unsigned int pwm1_mux[] = {
2962         PWM1_MARK,
2963 };
2964 static const unsigned int pwm1_b_pins[] = {
2965         RCAR_GP_PIN(6, 15),
2966 };
2967 static const unsigned int pwm1_b_mux[] = {
2968         PWM1_B_MARK,
2969 };
2970 static const unsigned int pwm2_pins[] = {
2971         RCAR_GP_PIN(1, 18),
2972 };
2973 static const unsigned int pwm2_mux[] = {
2974         PWM2_MARK,
2975 };
2976 static const unsigned int pwm2_b_pins[] = {
2977         RCAR_GP_PIN(0, 16),
2978 };
2979 static const unsigned int pwm2_b_mux[] = {
2980         PWM2_B_MARK,
2981 };
2982 static const unsigned int pwm3_pins[] = {
2983         RCAR_GP_PIN(1, 24),
2984 };
2985 static const unsigned int pwm3_mux[] = {
2986         PWM3_MARK,
2987 };
2988 static const unsigned int pwm4_pins[] = {
2989         RCAR_GP_PIN(3, 26),
2990 };
2991 static const unsigned int pwm4_mux[] = {
2992         PWM4_MARK,
2993 };
2994 static const unsigned int pwm4_b_pins[] = {
2995         RCAR_GP_PIN(3, 31),
2996 };
2997 static const unsigned int pwm4_b_mux[] = {
2998         PWM4_B_MARK,
2999 };
3000 static const unsigned int pwm5_pins[] = {
3001         RCAR_GP_PIN(7, 21),
3002 };
3003 static const unsigned int pwm5_mux[] = {
3004         PWM5_MARK,
3005 };
3006 static const unsigned int pwm5_b_pins[] = {
3007         RCAR_GP_PIN(7, 20),
3008 };
3009 static const unsigned int pwm5_b_mux[] = {
3010         PWM5_B_MARK,
3011 };
3012 static const unsigned int pwm6_pins[] = {
3013         RCAR_GP_PIN(7, 22),
3014 };
3015 static const unsigned int pwm6_mux[] = {
3016         PWM6_MARK,
3017 };
3018 /* - QSPI ------------------------------------------------------------------- */
3019 static const unsigned int qspi_ctrl_pins[] = {
3020         /* SPCLK, SSL */
3021         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3022 };
3023 static const unsigned int qspi_ctrl_mux[] = {
3024         SPCLK_MARK, SSL_MARK,
3025 };
3026 static const unsigned int qspi_data2_pins[] = {
3027         /* MOSI_IO0, MISO_IO1 */
3028         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3029 };
3030 static const unsigned int qspi_data2_mux[] = {
3031         MOSI_IO0_MARK, MISO_IO1_MARK,
3032 };
3033 static const unsigned int qspi_data4_pins[] = {
3034         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3035         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3036         RCAR_GP_PIN(1, 8),
3037 };
3038 static const unsigned int qspi_data4_mux[] = {
3039         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3040 };
3041
3042 static const unsigned int qspi_ctrl_b_pins[] = {
3043         /* SPCLK, SSL */
3044         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3045 };
3046 static const unsigned int qspi_ctrl_b_mux[] = {
3047         SPCLK_B_MARK, SSL_B_MARK,
3048 };
3049 static const unsigned int qspi_data2_b_pins[] = {
3050         /* MOSI_IO0, MISO_IO1 */
3051         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3052 };
3053 static const unsigned int qspi_data2_b_mux[] = {
3054         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3055 };
3056 static const unsigned int qspi_data4_b_pins[] = {
3057         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3058         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3059         RCAR_GP_PIN(6, 4),
3060 };
3061 static const unsigned int qspi_data4_b_mux[] = {
3062         SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3063         IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
3064 };
3065 /* - SCIF0 ------------------------------------------------------------------ */
3066 static const unsigned int scif0_data_pins[] = {
3067         /* RX, TX */
3068         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3069 };
3070 static const unsigned int scif0_data_mux[] = {
3071         RX0_MARK, TX0_MARK,
3072 };
3073 static const unsigned int scif0_data_b_pins[] = {
3074         /* RX, TX */
3075         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3076 };
3077 static const unsigned int scif0_data_b_mux[] = {
3078         RX0_B_MARK, TX0_B_MARK,
3079 };
3080 static const unsigned int scif0_data_c_pins[] = {
3081         /* RX, TX */
3082         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3083 };
3084 static const unsigned int scif0_data_c_mux[] = {
3085         RX0_C_MARK, TX0_C_MARK,
3086 };
3087 static const unsigned int scif0_data_d_pins[] = {
3088         /* RX, TX */
3089         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3090 };
3091 static const unsigned int scif0_data_d_mux[] = {
3092         RX0_D_MARK, TX0_D_MARK,
3093 };
3094 static const unsigned int scif0_data_e_pins[] = {
3095         /* RX, TX */
3096         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3097 };
3098 static const unsigned int scif0_data_e_mux[] = {
3099         RX0_E_MARK, TX0_E_MARK,
3100 };
3101 /* - SCIF1 ------------------------------------------------------------------ */
3102 static const unsigned int scif1_data_pins[] = {
3103         /* RX, TX */
3104         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3105 };
3106 static const unsigned int scif1_data_mux[] = {
3107         RX1_MARK, TX1_MARK,
3108 };
3109 static const unsigned int scif1_data_b_pins[] = {
3110         /* RX, TX */
3111         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3112 };
3113 static const unsigned int scif1_data_b_mux[] = {
3114         RX1_B_MARK, TX1_B_MARK,
3115 };
3116 static const unsigned int scif1_clk_b_pins[] = {
3117         /* SCK */
3118         RCAR_GP_PIN(3, 10),
3119 };
3120 static const unsigned int scif1_clk_b_mux[] = {
3121         SCIF1_SCK_B_MARK,
3122 };
3123 static const unsigned int scif1_data_c_pins[] = {
3124         /* RX, TX */
3125         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3126 };
3127 static const unsigned int scif1_data_c_mux[] = {
3128         RX1_C_MARK, TX1_C_MARK,
3129 };
3130 static const unsigned int scif1_data_d_pins[] = {
3131         /* RX, TX */
3132         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3133 };
3134 static const unsigned int scif1_data_d_mux[] = {
3135         RX1_D_MARK, TX1_D_MARK,
3136 };
3137 /* - SCIF2 ------------------------------------------------------------------ */
3138 static const unsigned int scif2_data_pins[] = {
3139         /* RX, TX */
3140         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3141 };
3142 static const unsigned int scif2_data_mux[] = {
3143         RX2_MARK, TX2_MARK,
3144 };
3145 static const unsigned int scif2_data_b_pins[] = {
3146         /* RX, TX */
3147         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3148 };
3149 static const unsigned int scif2_data_b_mux[] = {
3150         RX2_B_MARK, TX2_B_MARK,
3151 };
3152 static const unsigned int scif2_clk_b_pins[] = {
3153         /* SCK */
3154         RCAR_GP_PIN(3, 18),
3155 };
3156 static const unsigned int scif2_clk_b_mux[] = {
3157         SCIF2_SCK_B_MARK,
3158 };
3159 static const unsigned int scif2_data_c_pins[] = {
3160         /* RX, TX */
3161         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3162 };
3163 static const unsigned int scif2_data_c_mux[] = {
3164         RX2_C_MARK, TX2_C_MARK,
3165 };
3166 static const unsigned int scif2_data_e_pins[] = {
3167         /* RX, TX */
3168         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3169 };
3170 static const unsigned int scif2_data_e_mux[] = {
3171         RX2_E_MARK, TX2_E_MARK,
3172 };
3173 /* - SCIF3 ------------------------------------------------------------------ */
3174 static const unsigned int scif3_data_pins[] = {
3175         /* RX, TX */
3176         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3177 };
3178 static const unsigned int scif3_data_mux[] = {
3179         RX3_MARK, TX3_MARK,
3180 };
3181 static const unsigned int scif3_clk_pins[] = {
3182         /* SCK */
3183         RCAR_GP_PIN(3, 23),
3184 };
3185 static const unsigned int scif3_clk_mux[] = {
3186         SCIF3_SCK_MARK,
3187 };
3188 static const unsigned int scif3_data_b_pins[] = {
3189         /* RX, TX */
3190         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3191 };
3192 static const unsigned int scif3_data_b_mux[] = {
3193         RX3_B_MARK, TX3_B_MARK,
3194 };
3195 static const unsigned int scif3_clk_b_pins[] = {
3196         /* SCK */
3197         RCAR_GP_PIN(4, 8),
3198 };
3199 static const unsigned int scif3_clk_b_mux[] = {
3200         SCIF3_SCK_B_MARK,
3201 };
3202 static const unsigned int scif3_data_c_pins[] = {
3203         /* RX, TX */
3204         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3205 };
3206 static const unsigned int scif3_data_c_mux[] = {
3207         RX3_C_MARK, TX3_C_MARK,
3208 };
3209 static const unsigned int scif3_data_d_pins[] = {
3210         /* RX, TX */
3211         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3212 };
3213 static const unsigned int scif3_data_d_mux[] = {
3214         RX3_D_MARK, TX3_D_MARK,
3215 };
3216 /* - SCIF4 ------------------------------------------------------------------ */
3217 static const unsigned int scif4_data_pins[] = {
3218         /* RX, TX */
3219         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3220 };
3221 static const unsigned int scif4_data_mux[] = {
3222         RX4_MARK, TX4_MARK,
3223 };
3224 static const unsigned int scif4_data_b_pins[] = {
3225         /* RX, TX */
3226         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3227 };
3228 static const unsigned int scif4_data_b_mux[] = {
3229         RX4_B_MARK, TX4_B_MARK,
3230 };
3231 static const unsigned int scif4_data_c_pins[] = {
3232         /* RX, TX */
3233         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3234 };
3235 static const unsigned int scif4_data_c_mux[] = {
3236         RX4_C_MARK, TX4_C_MARK,
3237 };
3238 /* - SCIF5 ------------------------------------------------------------------ */
3239 static const unsigned int scif5_data_pins[] = {
3240         /* RX, TX */
3241         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3242 };
3243 static const unsigned int scif5_data_mux[] = {
3244         RX5_MARK, TX5_MARK,
3245 };
3246 static const unsigned int scif5_data_b_pins[] = {
3247         /* RX, TX */
3248         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3249 };
3250 static const unsigned int scif5_data_b_mux[] = {
3251         RX5_B_MARK, TX5_B_MARK,
3252 };
3253 /* - SCIFA0 ----------------------------------------------------------------- */
3254 static const unsigned int scifa0_data_pins[] = {
3255         /* RXD, TXD */
3256         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3257 };
3258 static const unsigned int scifa0_data_mux[] = {
3259         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3260 };
3261 static const unsigned int scifa0_data_b_pins[] = {
3262         /* RXD, TXD */
3263         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3264 };
3265 static const unsigned int scifa0_data_b_mux[] = {
3266         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3267 };
3268 /* - SCIFA1 ----------------------------------------------------------------- */
3269 static const unsigned int scifa1_data_pins[] = {
3270         /* RXD, TXD */
3271         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3272 };
3273 static const unsigned int scifa1_data_mux[] = {
3274         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3275 };
3276 static const unsigned int scifa1_clk_pins[] = {
3277         /* SCK */
3278         RCAR_GP_PIN(3, 10),
3279 };
3280 static const unsigned int scifa1_clk_mux[] = {
3281         SCIFA1_SCK_MARK,
3282 };
3283 static const unsigned int scifa1_data_b_pins[] = {
3284         /* RXD, TXD */
3285         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3286 };
3287 static const unsigned int scifa1_data_b_mux[] = {
3288         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3289 };
3290 static const unsigned int scifa1_clk_b_pins[] = {
3291         /* SCK */
3292         RCAR_GP_PIN(1, 0),
3293 };
3294 static const unsigned int scifa1_clk_b_mux[] = {
3295         SCIFA1_SCK_B_MARK,
3296 };
3297 static const unsigned int scifa1_data_c_pins[] = {
3298         /* RXD, TXD */
3299         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3300 };
3301 static const unsigned int scifa1_data_c_mux[] = {
3302         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3303 };
3304 /* - SCIFA2 ----------------------------------------------------------------- */
3305 static const unsigned int scifa2_data_pins[] = {
3306         /* RXD, TXD */
3307         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3308 };
3309 static const unsigned int scifa2_data_mux[] = {
3310         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3311 };
3312 static const unsigned int scifa2_clk_pins[] = {
3313         /* SCK */
3314         RCAR_GP_PIN(3, 18),
3315 };
3316 static const unsigned int scifa2_clk_mux[] = {
3317         SCIFA2_SCK_MARK,
3318 };
3319 static const unsigned int scifa2_data_b_pins[] = {
3320         /* RXD, TXD */
3321         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3322 };
3323 static const unsigned int scifa2_data_b_mux[] = {
3324         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3325 };
3326 /* - SCIFA3 ----------------------------------------------------------------- */
3327 static const unsigned int scifa3_data_pins[] = {
3328         /* RXD, TXD */
3329         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3330 };
3331 static const unsigned int scifa3_data_mux[] = {
3332         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3333 };
3334 static const unsigned int scifa3_clk_pins[] = {
3335         /* SCK */
3336         RCAR_GP_PIN(3, 23),
3337 };
3338 static const unsigned int scifa3_clk_mux[] = {
3339         SCIFA3_SCK_MARK,
3340 };
3341 static const unsigned int scifa3_data_b_pins[] = {
3342         /* RXD, TXD */
3343         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3344 };
3345 static const unsigned int scifa3_data_b_mux[] = {
3346         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3347 };
3348 static const unsigned int scifa3_clk_b_pins[] = {
3349         /* SCK */
3350         RCAR_GP_PIN(4, 8),
3351 };
3352 static const unsigned int scifa3_clk_b_mux[] = {
3353         SCIFA3_SCK_B_MARK,
3354 };
3355 static const unsigned int scifa3_data_c_pins[] = {
3356         /* RXD, TXD */
3357         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3358 };
3359 static const unsigned int scifa3_data_c_mux[] = {
3360         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3361 };
3362 static const unsigned int scifa3_clk_c_pins[] = {
3363         /* SCK */
3364         RCAR_GP_PIN(7, 22),
3365 };
3366 static const unsigned int scifa3_clk_c_mux[] = {
3367         SCIFA3_SCK_C_MARK,
3368 };
3369 /* - SCIFA4 ----------------------------------------------------------------- */
3370 static const unsigned int scifa4_data_pins[] = {
3371         /* RXD, TXD */
3372         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3373 };
3374 static const unsigned int scifa4_data_mux[] = {
3375         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3376 };
3377 static const unsigned int scifa4_data_b_pins[] = {
3378         /* RXD, TXD */
3379         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3380 };
3381 static const unsigned int scifa4_data_b_mux[] = {
3382         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3383 };
3384 static const unsigned int scifa4_data_c_pins[] = {
3385         /* RXD, TXD */
3386         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3387 };
3388 static const unsigned int scifa4_data_c_mux[] = {
3389         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3390 };
3391 /* - SCIFA5 ----------------------------------------------------------------- */
3392 static const unsigned int scifa5_data_pins[] = {
3393         /* RXD, TXD */
3394         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3395 };
3396 static const unsigned int scifa5_data_mux[] = {
3397         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3398 };
3399 static const unsigned int scifa5_data_b_pins[] = {
3400         /* RXD, TXD */
3401         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3402 };
3403 static const unsigned int scifa5_data_b_mux[] = {
3404         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3405 };
3406 static const unsigned int scifa5_data_c_pins[] = {
3407         /* RXD, TXD */
3408         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3409 };
3410 static const unsigned int scifa5_data_c_mux[] = {
3411         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3412 };
3413 /* - SCIFB0 ----------------------------------------------------------------- */
3414 static const unsigned int scifb0_data_pins[] = {
3415         /* RXD, TXD */
3416         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3417 };
3418 static const unsigned int scifb0_data_mux[] = {
3419         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3420 };
3421 static const unsigned int scifb0_clk_pins[] = {
3422         /* SCK */
3423         RCAR_GP_PIN(7, 2),
3424 };
3425 static const unsigned int scifb0_clk_mux[] = {
3426         SCIFB0_SCK_MARK,
3427 };
3428 static const unsigned int scifb0_ctrl_pins[] = {
3429         /* RTS, CTS */
3430         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3431 };
3432 static const unsigned int scifb0_ctrl_mux[] = {
3433         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3434 };
3435 static const unsigned int scifb0_data_b_pins[] = {
3436         /* RXD, TXD */
3437         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3438 };
3439 static const unsigned int scifb0_data_b_mux[] = {
3440         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3441 };
3442 static const unsigned int scifb0_clk_b_pins[] = {
3443         /* SCK */
3444         RCAR_GP_PIN(5, 31),
3445 };
3446 static const unsigned int scifb0_clk_b_mux[] = {
3447         SCIFB0_SCK_B_MARK,
3448 };
3449 static const unsigned int scifb0_ctrl_b_pins[] = {
3450         /* RTS, CTS */
3451         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3452 };
3453 static const unsigned int scifb0_ctrl_b_mux[] = {
3454         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3455 };
3456 static const unsigned int scifb0_data_c_pins[] = {
3457         /* RXD, TXD */
3458         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3459 };
3460 static const unsigned int scifb0_data_c_mux[] = {
3461         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3462 };
3463 static const unsigned int scifb0_clk_c_pins[] = {
3464         /* SCK */
3465         RCAR_GP_PIN(2, 30),
3466 };
3467 static const unsigned int scifb0_clk_c_mux[] = {
3468         SCIFB0_SCK_C_MARK,
3469 };
3470 static const unsigned int scifb0_data_d_pins[] = {
3471         /* RXD, TXD */
3472         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3473 };
3474 static const unsigned int scifb0_data_d_mux[] = {
3475         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3476 };
3477 static const unsigned int scifb0_clk_d_pins[] = {
3478         /* SCK */
3479         RCAR_GP_PIN(4, 17),
3480 };
3481 static const unsigned int scifb0_clk_d_mux[] = {
3482         SCIFB0_SCK_D_MARK,
3483 };
3484 /* - SCIFB1 ----------------------------------------------------------------- */
3485 static const unsigned int scifb1_data_pins[] = {
3486         /* RXD, TXD */
3487         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3488 };
3489 static const unsigned int scifb1_data_mux[] = {
3490         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3491 };
3492 static const unsigned int scifb1_clk_pins[] = {
3493         /* SCK */
3494         RCAR_GP_PIN(7, 7),
3495 };
3496 static const unsigned int scifb1_clk_mux[] = {
3497         SCIFB1_SCK_MARK,
3498 };
3499 static const unsigned int scifb1_ctrl_pins[] = {
3500         /* RTS, CTS */
3501         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3502 };
3503 static const unsigned int scifb1_ctrl_mux[] = {
3504         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3505 };
3506 static const unsigned int scifb1_data_b_pins[] = {
3507         /* RXD, TXD */
3508         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3509 };
3510 static const unsigned int scifb1_data_b_mux[] = {
3511         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3512 };
3513 static const unsigned int scifb1_clk_b_pins[] = {
3514         /* SCK */
3515         RCAR_GP_PIN(1, 3),
3516 };
3517 static const unsigned int scifb1_clk_b_mux[] = {
3518         SCIFB1_SCK_B_MARK,
3519 };
3520 static const unsigned int scifb1_data_c_pins[] = {
3521         /* RXD, TXD */
3522         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3523 };
3524 static const unsigned int scifb1_data_c_mux[] = {
3525         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3526 };
3527 static const unsigned int scifb1_clk_c_pins[] = {
3528         /* SCK */
3529         RCAR_GP_PIN(7, 11),
3530 };
3531 static const unsigned int scifb1_clk_c_mux[] = {
3532         SCIFB1_SCK_C_MARK,
3533 };
3534 static const unsigned int scifb1_data_d_pins[] = {
3535         /* RXD, TXD */
3536         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3537 };
3538 static const unsigned int scifb1_data_d_mux[] = {
3539         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3540 };
3541 /* - SCIFB2 ----------------------------------------------------------------- */
3542 static const unsigned int scifb2_data_pins[] = {
3543         /* RXD, TXD */
3544         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3545 };
3546 static const unsigned int scifb2_data_mux[] = {
3547         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3548 };
3549 static const unsigned int scifb2_clk_pins[] = {
3550         /* SCK */
3551         RCAR_GP_PIN(4, 15),
3552 };
3553 static const unsigned int scifb2_clk_mux[] = {
3554         SCIFB2_SCK_MARK,
3555 };
3556 static const unsigned int scifb2_ctrl_pins[] = {
3557         /* RTS, CTS */
3558         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3559 };
3560 static const unsigned int scifb2_ctrl_mux[] = {
3561         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3562 };
3563 static const unsigned int scifb2_data_b_pins[] = {
3564         /* RXD, TXD */
3565         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3566 };
3567 static const unsigned int scifb2_data_b_mux[] = {
3568         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3569 };
3570 static const unsigned int scifb2_clk_b_pins[] = {
3571         /* SCK */
3572         RCAR_GP_PIN(5, 31),
3573 };
3574 static const unsigned int scifb2_clk_b_mux[] = {
3575         SCIFB2_SCK_B_MARK,
3576 };
3577 static const unsigned int scifb2_ctrl_b_pins[] = {
3578         /* RTS, CTS */
3579         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3580 };
3581 static const unsigned int scifb2_ctrl_b_mux[] = {
3582         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3583 };
3584 static const unsigned int scifb2_data_c_pins[] = {
3585         /* RXD, TXD */
3586         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3587 };
3588 static const unsigned int scifb2_data_c_mux[] = {
3589         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3590 };
3591 static const unsigned int scifb2_clk_c_pins[] = {
3592         /* SCK */
3593         RCAR_GP_PIN(5, 27),
3594 };
3595 static const unsigned int scifb2_clk_c_mux[] = {
3596         SCIFB2_SCK_C_MARK,
3597 };
3598 static const unsigned int scifb2_data_d_pins[] = {
3599         /* RXD, TXD */
3600         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3601 };
3602 static const unsigned int scifb2_data_d_mux[] = {
3603         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3604 };
3605 /* - SDHI0 ------------------------------------------------------------------ */
3606 static const unsigned int sdhi0_data1_pins[] = {
3607         /* D0 */
3608         RCAR_GP_PIN(6, 2),
3609 };
3610 static const unsigned int sdhi0_data1_mux[] = {
3611         SD0_DATA0_MARK,
3612 };
3613 static const unsigned int sdhi0_data4_pins[] = {
3614         /* D[0:3] */
3615         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3616         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3617 };
3618 static const unsigned int sdhi0_data4_mux[] = {
3619         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3620 };
3621 static const unsigned int sdhi0_ctrl_pins[] = {
3622         /* CLK, CMD */
3623         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3624 };
3625 static const unsigned int sdhi0_ctrl_mux[] = {
3626         SD0_CLK_MARK, SD0_CMD_MARK,
3627 };
3628 static const unsigned int sdhi0_cd_pins[] = {
3629         /* CD */
3630         RCAR_GP_PIN(6, 6),
3631 };
3632 static const unsigned int sdhi0_cd_mux[] = {
3633         SD0_CD_MARK,
3634 };
3635 static const unsigned int sdhi0_wp_pins[] = {
3636         /* WP */
3637         RCAR_GP_PIN(6, 7),
3638 };
3639 static const unsigned int sdhi0_wp_mux[] = {
3640         SD0_WP_MARK,
3641 };
3642 /* - SDHI1 ------------------------------------------------------------------ */
3643 static const unsigned int sdhi1_data1_pins[] = {
3644         /* D0 */
3645         RCAR_GP_PIN(6, 10),
3646 };
3647 static const unsigned int sdhi1_data1_mux[] = {
3648         SD1_DATA0_MARK,
3649 };
3650 static const unsigned int sdhi1_data4_pins[] = {
3651         /* D[0:3] */
3652         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3653         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3654 };
3655 static const unsigned int sdhi1_data4_mux[] = {
3656         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3657 };
3658 static const unsigned int sdhi1_ctrl_pins[] = {
3659         /* CLK, CMD */
3660         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3661 };
3662 static const unsigned int sdhi1_ctrl_mux[] = {
3663         SD1_CLK_MARK, SD1_CMD_MARK,
3664 };
3665 static const unsigned int sdhi1_cd_pins[] = {
3666         /* CD */
3667         RCAR_GP_PIN(6, 14),
3668 };
3669 static const unsigned int sdhi1_cd_mux[] = {
3670         SD1_CD_MARK,
3671 };
3672 static const unsigned int sdhi1_wp_pins[] = {
3673         /* WP */
3674         RCAR_GP_PIN(6, 15),
3675 };
3676 static const unsigned int sdhi1_wp_mux[] = {
3677         SD1_WP_MARK,
3678 };
3679 /* - SDHI2 ------------------------------------------------------------------ */
3680 static const unsigned int sdhi2_data1_pins[] = {
3681         /* D0 */
3682         RCAR_GP_PIN(6, 18),
3683 };
3684 static const unsigned int sdhi2_data1_mux[] = {
3685         SD2_DATA0_MARK,
3686 };
3687 static const unsigned int sdhi2_data4_pins[] = {
3688         /* D[0:3] */
3689         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3690         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3691 };
3692 static const unsigned int sdhi2_data4_mux[] = {
3693         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3694 };
3695 static const unsigned int sdhi2_ctrl_pins[] = {
3696         /* CLK, CMD */
3697         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3698 };
3699 static const unsigned int sdhi2_ctrl_mux[] = {
3700         SD2_CLK_MARK, SD2_CMD_MARK,
3701 };
3702 static const unsigned int sdhi2_cd_pins[] = {
3703         /* CD */
3704         RCAR_GP_PIN(6, 22),
3705 };
3706 static const unsigned int sdhi2_cd_mux[] = {
3707         SD2_CD_MARK,
3708 };
3709 static const unsigned int sdhi2_wp_pins[] = {
3710         /* WP */
3711         RCAR_GP_PIN(6, 23),
3712 };
3713 static const unsigned int sdhi2_wp_mux[] = {
3714         SD2_WP_MARK,
3715 };
3716
3717 /* - SSI -------------------------------------------------------------------- */
3718 static const unsigned int ssi0_data_pins[] = {
3719         /* SDATA */
3720         RCAR_GP_PIN(2, 2),
3721 };
3722
3723 static const unsigned int ssi0_data_mux[] = {
3724         SSI_SDATA0_MARK,
3725 };
3726
3727 static const unsigned int ssi0_data_b_pins[] = {
3728         /* SDATA */
3729         RCAR_GP_PIN(3, 4),
3730 };
3731
3732 static const unsigned int ssi0_data_b_mux[] = {
3733         SSI_SDATA0_B_MARK,
3734 };
3735
3736 static const unsigned int ssi0129_ctrl_pins[] = {
3737         /* SCK, WS */
3738         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3739 };
3740
3741 static const unsigned int ssi0129_ctrl_mux[] = {
3742         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3743 };
3744
3745 static const unsigned int ssi0129_ctrl_b_pins[] = {
3746         /* SCK, WS */
3747         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3748 };
3749
3750 static const unsigned int ssi0129_ctrl_b_mux[] = {
3751         SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3752 };
3753
3754 static const unsigned int ssi1_data_pins[] = {
3755         /* SDATA */
3756         RCAR_GP_PIN(2, 5),
3757 };
3758
3759 static const unsigned int ssi1_data_mux[] = {
3760         SSI_SDATA1_MARK,
3761 };
3762
3763 static const unsigned int ssi1_data_b_pins[] = {
3764         /* SDATA */
3765         RCAR_GP_PIN(3, 7),
3766 };
3767
3768 static const unsigned int ssi1_data_b_mux[] = {
3769         SSI_SDATA1_B_MARK,
3770 };
3771
3772 static const unsigned int ssi1_ctrl_pins[] = {
3773         /* SCK, WS */
3774         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3775 };
3776
3777 static const unsigned int ssi1_ctrl_mux[] = {
3778         SSI_SCK1_MARK, SSI_WS1_MARK,
3779 };
3780
3781 static const unsigned int ssi1_ctrl_b_pins[] = {
3782         /* SCK, WS */
3783         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3784 };
3785
3786 static const unsigned int ssi1_ctrl_b_mux[] = {
3787         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3788 };
3789
3790 static const unsigned int ssi2_data_pins[] = {
3791         /* SDATA */
3792         RCAR_GP_PIN(2, 8),
3793 };
3794
3795 static const unsigned int ssi2_data_mux[] = {
3796         SSI_SDATA2_MARK,
3797 };
3798
3799 static const unsigned int ssi2_ctrl_pins[] = {
3800         /* SCK, WS */
3801         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3802 };
3803
3804 static const unsigned int ssi2_ctrl_mux[] = {
3805         SSI_SCK2_MARK, SSI_WS2_MARK,
3806 };
3807
3808 static const unsigned int ssi3_data_pins[] = {
3809         /* SDATA */
3810         RCAR_GP_PIN(2, 11),
3811 };
3812
3813 static const unsigned int ssi3_data_mux[] = {
3814         SSI_SDATA3_MARK,
3815 };
3816
3817 static const unsigned int ssi34_ctrl_pins[] = {
3818         /* SCK, WS */
3819         RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3820 };
3821
3822 static const unsigned int ssi34_ctrl_mux[] = {
3823         SSI_SCK34_MARK, SSI_WS34_MARK,
3824 };
3825
3826 static const unsigned int ssi4_data_pins[] = {
3827         /* SDATA */
3828         RCAR_GP_PIN(2, 14),
3829 };
3830
3831 static const unsigned int ssi4_data_mux[] = {
3832         SSI_SDATA4_MARK,
3833 };
3834
3835 static const unsigned int ssi4_ctrl_pins[] = {
3836         /* SCK, WS */
3837         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3838 };
3839
3840 static const unsigned int ssi4_ctrl_mux[] = {
3841         SSI_SCK4_MARK, SSI_WS4_MARK,
3842 };
3843
3844 static const unsigned int ssi5_data_pins[] = {
3845         /* SDATA */
3846         RCAR_GP_PIN(2, 17),
3847 };
3848
3849 static const unsigned int ssi5_data_mux[] = {
3850         SSI_SDATA5_MARK,
3851 };
3852
3853 static const unsigned int ssi5_ctrl_pins[] = {
3854         /* SCK, WS */
3855         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3856 };
3857
3858 static const unsigned int ssi5_ctrl_mux[] = {
3859         SSI_SCK5_MARK, SSI_WS5_MARK,
3860 };
3861
3862 static const unsigned int ssi6_data_pins[] = {
3863         /* SDATA */
3864         RCAR_GP_PIN(2, 20),
3865 };
3866
3867 static const unsigned int ssi6_data_mux[] = {
3868         SSI_SDATA6_MARK,
3869 };
3870
3871 static const unsigned int ssi6_ctrl_pins[] = {
3872         /* SCK, WS */
3873         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
3874 };
3875
3876 static const unsigned int ssi6_ctrl_mux[] = {
3877         SSI_SCK6_MARK, SSI_WS6_MARK,
3878 };
3879
3880 static const unsigned int ssi7_data_pins[] = {
3881         /* SDATA */
3882         RCAR_GP_PIN(2, 23),
3883 };
3884
3885 static const unsigned int ssi7_data_mux[] = {
3886         SSI_SDATA7_MARK,
3887 };
3888
3889 static const unsigned int ssi7_data_b_pins[] = {
3890         /* SDATA */
3891         RCAR_GP_PIN(3, 12),
3892 };
3893
3894 static const unsigned int ssi7_data_b_mux[] = {
3895         SSI_SDATA7_B_MARK,
3896 };
3897
3898 static const unsigned int ssi78_ctrl_pins[] = {
3899         /* SCK, WS */
3900         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3901 };
3902
3903 static const unsigned int ssi78_ctrl_mux[] = {
3904         SSI_SCK78_MARK, SSI_WS78_MARK,
3905 };
3906
3907 static const unsigned int ssi78_ctrl_b_pins[] = {
3908         /* SCK, WS */
3909         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3910 };
3911
3912 static const unsigned int ssi78_ctrl_b_mux[] = {
3913         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3914 };
3915
3916 static const unsigned int ssi8_data_pins[] = {
3917         /* SDATA */
3918         RCAR_GP_PIN(2, 24),
3919 };
3920
3921 static const unsigned int ssi8_data_mux[] = {
3922         SSI_SDATA8_MARK,
3923 };
3924
3925 static const unsigned int ssi8_data_b_pins[] = {
3926         /* SDATA */
3927         RCAR_GP_PIN(3, 13),
3928 };
3929
3930 static const unsigned int ssi8_data_b_mux[] = {
3931         SSI_SDATA8_B_MARK,
3932 };
3933
3934 static const unsigned int ssi9_data_pins[] = {
3935         /* SDATA */
3936         RCAR_GP_PIN(2, 27),
3937 };
3938
3939 static const unsigned int ssi9_data_mux[] = {
3940         SSI_SDATA9_MARK,
3941 };
3942
3943 static const unsigned int ssi9_data_b_pins[] = {
3944         /* SDATA */
3945         RCAR_GP_PIN(3, 18),
3946 };
3947
3948 static const unsigned int ssi9_data_b_mux[] = {
3949         SSI_SDATA9_B_MARK,
3950 };
3951
3952 static const unsigned int ssi9_ctrl_pins[] = {
3953         /* SCK, WS */
3954         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
3955 };
3956
3957 static const unsigned int ssi9_ctrl_mux[] = {
3958         SSI_SCK9_MARK, SSI_WS9_MARK,
3959 };
3960
3961 static const unsigned int ssi9_ctrl_b_pins[] = {
3962         /* SCK, WS */
3963         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3964 };
3965
3966 static const unsigned int ssi9_ctrl_b_mux[] = {
3967         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3968 };
3969
3970 /* - USB0 ------------------------------------------------------------------- */
3971 static const unsigned int usb0_pins[] = {
3972         RCAR_GP_PIN(7, 23), /* PWEN */
3973         RCAR_GP_PIN(7, 24), /* OVC */
3974 };
3975 static const unsigned int usb0_mux[] = {
3976         USB0_PWEN_MARK,
3977         USB0_OVC_MARK,
3978 };
3979 /* - USB1 ------------------------------------------------------------------- */
3980 static const unsigned int usb1_pins[] = {
3981         RCAR_GP_PIN(7, 25), /* PWEN */
3982         RCAR_GP_PIN(6, 30), /* OVC */
3983 };
3984 static const unsigned int usb1_mux[] = {
3985         USB1_PWEN_MARK,
3986         USB1_OVC_MARK,
3987 };
3988 /* - VIN0 ------------------------------------------------------------------- */
3989 static const union vin_data vin0_data_pins = {
3990         .data24 = {
3991                 /* B */
3992                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
3993                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3994                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3995                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3996                 /* G */
3997                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3998                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3999                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4000                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4001                 /* R */
4002                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4003                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4004                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4005                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4006         },
4007 };
4008 static const union vin_data vin0_data_mux = {
4009         .data24 = {
4010                 /* B */
4011                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4012                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4013                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4014                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4015                 /* G */
4016                 VI0_G0_MARK, VI0_G1_MARK,
4017                 VI0_G2_MARK, VI0_G3_MARK,
4018                 VI0_G4_MARK, VI0_G5_MARK,
4019                 VI0_G6_MARK, VI0_G7_MARK,
4020                 /* R */
4021                 VI0_R0_MARK, VI0_R1_MARK,
4022                 VI0_R2_MARK, VI0_R3_MARK,
4023                 VI0_R4_MARK, VI0_R5_MARK,
4024                 VI0_R6_MARK, VI0_R7_MARK,
4025         },
4026 };
4027 static const unsigned int vin0_data18_pins[] = {
4028         /* B */
4029         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4030         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4031         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4032         /* G */
4033         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4034         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4035         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4036         /* R */
4037         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4038         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4039         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4040 };
4041 static const unsigned int vin0_data18_mux[] = {
4042         /* B */
4043         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4044         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4045         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4046         /* G */
4047         VI0_G2_MARK, VI0_G3_MARK,
4048         VI0_G4_MARK, VI0_G5_MARK,
4049         VI0_G6_MARK, VI0_G7_MARK,
4050         /* R */
4051         VI0_R2_MARK, VI0_R3_MARK,
4052         VI0_R4_MARK, VI0_R5_MARK,
4053         VI0_R6_MARK, VI0_R7_MARK,
4054 };
4055 static const unsigned int vin0_sync_pins[] = {
4056         RCAR_GP_PIN(4, 3), /* HSYNC */
4057         RCAR_GP_PIN(4, 4), /* VSYNC */
4058 };
4059 static const unsigned int vin0_sync_mux[] = {
4060         VI0_HSYNC_N_MARK,
4061         VI0_VSYNC_N_MARK,
4062 };
4063 static const unsigned int vin0_field_pins[] = {
4064         RCAR_GP_PIN(4, 2),
4065 };
4066 static const unsigned int vin0_field_mux[] = {
4067         VI0_FIELD_MARK,
4068 };
4069 static const unsigned int vin0_clkenb_pins[] = {
4070         RCAR_GP_PIN(4, 1),
4071 };
4072 static const unsigned int vin0_clkenb_mux[] = {
4073         VI0_CLKENB_MARK,
4074 };
4075 static const unsigned int vin0_clk_pins[] = {
4076         RCAR_GP_PIN(4, 0),
4077 };
4078 static const unsigned int vin0_clk_mux[] = {
4079         VI0_CLK_MARK,
4080 };
4081 /* - VIN1 ----------------------------------------------------------------- */
4082 static const unsigned int vin1_data8_pins[] = {
4083         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4084         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4085         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4086         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4087 };
4088 static const unsigned int vin1_data8_mux[] = {
4089         VI1_DATA0_MARK, VI1_DATA1_MARK,
4090         VI1_DATA2_MARK, VI1_DATA3_MARK,
4091         VI1_DATA4_MARK, VI1_DATA5_MARK,
4092         VI1_DATA6_MARK, VI1_DATA7_MARK,
4093 };
4094 static const unsigned int vin1_sync_pins[] = {
4095         RCAR_GP_PIN(5, 0), /* HSYNC */
4096         RCAR_GP_PIN(5, 1), /* VSYNC */
4097 };
4098 static const unsigned int vin1_sync_mux[] = {
4099         VI1_HSYNC_N_MARK,
4100         VI1_VSYNC_N_MARK,
4101 };
4102 static const unsigned int vin1_field_pins[] = {
4103         RCAR_GP_PIN(5, 3),
4104 };
4105 static const unsigned int vin1_field_mux[] = {
4106         VI1_FIELD_MARK,
4107 };
4108 static const unsigned int vin1_clkenb_pins[] = {
4109         RCAR_GP_PIN(5, 2),
4110 };
4111 static const unsigned int vin1_clkenb_mux[] = {
4112         VI1_CLKENB_MARK,
4113 };
4114 static const unsigned int vin1_clk_pins[] = {
4115         RCAR_GP_PIN(5, 4),
4116 };
4117 static const unsigned int vin1_clk_mux[] = {
4118         VI1_CLK_MARK,
4119 };
4120 static const union vin_data vin1_b_data_pins = {
4121         .data24 = {
4122                 /* B */
4123                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4124                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4125                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4126                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4127                 /* G */
4128                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4129                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4130                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4131                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4132                 /* R */
4133                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4134                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4135                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4136                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4137         },
4138 };
4139 static const union vin_data vin1_b_data_mux = {
4140         .data24 = {
4141                 /* B */
4142                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4143                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4144                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4145                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4146                 /* G */
4147                 VI1_G0_B_MARK, VI1_G1_B_MARK,
4148                 VI1_G2_B_MARK, VI1_G3_B_MARK,
4149                 VI1_G4_B_MARK, VI1_G5_B_MARK,
4150                 VI1_G6_B_MARK, VI1_G7_B_MARK,
4151                 /* R */
4152                 VI1_R0_B_MARK, VI1_R1_B_MARK,
4153                 VI1_R2_B_MARK, VI1_R3_B_MARK,
4154                 VI1_R4_B_MARK, VI1_R5_B_MARK,
4155                 VI1_R6_B_MARK, VI1_R7_B_MARK,
4156         },
4157 };
4158 static const unsigned int vin1_b_data18_pins[] = {
4159         /* B */
4160         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4161         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4162         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4163         /* G */
4164         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4165         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4166         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4167         /* R */
4168         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4169         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4170         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4171 };
4172 static const unsigned int vin1_b_data18_mux[] = {
4173         /* B */
4174         VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4175         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4176         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4177         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4178         /* G */
4179         VI1_G0_B_MARK, VI1_G1_B_MARK,
4180         VI1_G2_B_MARK, VI1_G3_B_MARK,
4181         VI1_G4_B_MARK, VI1_G5_B_MARK,
4182         VI1_G6_B_MARK, VI1_G7_B_MARK,
4183         /* R */
4184         VI1_R0_B_MARK, VI1_R1_B_MARK,
4185         VI1_R2_B_MARK, VI1_R3_B_MARK,
4186         VI1_R4_B_MARK, VI1_R5_B_MARK,
4187         VI1_R6_B_MARK, VI1_R7_B_MARK,
4188 };
4189 static const unsigned int vin1_b_sync_pins[] = {
4190         RCAR_GP_PIN(3, 17), /* HSYNC */
4191         RCAR_GP_PIN(3, 18), /* VSYNC */
4192 };
4193 static const unsigned int vin1_b_sync_mux[] = {
4194         VI1_HSYNC_N_B_MARK,
4195         VI1_VSYNC_N_B_MARK,
4196 };
4197 static const unsigned int vin1_b_field_pins[] = {
4198         RCAR_GP_PIN(3, 20),
4199 };
4200 static const unsigned int vin1_b_field_mux[] = {
4201         VI1_FIELD_B_MARK,
4202 };
4203 static const unsigned int vin1_b_clkenb_pins[] = {
4204         RCAR_GP_PIN(3, 19),
4205 };
4206 static const unsigned int vin1_b_clkenb_mux[] = {
4207         VI1_CLKENB_B_MARK,
4208 };
4209 static const unsigned int vin1_b_clk_pins[] = {
4210         RCAR_GP_PIN(3, 16),
4211 };
4212 static const unsigned int vin1_b_clk_mux[] = {
4213         VI1_CLK_B_MARK,
4214 };
4215 /* - VIN2 ----------------------------------------------------------------- */
4216 static const unsigned int vin2_data8_pins[] = {
4217         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4218         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4219         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4220         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4221 };
4222 static const unsigned int vin2_data8_mux[] = {
4223         VI2_DATA0_MARK, VI2_DATA1_MARK,
4224         VI2_DATA2_MARK, VI2_DATA3_MARK,
4225         VI2_DATA4_MARK, VI2_DATA5_MARK,
4226         VI2_DATA6_MARK, VI2_DATA7_MARK,
4227 };
4228 static const unsigned int vin2_sync_pins[] = {
4229         RCAR_GP_PIN(4, 15), /* HSYNC */
4230         RCAR_GP_PIN(4, 16), /* VSYNC */
4231 };
4232 static const unsigned int vin2_sync_mux[] = {
4233         VI2_HSYNC_N_MARK,
4234         VI2_VSYNC_N_MARK,
4235 };
4236 static const unsigned int vin2_field_pins[] = {
4237         RCAR_GP_PIN(4, 18),
4238 };
4239 static const unsigned int vin2_field_mux[] = {
4240         VI2_FIELD_MARK,
4241 };
4242 static const unsigned int vin2_clkenb_pins[] = {
4243         RCAR_GP_PIN(4, 17),
4244 };
4245 static const unsigned int vin2_clkenb_mux[] = {
4246         VI2_CLKENB_MARK,
4247 };
4248 static const unsigned int vin2_clk_pins[] = {
4249         RCAR_GP_PIN(4, 19),
4250 };
4251 static const unsigned int vin2_clk_mux[] = {
4252         VI2_CLK_MARK,
4253 };
4254
4255 static const struct sh_pfc_pin_group pinmux_groups[] = {
4256         SH_PFC_PIN_GROUP(audio_clk_a),
4257         SH_PFC_PIN_GROUP(audio_clk_b),
4258         SH_PFC_PIN_GROUP(audio_clk_b_b),
4259         SH_PFC_PIN_GROUP(audio_clk_c),
4260         SH_PFC_PIN_GROUP(audio_clkout),
4261         SH_PFC_PIN_GROUP(can0_data),
4262         SH_PFC_PIN_GROUP(can0_data_b),
4263         SH_PFC_PIN_GROUP(can0_data_c),
4264         SH_PFC_PIN_GROUP(can0_data_d),
4265         SH_PFC_PIN_GROUP(can0_data_e),
4266         SH_PFC_PIN_GROUP(can0_data_f),
4267         SH_PFC_PIN_GROUP(can1_data),
4268         SH_PFC_PIN_GROUP(can1_data_b),
4269         SH_PFC_PIN_GROUP(can1_data_c),
4270         SH_PFC_PIN_GROUP(can1_data_d),
4271         SH_PFC_PIN_GROUP(can_clk),
4272         SH_PFC_PIN_GROUP(can_clk_b),
4273         SH_PFC_PIN_GROUP(can_clk_c),
4274         SH_PFC_PIN_GROUP(can_clk_d),
4275         SH_PFC_PIN_GROUP(du_rgb666),
4276         SH_PFC_PIN_GROUP(du_rgb888),
4277         SH_PFC_PIN_GROUP(du_clk_out_0),
4278         SH_PFC_PIN_GROUP(du_clk_out_1),
4279         SH_PFC_PIN_GROUP(du_sync),
4280         SH_PFC_PIN_GROUP(du_oddf),
4281         SH_PFC_PIN_GROUP(du_cde),
4282         SH_PFC_PIN_GROUP(du_disp),
4283         SH_PFC_PIN_GROUP(du0_clk_in),
4284         SH_PFC_PIN_GROUP(du1_clk_in),
4285         SH_PFC_PIN_GROUP(du1_clk_in_b),
4286         SH_PFC_PIN_GROUP(du1_clk_in_c),
4287         SH_PFC_PIN_GROUP(eth_link),
4288         SH_PFC_PIN_GROUP(eth_magic),
4289         SH_PFC_PIN_GROUP(eth_mdio),
4290         SH_PFC_PIN_GROUP(eth_rmii),
4291         SH_PFC_PIN_GROUP(hscif0_data),
4292         SH_PFC_PIN_GROUP(hscif0_clk),
4293         SH_PFC_PIN_GROUP(hscif0_ctrl),
4294         SH_PFC_PIN_GROUP(hscif0_data_b),
4295         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4296         SH_PFC_PIN_GROUP(hscif0_data_c),
4297         SH_PFC_PIN_GROUP(hscif0_clk_c),
4298         SH_PFC_PIN_GROUP(hscif1_data),
4299         SH_PFC_PIN_GROUP(hscif1_clk),
4300         SH_PFC_PIN_GROUP(hscif1_ctrl),
4301         SH_PFC_PIN_GROUP(hscif1_data_b),
4302         SH_PFC_PIN_GROUP(hscif1_data_c),
4303         SH_PFC_PIN_GROUP(hscif1_clk_c),
4304         SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4305         SH_PFC_PIN_GROUP(hscif1_data_d),
4306         SH_PFC_PIN_GROUP(hscif1_data_e),
4307         SH_PFC_PIN_GROUP(hscif1_clk_e),
4308         SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4309         SH_PFC_PIN_GROUP(hscif2_data),
4310         SH_PFC_PIN_GROUP(hscif2_clk),
4311         SH_PFC_PIN_GROUP(hscif2_ctrl),
4312         SH_PFC_PIN_GROUP(hscif2_data_b),
4313         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4314         SH_PFC_PIN_GROUP(hscif2_data_c),
4315         SH_PFC_PIN_GROUP(hscif2_clk_c),
4316         SH_PFC_PIN_GROUP(hscif2_data_d),
4317         SH_PFC_PIN_GROUP(i2c0),
4318         SH_PFC_PIN_GROUP(i2c0_b),
4319         SH_PFC_PIN_GROUP(i2c0_c),
4320         SH_PFC_PIN_GROUP(i2c1),
4321         SH_PFC_PIN_GROUP(i2c1_b),
4322         SH_PFC_PIN_GROUP(i2c1_c),
4323         SH_PFC_PIN_GROUP(i2c1_d),
4324         SH_PFC_PIN_GROUP(i2c1_e),
4325         SH_PFC_PIN_GROUP(i2c2),
4326         SH_PFC_PIN_GROUP(i2c2_b),
4327         SH_PFC_PIN_GROUP(i2c2_c),
4328         SH_PFC_PIN_GROUP(i2c2_d),
4329         SH_PFC_PIN_GROUP(i2c3),
4330         SH_PFC_PIN_GROUP(i2c3_b),
4331         SH_PFC_PIN_GROUP(i2c3_c),
4332         SH_PFC_PIN_GROUP(i2c3_d),
4333         SH_PFC_PIN_GROUP(i2c4),
4334         SH_PFC_PIN_GROUP(i2c4_b),
4335         SH_PFC_PIN_GROUP(i2c4_c),
4336         SH_PFC_PIN_GROUP(i2c7),
4337         SH_PFC_PIN_GROUP(i2c7_b),
4338         SH_PFC_PIN_GROUP(i2c7_c),
4339         SH_PFC_PIN_GROUP(i2c8),
4340         SH_PFC_PIN_GROUP(i2c8_b),
4341         SH_PFC_PIN_GROUP(i2c8_c),
4342         SH_PFC_PIN_GROUP(intc_irq0),
4343         SH_PFC_PIN_GROUP(intc_irq1),
4344         SH_PFC_PIN_GROUP(intc_irq2),
4345         SH_PFC_PIN_GROUP(intc_irq3),
4346         SH_PFC_PIN_GROUP(mlb_3pin),
4347         SH_PFC_PIN_GROUP(mmc_data1),
4348         SH_PFC_PIN_GROUP(mmc_data4),
4349         SH_PFC_PIN_GROUP(mmc_data8),
4350         SH_PFC_PIN_GROUP(mmc_ctrl),
4351         SH_PFC_PIN_GROUP(msiof0_clk),
4352         SH_PFC_PIN_GROUP(msiof0_sync),
4353         SH_PFC_PIN_GROUP(msiof0_ss1),
4354         SH_PFC_PIN_GROUP(msiof0_ss2),
4355         SH_PFC_PIN_GROUP(msiof0_rx),
4356         SH_PFC_PIN_GROUP(msiof0_tx),
4357         SH_PFC_PIN_GROUP(msiof0_clk_b),
4358         SH_PFC_PIN_GROUP(msiof0_sync_b),
4359         SH_PFC_PIN_GROUP(msiof0_ss1_b),
4360         SH_PFC_PIN_GROUP(msiof0_ss2_b),
4361         SH_PFC_PIN_GROUP(msiof0_rx_b),
4362         SH_PFC_PIN_GROUP(msiof0_tx_b),
4363         SH_PFC_PIN_GROUP(msiof0_clk_c),
4364         SH_PFC_PIN_GROUP(msiof0_sync_c),
4365         SH_PFC_PIN_GROUP(msiof0_ss1_c),
4366         SH_PFC_PIN_GROUP(msiof0_ss2_c),
4367         SH_PFC_PIN_GROUP(msiof0_rx_c),
4368         SH_PFC_PIN_GROUP(msiof0_tx_c),
4369         SH_PFC_PIN_GROUP(msiof1_clk),
4370         SH_PFC_PIN_GROUP(msiof1_sync),
4371         SH_PFC_PIN_GROUP(msiof1_ss1),
4372         SH_PFC_PIN_GROUP(msiof1_ss2),
4373         SH_PFC_PIN_GROUP(msiof1_rx),
4374         SH_PFC_PIN_GROUP(msiof1_tx),
4375         SH_PFC_PIN_GROUP(msiof1_clk_b),
4376         SH_PFC_PIN_GROUP(msiof1_sync_b),
4377         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4378         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4379         SH_PFC_PIN_GROUP(msiof1_rx_b),
4380         SH_PFC_PIN_GROUP(msiof1_tx_b),
4381         SH_PFC_PIN_GROUP(msiof1_clk_c),
4382         SH_PFC_PIN_GROUP(msiof1_sync_c),
4383         SH_PFC_PIN_GROUP(msiof1_rx_c),
4384         SH_PFC_PIN_GROUP(msiof1_tx_c),
4385         SH_PFC_PIN_GROUP(msiof1_clk_d),
4386         SH_PFC_PIN_GROUP(msiof1_sync_d),
4387         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4388         SH_PFC_PIN_GROUP(msiof1_rx_d),
4389         SH_PFC_PIN_GROUP(msiof1_tx_d),
4390         SH_PFC_PIN_GROUP(msiof1_clk_e),
4391         SH_PFC_PIN_GROUP(msiof1_sync_e),
4392         SH_PFC_PIN_GROUP(msiof1_rx_e),
4393         SH_PFC_PIN_GROUP(msiof1_tx_e),
4394         SH_PFC_PIN_GROUP(msiof2_clk),
4395         SH_PFC_PIN_GROUP(msiof2_sync),
4396         SH_PFC_PIN_GROUP(msiof2_ss1),
4397         SH_PFC_PIN_GROUP(msiof2_ss2),
4398         SH_PFC_PIN_GROUP(msiof2_rx),
4399         SH_PFC_PIN_GROUP(msiof2_tx),
4400         SH_PFC_PIN_GROUP(msiof2_clk_b),
4401         SH_PFC_PIN_GROUP(msiof2_sync_b),
4402         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4403         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4404         SH_PFC_PIN_GROUP(msiof2_rx_b),
4405         SH_PFC_PIN_GROUP(msiof2_tx_b),
4406         SH_PFC_PIN_GROUP(msiof2_clk_c),
4407         SH_PFC_PIN_GROUP(msiof2_sync_c),
4408         SH_PFC_PIN_GROUP(msiof2_rx_c),
4409         SH_PFC_PIN_GROUP(msiof2_tx_c),
4410         SH_PFC_PIN_GROUP(msiof2_clk_d),
4411         SH_PFC_PIN_GROUP(msiof2_sync_d),
4412         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4413         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4414         SH_PFC_PIN_GROUP(msiof2_rx_d),
4415         SH_PFC_PIN_GROUP(msiof2_tx_d),
4416         SH_PFC_PIN_GROUP(msiof2_clk_e),
4417         SH_PFC_PIN_GROUP(msiof2_sync_e),
4418         SH_PFC_PIN_GROUP(msiof2_rx_e),
4419         SH_PFC_PIN_GROUP(msiof2_tx_e),
4420         SH_PFC_PIN_GROUP(pwm0),
4421         SH_PFC_PIN_GROUP(pwm0_b),
4422         SH_PFC_PIN_GROUP(pwm1),
4423         SH_PFC_PIN_GROUP(pwm1_b),
4424         SH_PFC_PIN_GROUP(pwm2),
4425         SH_PFC_PIN_GROUP(pwm2_b),
4426         SH_PFC_PIN_GROUP(pwm3),
4427         SH_PFC_PIN_GROUP(pwm4),
4428         SH_PFC_PIN_GROUP(pwm4_b),
4429         SH_PFC_PIN_GROUP(pwm5),
4430         SH_PFC_PIN_GROUP(pwm5_b),
4431         SH_PFC_PIN_GROUP(pwm6),
4432         SH_PFC_PIN_GROUP(qspi_ctrl),
4433         SH_PFC_PIN_GROUP(qspi_data2),
4434         SH_PFC_PIN_GROUP(qspi_data4),
4435         SH_PFC_PIN_GROUP(qspi_ctrl_b),
4436         SH_PFC_PIN_GROUP(qspi_data2_b),
4437         SH_PFC_PIN_GROUP(qspi_data4_b),
4438         SH_PFC_PIN_GROUP(scif0_data),
4439         SH_PFC_PIN_GROUP(scif0_data_b),
4440         SH_PFC_PIN_GROUP(scif0_data_c),
4441         SH_PFC_PIN_GROUP(scif0_data_d),
4442         SH_PFC_PIN_GROUP(scif0_data_e),
4443         SH_PFC_PIN_GROUP(scif1_data),
4444         SH_PFC_PIN_GROUP(scif1_data_b),
4445         SH_PFC_PIN_GROUP(scif1_clk_b),
4446         SH_PFC_PIN_GROUP(scif1_data_c),
4447         SH_PFC_PIN_GROUP(scif1_data_d),
4448         SH_PFC_PIN_GROUP(scif2_data),
4449         SH_PFC_PIN_GROUP(scif2_data_b),
4450         SH_PFC_PIN_GROUP(scif2_clk_b),
4451         SH_PFC_PIN_GROUP(scif2_data_c),
4452         SH_PFC_PIN_GROUP(scif2_data_e),
4453         SH_PFC_PIN_GROUP(scif3_data),
4454         SH_PFC_PIN_GROUP(scif3_clk),
4455         SH_PFC_PIN_GROUP(scif3_data_b),
4456         SH_PFC_PIN_GROUP(scif3_clk_b),
4457         SH_PFC_PIN_GROUP(scif3_data_c),
4458         SH_PFC_PIN_GROUP(scif3_data_d),
4459         SH_PFC_PIN_GROUP(scif4_data),
4460         SH_PFC_PIN_GROUP(scif4_data_b),
4461         SH_PFC_PIN_GROUP(scif4_data_c),
4462         SH_PFC_PIN_GROUP(scif5_data),
4463         SH_PFC_PIN_GROUP(scif5_data_b),
4464         SH_PFC_PIN_GROUP(scifa0_data),
4465         SH_PFC_PIN_GROUP(scifa0_data_b),
4466         SH_PFC_PIN_GROUP(scifa1_data),
4467         SH_PFC_PIN_GROUP(scifa1_clk),
4468         SH_PFC_PIN_GROUP(scifa1_data_b),
4469         SH_PFC_PIN_GROUP(scifa1_clk_b),
4470         SH_PFC_PIN_GROUP(scifa1_data_c),
4471         SH_PFC_PIN_GROUP(scifa2_data),
4472         SH_PFC_PIN_GROUP(scifa2_clk),
4473         SH_PFC_PIN_GROUP(scifa2_data_b),
4474         SH_PFC_PIN_GROUP(scifa3_data),
4475         SH_PFC_PIN_GROUP(scifa3_clk),
4476         SH_PFC_PIN_GROUP(scifa3_data_b),
4477         SH_PFC_PIN_GROUP(scifa3_clk_b),
4478         SH_PFC_PIN_GROUP(scifa3_data_c),
4479         SH_PFC_PIN_GROUP(scifa3_clk_c),
4480         SH_PFC_PIN_GROUP(scifa4_data),
4481         SH_PFC_PIN_GROUP(scifa4_data_b),
4482         SH_PFC_PIN_GROUP(scifa4_data_c),
4483         SH_PFC_PIN_GROUP(scifa5_data),
4484         SH_PFC_PIN_GROUP(scifa5_data_b),
4485         SH_PFC_PIN_GROUP(scifa5_data_c),
4486         SH_PFC_PIN_GROUP(scifb0_data),
4487         SH_PFC_PIN_GROUP(scifb0_clk),
4488         SH_PFC_PIN_GROUP(scifb0_ctrl),
4489         SH_PFC_PIN_GROUP(scifb0_data_b),
4490         SH_PFC_PIN_GROUP(scifb0_clk_b),
4491         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4492         SH_PFC_PIN_GROUP(scifb0_data_c),
4493         SH_PFC_PIN_GROUP(scifb0_clk_c),
4494         SH_PFC_PIN_GROUP(scifb0_data_d),
4495         SH_PFC_PIN_GROUP(scifb0_clk_d),
4496         SH_PFC_PIN_GROUP(scifb1_data),
4497         SH_PFC_PIN_GROUP(scifb1_clk),
4498         SH_PFC_PIN_GROUP(scifb1_ctrl),
4499         SH_PFC_PIN_GROUP(scifb1_data_b),
4500         SH_PFC_PIN_GROUP(scifb1_clk_b),
4501         SH_PFC_PIN_GROUP(scifb1_data_c),
4502         SH_PFC_PIN_GROUP(scifb1_clk_c),
4503         SH_PFC_PIN_GROUP(scifb1_data_d),
4504         SH_PFC_PIN_GROUP(scifb2_data),
4505         SH_PFC_PIN_GROUP(scifb2_clk),
4506         SH_PFC_PIN_GROUP(scifb2_ctrl),
4507         SH_PFC_PIN_GROUP(scifb2_data_b),
4508         SH_PFC_PIN_GROUP(scifb2_clk_b),
4509         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4510         SH_PFC_PIN_GROUP(scifb2_data_c),
4511         SH_PFC_PIN_GROUP(scifb2_clk_c),
4512         SH_PFC_PIN_GROUP(scifb2_data_d),
4513         SH_PFC_PIN_GROUP(sdhi0_data1),
4514         SH_PFC_PIN_GROUP(sdhi0_data4),
4515         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4516         SH_PFC_PIN_GROUP(sdhi0_cd),
4517         SH_PFC_PIN_GROUP(sdhi0_wp),
4518         SH_PFC_PIN_GROUP(sdhi1_data1),
4519         SH_PFC_PIN_GROUP(sdhi1_data4),
4520         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4521         SH_PFC_PIN_GROUP(sdhi1_cd),
4522         SH_PFC_PIN_GROUP(sdhi1_wp),
4523         SH_PFC_PIN_GROUP(sdhi2_data1),
4524         SH_PFC_PIN_GROUP(sdhi2_data4),
4525         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4526         SH_PFC_PIN_GROUP(sdhi2_cd),
4527         SH_PFC_PIN_GROUP(sdhi2_wp),
4528         SH_PFC_PIN_GROUP(ssi0_data),
4529         SH_PFC_PIN_GROUP(ssi0_data_b),
4530         SH_PFC_PIN_GROUP(ssi0129_ctrl),
4531         SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4532         SH_PFC_PIN_GROUP(ssi1_data),
4533         SH_PFC_PIN_GROUP(ssi1_data_b),
4534         SH_PFC_PIN_GROUP(ssi1_ctrl),
4535         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4536         SH_PFC_PIN_GROUP(ssi2_data),
4537         SH_PFC_PIN_GROUP(ssi2_ctrl),
4538         SH_PFC_PIN_GROUP(ssi3_data),
4539         SH_PFC_PIN_GROUP(ssi34_ctrl),
4540         SH_PFC_PIN_GROUP(ssi4_data),
4541         SH_PFC_PIN_GROUP(ssi4_ctrl),
4542         SH_PFC_PIN_GROUP(ssi5_data),
4543         SH_PFC_PIN_GROUP(ssi5_ctrl),
4544         SH_PFC_PIN_GROUP(ssi6_data),
4545         SH_PFC_PIN_GROUP(ssi6_ctrl),
4546         SH_PFC_PIN_GROUP(ssi7_data),
4547         SH_PFC_PIN_GROUP(ssi7_data_b),
4548         SH_PFC_PIN_GROUP(ssi78_ctrl),
4549         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4550         SH_PFC_PIN_GROUP(ssi8_data),
4551         SH_PFC_PIN_GROUP(ssi8_data_b),
4552         SH_PFC_PIN_GROUP(ssi9_data),
4553         SH_PFC_PIN_GROUP(ssi9_data_b),
4554         SH_PFC_PIN_GROUP(ssi9_ctrl),
4555         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4556         SH_PFC_PIN_GROUP(usb0),
4557         SH_PFC_PIN_GROUP(usb1),
4558         VIN_DATA_PIN_GROUP(vin0_data, 24),
4559         VIN_DATA_PIN_GROUP(vin0_data, 20),
4560         SH_PFC_PIN_GROUP(vin0_data18),
4561         VIN_DATA_PIN_GROUP(vin0_data, 16),
4562         VIN_DATA_PIN_GROUP(vin0_data, 12),
4563         VIN_DATA_PIN_GROUP(vin0_data, 10),
4564         VIN_DATA_PIN_GROUP(vin0_data, 8),
4565         SH_PFC_PIN_GROUP(vin0_sync),
4566         SH_PFC_PIN_GROUP(vin0_field),
4567         SH_PFC_PIN_GROUP(vin0_clkenb),
4568         SH_PFC_PIN_GROUP(vin0_clk),
4569         SH_PFC_PIN_GROUP(vin1_data8),
4570         SH_PFC_PIN_GROUP(vin1_sync),
4571         SH_PFC_PIN_GROUP(vin1_field),
4572         SH_PFC_PIN_GROUP(vin1_clkenb),
4573         SH_PFC_PIN_GROUP(vin1_clk),
4574         VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4575         VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4576         SH_PFC_PIN_GROUP(vin1_b_data18),
4577         VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4578         VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4579         VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4580         VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4581         SH_PFC_PIN_GROUP(vin1_b_sync),
4582         SH_PFC_PIN_GROUP(vin1_b_field),
4583         SH_PFC_PIN_GROUP(vin1_b_clkenb),
4584         SH_PFC_PIN_GROUP(vin1_b_clk),
4585         SH_PFC_PIN_GROUP(vin2_data8),
4586         SH_PFC_PIN_GROUP(vin2_sync),
4587         SH_PFC_PIN_GROUP(vin2_field),
4588         SH_PFC_PIN_GROUP(vin2_clkenb),
4589         SH_PFC_PIN_GROUP(vin2_clk),
4590 };
4591
4592 static const char * const audio_clk_groups[] = {
4593         "audio_clk_a",
4594         "audio_clk_b",
4595         "audio_clk_b_b",
4596         "audio_clk_c",
4597         "audio_clkout",
4598 };
4599
4600 static const char * const can0_groups[] = {
4601         "can0_data",
4602         "can0_data_b",
4603         "can0_data_c",
4604         "can0_data_d",
4605         "can0_data_e",
4606         "can0_data_f",
4607         "can_clk",
4608         "can_clk_b",
4609         "can_clk_c",
4610         "can_clk_d",
4611 };
4612
4613 static const char * const can1_groups[] = {
4614         "can1_data",
4615         "can1_data_b",
4616         "can1_data_c",
4617         "can1_data_d",
4618         "can_clk",
4619         "can_clk_b",
4620         "can_clk_c",
4621         "can_clk_d",
4622 };
4623
4624 static const char * const du_groups[] = {
4625         "du_rgb666",
4626         "du_rgb888",
4627         "du_clk_out_0",
4628         "du_clk_out_1",
4629         "du_sync",
4630         "du_oddf",
4631         "du_cde",
4632         "du_disp",
4633 };
4634
4635 static const char * const du0_groups[] = {
4636         "du0_clk_in",
4637 };
4638
4639 static const char * const du1_groups[] = {
4640         "du1_clk_in",
4641         "du1_clk_in_b",
4642         "du1_clk_in_c",
4643 };
4644
4645 static const char * const eth_groups[] = {
4646         "eth_link",
4647         "eth_magic",
4648         "eth_mdio",
4649         "eth_rmii",
4650 };
4651
4652 static const char * const hscif0_groups[] = {
4653         "hscif0_data",
4654         "hscif0_clk",
4655         "hscif0_ctrl",
4656         "hscif0_data_b",
4657         "hscif0_ctrl_b",
4658         "hscif0_data_c",
4659         "hscif0_clk_c",
4660 };
4661
4662 static const char * const hscif1_groups[] = {
4663         "hscif1_data",
4664         "hscif1_clk",
4665         "hscif1_ctrl",
4666         "hscif1_data_b",
4667         "hscif1_data_c",
4668         "hscif1_clk_c",
4669         "hscif1_ctrl_c",
4670         "hscif1_data_d",
4671         "hscif1_data_e",
4672         "hscif1_clk_e",
4673         "hscif1_ctrl_e",
4674 };
4675
4676 static const char * const hscif2_groups[] = {
4677         "hscif2_data",
4678         "hscif2_clk",
4679         "hscif2_ctrl",
4680         "hscif2_data_b",
4681         "hscif2_ctrl_b",
4682         "hscif2_data_c",
4683         "hscif2_clk_c",
4684         "hscif2_data_d",
4685 };
4686
4687 static const char * const i2c0_groups[] = {
4688         "i2c0",
4689         "i2c0_b",
4690         "i2c0_c",
4691 };
4692
4693 static const char * const i2c1_groups[] = {
4694         "i2c1",
4695         "i2c1_b",
4696         "i2c1_c",
4697         "i2c1_d",
4698         "i2c1_e",
4699 };
4700
4701 static const char * const i2c2_groups[] = {
4702         "i2c2",
4703         "i2c2_b",
4704         "i2c2_c",
4705         "i2c2_d",
4706 };
4707
4708 static const char * const i2c3_groups[] = {
4709         "i2c3",
4710         "i2c3_b",
4711         "i2c3_c",
4712         "i2c3_d",
4713 };
4714
4715 static const char * const i2c4_groups[] = {
4716         "i2c4",
4717         "i2c4_b",
4718         "i2c4_c",
4719 };
4720
4721 static const char * const i2c7_groups[] = {
4722         "i2c7",
4723         "i2c7_b",
4724         "i2c7_c",
4725 };
4726
4727 static const char * const i2c8_groups[] = {
4728         "i2c8",
4729         "i2c8_b",
4730         "i2c8_c",
4731 };
4732
4733 static const char * const intc_groups[] = {
4734         "intc_irq0",
4735         "intc_irq1",
4736         "intc_irq2",
4737         "intc_irq3",
4738 };
4739
4740 static const char * const mlb_groups[] = {
4741         "mlb_3pin",
4742 };
4743
4744 static const char * const mmc_groups[] = {
4745         "mmc_data1",
4746         "mmc_data4",
4747         "mmc_data8",
4748         "mmc_ctrl",
4749 };
4750
4751 static const char * const msiof0_groups[] = {
4752         "msiof0_clk",
4753         "msiof0_sync",
4754         "msiof0_ss1",
4755         "msiof0_ss2",
4756         "msiof0_rx",
4757         "msiof0_tx",
4758         "msiof0_clk_b",
4759         "msiof0_sync_b",
4760         "msiof0_ss1_b",
4761         "msiof0_ss2_b",
4762         "msiof0_rx_b",
4763         "msiof0_tx_b",
4764         "msiof0_clk_c",
4765         "msiof0_sync_c",
4766         "msiof0_ss1_c",
4767         "msiof0_ss2_c",
4768         "msiof0_rx_c",
4769         "msiof0_tx_c",
4770 };
4771
4772 static const char * const msiof1_groups[] = {
4773         "msiof1_clk",
4774         "msiof1_sync",
4775         "msiof1_ss1",
4776         "msiof1_ss2",
4777         "msiof1_rx",
4778         "msiof1_tx",
4779         "msiof1_clk_b",
4780         "msiof1_sync_b",
4781         "msiof1_ss1_b",
4782         "msiof1_ss2_b",
4783         "msiof1_rx_b",
4784         "msiof1_tx_b",
4785         "msiof1_clk_c",
4786         "msiof1_sync_c",
4787         "msiof1_rx_c",
4788         "msiof1_tx_c",
4789         "msiof1_clk_d",
4790         "msiof1_sync_d",
4791         "msiof1_ss1_d",
4792         "msiof1_rx_d",
4793         "msiof1_tx_d",
4794         "msiof1_clk_e",
4795         "msiof1_sync_e",
4796         "msiof1_rx_e",
4797         "msiof1_tx_e",
4798 };
4799
4800 static const char * const msiof2_groups[] = {
4801         "msiof2_clk",
4802         "msiof2_sync",
4803         "msiof2_ss1",
4804         "msiof2_ss2",
4805         "msiof2_rx",
4806         "msiof2_tx",
4807         "msiof2_clk_b",
4808         "msiof2_sync_b",
4809         "msiof2_ss1_b",
4810         "msiof2_ss2_b",
4811         "msiof2_rx_b",
4812         "msiof2_tx_b",
4813         "msiof2_clk_c",
4814         "msiof2_sync_c",
4815         "msiof2_rx_c",
4816         "msiof2_tx_c",
4817         "msiof2_clk_d",
4818         "msiof2_sync_d",
4819         "msiof2_ss1_d",
4820         "msiof2_ss2_d",
4821         "msiof2_rx_d",
4822         "msiof2_tx_d",
4823         "msiof2_clk_e",
4824         "msiof2_sync_e",
4825         "msiof2_rx_e",
4826         "msiof2_tx_e",
4827 };
4828
4829 static const char * const pwm0_groups[] = {
4830         "pwm0",
4831         "pwm0_b",
4832 };
4833
4834 static const char * const pwm1_groups[] = {
4835         "pwm1",
4836         "pwm1_b",
4837 };
4838
4839 static const char * const pwm2_groups[] = {
4840         "pwm2",
4841         "pwm2_b",
4842 };
4843
4844 static const char * const pwm3_groups[] = {
4845         "pwm3",
4846 };
4847
4848 static const char * const pwm4_groups[] = {
4849         "pwm4",
4850         "pwm4_b",
4851 };
4852
4853 static const char * const pwm5_groups[] = {
4854         "pwm5",
4855         "pwm5_b",
4856 };
4857
4858 static const char * const pwm6_groups[] = {
4859         "pwm6",
4860 };
4861
4862 static const char * const qspi_groups[] = {
4863         "qspi_ctrl",
4864         "qspi_data2",
4865         "qspi_data4",
4866         "qspi_ctrl_b",
4867         "qspi_data2_b",
4868         "qspi_data4_b",
4869 };
4870
4871 static const char * const scif0_groups[] = {
4872         "scif0_data",
4873         "scif0_data_b",
4874         "scif0_data_c",
4875         "scif0_data_d",
4876         "scif0_data_e",
4877 };
4878
4879 static const char * const scif1_groups[] = {
4880         "scif1_data",
4881         "scif1_data_b",
4882         "scif1_clk_b",
4883         "scif1_data_c",
4884         "scif1_data_d",
4885 };
4886
4887 static const char * const scif2_groups[] = {
4888         "scif2_data",
4889         "scif2_data_b",
4890         "scif2_clk_b",
4891         "scif2_data_c",
4892         "scif2_data_e",
4893 };
4894 static const char * const scif3_groups[] = {
4895         "scif3_data",
4896         "scif3_clk",
4897         "scif3_data_b",
4898         "scif3_clk_b",
4899         "scif3_data_c",
4900         "scif3_data_d",
4901 };
4902 static const char * const scif4_groups[] = {
4903         "scif4_data",
4904         "scif4_data_b",
4905         "scif4_data_c",
4906 };
4907 static const char * const scif5_groups[] = {
4908         "scif5_data",
4909         "scif5_data_b",
4910 };
4911 static const char * const scifa0_groups[] = {
4912         "scifa0_data",
4913         "scifa0_data_b",
4914 };
4915 static const char * const scifa1_groups[] = {
4916         "scifa1_data",
4917         "scifa1_clk",
4918         "scifa1_data_b",
4919         "scifa1_clk_b",
4920         "scifa1_data_c",
4921 };
4922 static const char * const scifa2_groups[] = {
4923         "scifa2_data",
4924         "scifa2_clk",
4925         "scifa2_data_b",
4926 };
4927 static const char * const scifa3_groups[] = {
4928         "scifa3_data",
4929         "scifa3_clk",
4930         "scifa3_data_b",
4931         "scifa3_clk_b",
4932         "scifa3_data_c",
4933         "scifa3_clk_c",
4934 };
4935 static const char * const scifa4_groups[] = {
4936         "scifa4_data",
4937         "scifa4_data_b",
4938         "scifa4_data_c",
4939 };
4940 static const char * const scifa5_groups[] = {
4941         "scifa5_data",
4942         "scifa5_data_b",
4943         "scifa5_data_c",
4944 };
4945 static const char * const scifb0_groups[] = {
4946         "scifb0_data",
4947         "scifb0_clk",
4948         "scifb0_ctrl",
4949         "scifb0_data_b",
4950         "scifb0_clk_b",
4951         "scifb0_ctrl_b",
4952         "scifb0_data_c",
4953         "scifb0_clk_c",
4954         "scifb0_data_d",
4955         "scifb0_clk_d",
4956 };
4957 static const char * const scifb1_groups[] = {
4958         "scifb1_data",
4959         "scifb1_clk",
4960         "scifb1_ctrl",
4961         "scifb1_data_b",
4962         "scifb1_clk_b",
4963         "scifb1_data_c",
4964         "scifb1_clk_c",
4965         "scifb1_data_d",
4966 };
4967 static const char * const scifb2_groups[] = {
4968         "scifb2_data",
4969         "scifb2_clk",
4970         "scifb2_ctrl",
4971         "scifb2_data_b",
4972         "scifb2_clk_b",
4973         "scifb2_ctrl_b",
4974         "scifb0_data_c",
4975         "scifb2_clk_c",
4976         "scifb2_data_d",
4977 };
4978
4979 static const char * const sdhi0_groups[] = {
4980         "sdhi0_data1",
4981         "sdhi0_data4",
4982         "sdhi0_ctrl",
4983         "sdhi0_cd",
4984         "sdhi0_wp",
4985 };
4986
4987 static const char * const sdhi1_groups[] = {
4988         "sdhi1_data1",
4989         "sdhi1_data4",
4990         "sdhi1_ctrl",
4991         "sdhi1_cd",
4992         "sdhi1_wp",
4993 };
4994
4995 static const char * const sdhi2_groups[] = {
4996         "sdhi2_data1",
4997         "sdhi2_data4",
4998         "sdhi2_ctrl",
4999         "sdhi2_cd",
5000         "sdhi2_wp",
5001 };
5002
5003 static const char * const ssi_groups[] = {
5004         "ssi0_data",
5005         "ssi0_data_b",
5006         "ssi0129_ctrl",
5007         "ssi0129_ctrl_b",
5008         "ssi1_data",
5009         "ssi1_data_b",
5010         "ssi1_ctrl",
5011         "ssi1_ctrl_b",
5012         "ssi2_data",
5013         "ssi2_ctrl",
5014         "ssi3_data",
5015         "ssi34_ctrl",
5016         "ssi4_data",
5017         "ssi4_ctrl",
5018         "ssi5_data",
5019         "ssi5_ctrl",
5020         "ssi6_data",
5021         "ssi6_ctrl",
5022         "ssi7_data",
5023         "ssi7_data_b",
5024         "ssi78_ctrl",
5025         "ssi78_ctrl_b",
5026         "ssi8_data",
5027         "ssi8_data_b",
5028         "ssi9_data",
5029         "ssi9_data_b",
5030         "ssi9_ctrl",
5031         "ssi9_ctrl_b",
5032 };
5033
5034 static const char * const usb0_groups[] = {
5035         "usb0",
5036 };
5037 static const char * const usb1_groups[] = {
5038         "usb1",
5039 };
5040
5041 static const char * const vin0_groups[] = {
5042         "vin0_data24",
5043         "vin0_data20",
5044         "vin0_data18",
5045         "vin0_data16",
5046         "vin0_data12",
5047         "vin0_data10",
5048         "vin0_data8",
5049         "vin0_sync",
5050         "vin0_field",
5051         "vin0_clkenb",
5052         "vin0_clk",
5053 };
5054
5055 static const char * const vin1_groups[] = {
5056         "vin1_data8",
5057         "vin1_sync",
5058         "vin1_field",
5059         "vin1_clkenb",
5060         "vin1_clk",
5061         "vin1_b_data24",
5062         "vin1_b_data20",
5063         "vin1_b_data18",
5064         "vin1_b_data16",
5065         "vin1_b_data12",
5066         "vin1_b_data10",
5067         "vin1_b_data8",
5068         "vin1_b_sync",
5069         "vin1_b_field",
5070         "vin1_b_clkenb",
5071         "vin1_b_clk",
5072 };
5073
5074 static const char * const vin2_groups[] = {
5075         "vin2_data8",
5076         "vin2_sync",
5077         "vin2_field",
5078         "vin2_clkenb",
5079         "vin2_clk",
5080 };
5081
5082 static const struct sh_pfc_function pinmux_functions[] = {
5083         SH_PFC_FUNCTION(audio_clk),
5084         SH_PFC_FUNCTION(can0),
5085         SH_PFC_FUNCTION(can1),
5086         SH_PFC_FUNCTION(du),
5087         SH_PFC_FUNCTION(du0),
5088         SH_PFC_FUNCTION(du1),
5089         SH_PFC_FUNCTION(eth),
5090         SH_PFC_FUNCTION(hscif0),
5091         SH_PFC_FUNCTION(hscif1),
5092         SH_PFC_FUNCTION(hscif2),
5093         SH_PFC_FUNCTION(i2c0),
5094         SH_PFC_FUNCTION(i2c1),
5095         SH_PFC_FUNCTION(i2c2),
5096         SH_PFC_FUNCTION(i2c3),
5097         SH_PFC_FUNCTION(i2c4),
5098         SH_PFC_FUNCTION(i2c7),
5099         SH_PFC_FUNCTION(i2c8),
5100         SH_PFC_FUNCTION(intc),
5101         SH_PFC_FUNCTION(mlb),
5102         SH_PFC_FUNCTION(mmc),
5103         SH_PFC_FUNCTION(msiof0),
5104         SH_PFC_FUNCTION(msiof1),
5105         SH_PFC_FUNCTION(msiof2),
5106         SH_PFC_FUNCTION(pwm0),
5107         SH_PFC_FUNCTION(pwm1),
5108         SH_PFC_FUNCTION(pwm2),
5109         SH_PFC_FUNCTION(pwm3),
5110         SH_PFC_FUNCTION(pwm4),
5111         SH_PFC_FUNCTION(pwm5),
5112         SH_PFC_FUNCTION(pwm6),
5113         SH_PFC_FUNCTION(qspi),
5114         SH_PFC_FUNCTION(scif0),
5115         SH_PFC_FUNCTION(scif1),
5116         SH_PFC_FUNCTION(scif2),
5117         SH_PFC_FUNCTION(scif3),
5118         SH_PFC_FUNCTION(scif4),
5119         SH_PFC_FUNCTION(scif5),
5120         SH_PFC_FUNCTION(scifa0),
5121         SH_PFC_FUNCTION(scifa1),
5122         SH_PFC_FUNCTION(scifa2),
5123         SH_PFC_FUNCTION(scifa3),
5124         SH_PFC_FUNCTION(scifa4),
5125         SH_PFC_FUNCTION(scifa5),
5126         SH_PFC_FUNCTION(scifb0),
5127         SH_PFC_FUNCTION(scifb1),
5128         SH_PFC_FUNCTION(scifb2),
5129         SH_PFC_FUNCTION(sdhi0),
5130         SH_PFC_FUNCTION(sdhi1),
5131         SH_PFC_FUNCTION(sdhi2),
5132         SH_PFC_FUNCTION(ssi),
5133         SH_PFC_FUNCTION(usb0),
5134         SH_PFC_FUNCTION(usb1),
5135         SH_PFC_FUNCTION(vin0),
5136         SH_PFC_FUNCTION(vin1),
5137         SH_PFC_FUNCTION(vin2),
5138 };
5139
5140 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5141         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5142                 GP_0_31_FN, FN_IP1_22_20,
5143                 GP_0_30_FN, FN_IP1_19_17,
5144                 GP_0_29_FN, FN_IP1_16_14,
5145                 GP_0_28_FN, FN_IP1_13_11,
5146                 GP_0_27_FN, FN_IP1_10_8,
5147                 GP_0_26_FN, FN_IP1_7_6,
5148                 GP_0_25_FN, FN_IP1_5_4,
5149                 GP_0_24_FN, FN_IP1_3_2,
5150                 GP_0_23_FN, FN_IP1_1_0,
5151                 GP_0_22_FN, FN_IP0_30_29,
5152                 GP_0_21_FN, FN_IP0_28_27,
5153                 GP_0_20_FN, FN_IP0_26_25,
5154                 GP_0_19_FN, FN_IP0_24_23,
5155                 GP_0_18_FN, FN_IP0_22_21,
5156                 GP_0_17_FN, FN_IP0_20_19,
5157                 GP_0_16_FN, FN_IP0_18_16,
5158                 GP_0_15_FN, FN_IP0_15,
5159                 GP_0_14_FN, FN_IP0_14,
5160                 GP_0_13_FN, FN_IP0_13,
5161                 GP_0_12_FN, FN_IP0_12,
5162                 GP_0_11_FN, FN_IP0_11,
5163                 GP_0_10_FN, FN_IP0_10,
5164                 GP_0_9_FN, FN_IP0_9,
5165                 GP_0_8_FN, FN_IP0_8,
5166                 GP_0_7_FN, FN_IP0_7,
5167                 GP_0_6_FN, FN_IP0_6,
5168                 GP_0_5_FN, FN_IP0_5,
5169                 GP_0_4_FN, FN_IP0_4,
5170                 GP_0_3_FN, FN_IP0_3,
5171                 GP_0_2_FN, FN_IP0_2,
5172                 GP_0_1_FN, FN_IP0_1,
5173                 GP_0_0_FN, FN_IP0_0, }
5174         },
5175         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5176                 0, 0,
5177                 0, 0,
5178                 0, 0,
5179                 0, 0,
5180                 0, 0,
5181                 0, 0,
5182                 GP_1_25_FN, FN_IP3_21_20,
5183                 GP_1_24_FN, FN_IP3_19_18,
5184                 GP_1_23_FN, FN_IP3_17_16,
5185                 GP_1_22_FN, FN_IP3_15_14,
5186                 GP_1_21_FN, FN_IP3_13_12,
5187                 GP_1_20_FN, FN_IP3_11_9,
5188                 GP_1_19_FN, FN_RD_N,
5189                 GP_1_18_FN, FN_IP3_8_6,
5190                 GP_1_17_FN, FN_IP3_5_3,
5191                 GP_1_16_FN, FN_IP3_2_0,
5192                 GP_1_15_FN, FN_IP2_29_27,
5193                 GP_1_14_FN, FN_IP2_26_25,
5194                 GP_1_13_FN, FN_IP2_24_23,
5195                 GP_1_12_FN, FN_EX_CS0_N,
5196                 GP_1_11_FN, FN_IP2_22_21,
5197                 GP_1_10_FN, FN_IP2_20_19,
5198                 GP_1_9_FN, FN_IP2_18_16,
5199                 GP_1_8_FN, FN_IP2_15_13,
5200                 GP_1_7_FN, FN_IP2_12_10,
5201                 GP_1_6_FN, FN_IP2_9_7,
5202                 GP_1_5_FN, FN_IP2_6_5,
5203                 GP_1_4_FN, FN_IP2_4_3,
5204                 GP_1_3_FN, FN_IP2_2_0,
5205                 GP_1_2_FN, FN_IP1_31_29,
5206                 GP_1_1_FN, FN_IP1_28_26,
5207                 GP_1_0_FN, FN_IP1_25_23, }
5208         },
5209         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5210                 GP_2_31_FN, FN_IP6_7_6,
5211                 GP_2_30_FN, FN_IP6_5_3,
5212                 GP_2_29_FN, FN_IP6_2_0,
5213                 GP_2_28_FN, FN_AUDIO_CLKA,
5214                 GP_2_27_FN, FN_IP5_31_29,
5215                 GP_2_26_FN, FN_IP5_28_26,
5216                 GP_2_25_FN, FN_IP5_25_24,
5217                 GP_2_24_FN, FN_IP5_23_22,
5218                 GP_2_23_FN, FN_IP5_21_20,
5219                 GP_2_22_FN, FN_IP5_19_17,
5220                 GP_2_21_FN, FN_IP5_16_15,
5221                 GP_2_20_FN, FN_IP5_14_12,
5222                 GP_2_19_FN, FN_IP5_11_9,
5223                 GP_2_18_FN, FN_IP5_8_6,
5224                 GP_2_17_FN, FN_IP5_5_3,
5225                 GP_2_16_FN, FN_IP5_2_0,
5226                 GP_2_15_FN, FN_IP4_30_28,
5227                 GP_2_14_FN, FN_IP4_27_26,
5228                 GP_2_13_FN, FN_IP4_25_24,
5229                 GP_2_12_FN, FN_IP4_23_22,
5230                 GP_2_11_FN, FN_IP4_21,
5231                 GP_2_10_FN, FN_IP4_20,
5232                 GP_2_9_FN, FN_IP4_19,
5233                 GP_2_8_FN, FN_IP4_18_16,
5234                 GP_2_7_FN, FN_IP4_15_13,
5235                 GP_2_6_FN, FN_IP4_12_10,
5236                 GP_2_5_FN, FN_IP4_9_8,
5237                 GP_2_4_FN, FN_IP4_7_5,
5238                 GP_2_3_FN, FN_IP4_4_2,
5239                 GP_2_2_FN, FN_IP4_1_0,
5240                 GP_2_1_FN, FN_IP3_30_28,
5241                 GP_2_0_FN, FN_IP3_27_25 }
5242         },
5243         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5244                 GP_3_31_FN, FN_IP9_18_17,
5245                 GP_3_30_FN, FN_IP9_16,
5246                 GP_3_29_FN, FN_IP9_15_13,
5247                 GP_3_28_FN, FN_IP9_12,
5248                 GP_3_27_FN, FN_IP9_11,
5249                 GP_3_26_FN, FN_IP9_10_8,
5250                 GP_3_25_FN, FN_IP9_7,
5251                 GP_3_24_FN, FN_IP9_6,
5252                 GP_3_23_FN, FN_IP9_5_3,
5253                 GP_3_22_FN, FN_IP9_2_0,
5254                 GP_3_21_FN, FN_IP8_30_28,
5255                 GP_3_20_FN, FN_IP8_27_26,
5256                 GP_3_19_FN, FN_IP8_25_24,
5257                 GP_3_18_FN, FN_IP8_23_21,
5258                 GP_3_17_FN, FN_IP8_20_18,
5259                 GP_3_16_FN, FN_IP8_17_15,
5260                 GP_3_15_FN, FN_IP8_14_12,
5261                 GP_3_14_FN, FN_IP8_11_9,
5262                 GP_3_13_FN, FN_IP8_8_6,
5263                 GP_3_12_FN, FN_IP8_5_3,
5264                 GP_3_11_FN, FN_IP8_2_0,
5265                 GP_3_10_FN, FN_IP7_29_27,
5266                 GP_3_9_FN, FN_IP7_26_24,
5267                 GP_3_8_FN, FN_IP7_23_21,
5268                 GP_3_7_FN, FN_IP7_20_19,
5269                 GP_3_6_FN, FN_IP7_18_17,
5270                 GP_3_5_FN, FN_IP7_16_15,
5271                 GP_3_4_FN, FN_IP7_14_13,
5272                 GP_3_3_FN, FN_IP7_12_11,
5273                 GP_3_2_FN, FN_IP7_10_9,
5274                 GP_3_1_FN, FN_IP7_8_6,
5275                 GP_3_0_FN, FN_IP7_5_3 }
5276         },
5277         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5278                 GP_4_31_FN, FN_IP15_5_4,
5279                 GP_4_30_FN, FN_IP15_3_2,
5280                 GP_4_29_FN, FN_IP15_1_0,
5281                 GP_4_28_FN, FN_IP11_8_6,
5282                 GP_4_27_FN, FN_IP11_5_3,
5283                 GP_4_26_FN, FN_IP11_2_0,
5284                 GP_4_25_FN, FN_IP10_31_29,
5285                 GP_4_24_FN, FN_IP10_28_27,
5286                 GP_4_23_FN, FN_IP10_26_25,
5287                 GP_4_22_FN, FN_IP10_24_22,
5288                 GP_4_21_FN, FN_IP10_21_19,
5289                 GP_4_20_FN, FN_IP10_18_17,
5290                 GP_4_19_FN, FN_IP10_16_15,
5291                 GP_4_18_FN, FN_IP10_14_12,
5292                 GP_4_17_FN, FN_IP10_11_9,
5293                 GP_4_16_FN, FN_IP10_8_6,
5294                 GP_4_15_FN, FN_IP10_5_3,
5295                 GP_4_14_FN, FN_IP10_2_0,
5296                 GP_4_13_FN, FN_IP9_31_29,
5297                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5298                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5299                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5300                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5301                 GP_4_8_FN, FN_IP9_28_27,
5302                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5303                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5304                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5305                 GP_4_4_FN, FN_IP9_26_25,
5306                 GP_4_3_FN, FN_IP9_24_23,
5307                 GP_4_2_FN, FN_IP9_22_21,
5308                 GP_4_1_FN, FN_IP9_20_19,
5309                 GP_4_0_FN, FN_VI0_CLK }
5310         },
5311         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5312                 GP_5_31_FN, FN_IP3_24_22,
5313                 GP_5_30_FN, FN_IP13_9_7,
5314                 GP_5_29_FN, FN_IP13_6_5,
5315                 GP_5_28_FN, FN_IP13_4_3,
5316                 GP_5_27_FN, FN_IP13_2_0,
5317                 GP_5_26_FN, FN_IP12_29_27,
5318                 GP_5_25_FN, FN_IP12_26_24,
5319                 GP_5_24_FN, FN_IP12_23_22,
5320                 GP_5_23_FN, FN_IP12_21_20,
5321                 GP_5_22_FN, FN_IP12_19_18,
5322                 GP_5_21_FN, FN_IP12_17_16,
5323                 GP_5_20_FN, FN_IP12_15_13,
5324                 GP_5_19_FN, FN_IP12_12_10,
5325                 GP_5_18_FN, FN_IP12_9_7,
5326                 GP_5_17_FN, FN_IP12_6_4,
5327                 GP_5_16_FN, FN_IP12_3_2,
5328                 GP_5_15_FN, FN_IP12_1_0,
5329                 GP_5_14_FN, FN_IP11_31_30,
5330                 GP_5_13_FN, FN_IP11_29_28,
5331                 GP_5_12_FN, FN_IP11_27,
5332                 GP_5_11_FN, FN_IP11_26,
5333                 GP_5_10_FN, FN_IP11_25,
5334                 GP_5_9_FN, FN_IP11_24,
5335                 GP_5_8_FN, FN_IP11_23,
5336                 GP_5_7_FN, FN_IP11_22,
5337                 GP_5_6_FN, FN_IP11_21,
5338                 GP_5_5_FN, FN_IP11_20,
5339                 GP_5_4_FN, FN_IP11_19,
5340                 GP_5_3_FN, FN_IP11_18_17,
5341                 GP_5_2_FN, FN_IP11_16_15,
5342                 GP_5_1_FN, FN_IP11_14_12,
5343                 GP_5_0_FN, FN_IP11_11_9 }
5344         },
5345         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5346                 GP_6_31_FN, FN_DU0_DOTCLKIN,
5347                 GP_6_30_FN, FN_USB1_OVC,
5348                 GP_6_29_FN, FN_IP14_31_29,
5349                 GP_6_28_FN, FN_IP14_28_26,
5350                 GP_6_27_FN, FN_IP14_25_23,
5351                 GP_6_26_FN, FN_IP14_22_20,
5352                 GP_6_25_FN, FN_IP14_19_17,
5353                 GP_6_24_FN, FN_IP14_16_14,
5354                 GP_6_23_FN, FN_IP14_13_11,
5355                 GP_6_22_FN, FN_IP14_10_8,
5356                 GP_6_21_FN, FN_IP14_7,
5357                 GP_6_20_FN, FN_IP14_6,
5358                 GP_6_19_FN, FN_IP14_5,
5359                 GP_6_18_FN, FN_IP14_4,
5360                 GP_6_17_FN, FN_IP14_3,
5361                 GP_6_16_FN, FN_IP14_2,
5362                 GP_6_15_FN, FN_IP14_1_0,
5363                 GP_6_14_FN, FN_IP13_30_28,
5364                 GP_6_13_FN, FN_IP13_27,
5365                 GP_6_12_FN, FN_IP13_26,
5366                 GP_6_11_FN, FN_IP13_25,
5367                 GP_6_10_FN, FN_IP13_24_23,
5368                 GP_6_9_FN, FN_IP13_22,
5369                 GP_6_8_FN, FN_SD1_CLK,
5370                 GP_6_7_FN, FN_IP13_21_19,
5371                 GP_6_6_FN, FN_IP13_18_16,
5372                 GP_6_5_FN, FN_IP13_15,
5373                 GP_6_4_FN, FN_IP13_14,
5374                 GP_6_3_FN, FN_IP13_13,
5375                 GP_6_2_FN, FN_IP13_12,
5376                 GP_6_1_FN, FN_IP13_11,
5377                 GP_6_0_FN, FN_IP13_10 }
5378         },
5379         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5380                 0, 0,
5381                 0, 0,
5382                 0, 0,
5383                 0, 0,
5384                 0, 0,
5385                 0, 0,
5386                 GP_7_25_FN, FN_USB1_PWEN,
5387                 GP_7_24_FN, FN_USB0_OVC,
5388                 GP_7_23_FN, FN_USB0_PWEN,
5389                 GP_7_22_FN, FN_IP15_14_12,
5390                 GP_7_21_FN, FN_IP15_11_9,
5391                 GP_7_20_FN, FN_IP15_8_6,
5392                 GP_7_19_FN, FN_IP7_2_0,
5393                 GP_7_18_FN, FN_IP6_29_27,
5394                 GP_7_17_FN, FN_IP6_26_24,
5395                 GP_7_16_FN, FN_IP6_23_21,
5396                 GP_7_15_FN, FN_IP6_20_19,
5397                 GP_7_14_FN, FN_IP6_18_16,
5398                 GP_7_13_FN, FN_IP6_15_14,
5399                 GP_7_12_FN, FN_IP6_13_12,
5400                 GP_7_11_FN, FN_IP6_11_10,
5401                 GP_7_10_FN, FN_IP6_9_8,
5402                 GP_7_9_FN, FN_IP16_11_10,
5403                 GP_7_8_FN, FN_IP16_9_8,
5404                 GP_7_7_FN, FN_IP16_7_6,
5405                 GP_7_6_FN, FN_IP16_5_3,
5406                 GP_7_5_FN, FN_IP16_2_0,
5407                 GP_7_4_FN, FN_IP15_29_27,
5408                 GP_7_3_FN, FN_IP15_26_24,
5409                 GP_7_2_FN, FN_IP15_23_21,
5410                 GP_7_1_FN, FN_IP15_20_18,
5411                 GP_7_0_FN, FN_IP15_17_15 }
5412         },
5413         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5414                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5415                              1, 1, 1, 1, 1, 1, 1, 1) {
5416                 /* IP0_31 [1] */
5417                 0, 0,
5418                 /* IP0_30_29 [2] */
5419                 FN_A6, FN_MSIOF1_SCK,
5420                 0, 0,
5421                 /* IP0_28_27 [2] */
5422                 FN_A5, FN_MSIOF0_RXD_B,
5423                 0, 0,
5424                 /* IP0_26_25 [2] */
5425                 FN_A4, FN_MSIOF0_TXD_B,
5426                 0, 0,
5427                 /* IP0_24_23 [2] */
5428                 FN_A3, FN_MSIOF0_SS2_B,
5429                 0, 0,
5430                 /* IP0_22_21 [2] */
5431                 FN_A2, FN_MSIOF0_SS1_B,
5432                 0, 0,
5433                 /* IP0_20_19 [2] */
5434                 FN_A1, FN_MSIOF0_SYNC_B,
5435                 0, 0,
5436                 /* IP0_18_16 [3] */
5437                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
5438                 0, 0, 0,
5439                 /* IP0_15 [1] */
5440                 FN_D15, 0,
5441                 /* IP0_14 [1] */
5442                 FN_D14, 0,
5443                 /* IP0_13 [1] */
5444                 FN_D13, 0,
5445                 /* IP0_12 [1] */
5446                 FN_D12, 0,
5447                 /* IP0_11 [1] */
5448                 FN_D11, 0,
5449                 /* IP0_10 [1] */
5450                 FN_D10, 0,
5451                 /* IP0_9 [1] */
5452                 FN_D9, 0,
5453                 /* IP0_8 [1] */
5454                 FN_D8, 0,
5455                 /* IP0_7 [1] */
5456                 FN_D7, 0,
5457                 /* IP0_6 [1] */
5458                 FN_D6, 0,
5459                 /* IP0_5 [1] */
5460                 FN_D5, 0,
5461                 /* IP0_4 [1] */
5462                 FN_D4, 0,
5463                 /* IP0_3 [1] */
5464                 FN_D3, 0,
5465                 /* IP0_2 [1] */
5466                 FN_D2, 0,
5467                 /* IP0_1 [1] */
5468                 FN_D1, 0,
5469                 /* IP0_0 [1] */
5470                 FN_D0, 0, }
5471         },
5472         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5473                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5474                 /* IP1_31_29 [3] */
5475                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5476                 0, 0, 0,
5477                 /* IP1_28_26 [3] */
5478                 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
5479                 0, 0, 0, 0,
5480                 /* IP1_25_23 [3] */
5481                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5482                 0, 0, 0,
5483                 /* IP1_22_20 [3] */
5484                 FN_A15, FN_BPFCLK_C,
5485                 0, 0, 0, 0, 0, 0,
5486                 /* IP1_19_17 [3] */
5487                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5488                 0, 0, 0,
5489                 /* IP1_16_14 [3] */
5490                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5491                 0, 0, 0, 0,
5492                 /* IP1_13_11 [3] */
5493                 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
5494                 0, 0, 0, 0,
5495                 /* IP1_10_8 [3] */
5496                 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
5497                 0, 0, 0, 0,
5498                 /* IP1_7_6 [2] */
5499                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5500                 /* IP1_5_4 [2] */
5501                 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
5502                 /* IP1_3_2 [2] */
5503                 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
5504                 /* IP1_1_0 [2] */
5505                 FN_A7, FN_MSIOF1_SYNC,
5506                 0, 0, }
5507         },
5508         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5509                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5510                 /* IP2_31_20 [2] */
5511                 0, 0, 0, 0,
5512                 /* IP2_29_27 [3] */
5513                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5514                 FN_ATAG0_N, 0, FN_EX_WAIT1,
5515                 0, 0,
5516                 /* IP2_26_25 [2] */
5517                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5518                 /* IP2_24_23 [2] */
5519                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5520                 /* IP2_22_21 [2] */
5521                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
5522                 /* IP2_20_19 [2] */
5523                 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
5524                 /* IP2_18_16 [3] */
5525                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5526                 0, 0,
5527                 /* IP2_15_13 [3] */
5528                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5529                 0, 0, 0,
5530                 /* IP2_12_0 [3] */
5531                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5532                 0, 0, 0,
5533                 /* IP2_9_7 [3] */
5534                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5535                 0, 0, 0,
5536                 /* IP2_6_5 [2] */
5537                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5538                 /* IP2_4_3 [2] */
5539                 FN_A20, FN_SPCLK, 0, 0,
5540                 /* IP2_2_0 [3] */
5541                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5542                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5543         },
5544         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5545                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5546                 /* IP3_31 [1] */
5547                 0, 0,
5548                 /* IP3_30_28 [3] */
5549                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5550                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5551                 0, 0, 0,
5552                 /* IP3_27_25 [3] */
5553                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5554                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5555                 0, 0, 0,
5556                 /* IP3_24_22 [3] */
5557                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5558                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5559                 /* IP3_21_20 [2] */
5560                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5561                 /* IP3_19_18 [2] */
5562                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5563                 /* IP3_17_16 [2] */
5564                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5565                 /* IP3_15_14 [2] */
5566                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5567                 /* IP3_13_12 [2] */
5568                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5569                 /* IP3_11_9 [3] */
5570                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5571                 0, 0, 0,
5572                 /* IP3_8_6 [3] */
5573                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5574                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5575                 /* IP3_5_3 [3] */
5576                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5577                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5578                 /* IP3_2_0 [3] */
5579                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5580                 0, 0, 0, }
5581         },
5582         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5583                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5584                 /* IP4_31 [1] */
5585                 0, 0,
5586                 /* IP4_30_28 [3] */
5587                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5588                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5589                 0, 0,
5590                 /* IP4_27_26 [2] */
5591                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5592                 /* IP4_25_24 [2] */
5593                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5594                 /* IP4_23_22 [2] */
5595                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5596                 /* IP4_21 [1] */
5597                 FN_SSI_SDATA3, 0,
5598                 /* IP4_20 [1] */
5599                 FN_SSI_WS34, 0,
5600                 /* IP4_19 [1] */
5601                 FN_SSI_SCK34, 0,
5602                 /* IP4_18_16 [3] */
5603                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5604                 0, 0, 0, 0,
5605                 /* IP4_15_13 [3] */
5606                 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
5607                 FN_GLO_Q1_D, FN_HCTS1_N_E,
5608                 0, 0,
5609                 /* IP4_12_10 [3] */
5610                 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5611                 0, 0, 0,
5612                 /* IP4_9_8 [2] */
5613                 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
5614                 /* IP4_7_5 [3] */
5615                 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
5616                 0, 0, 0,
5617                 /* IP4_4_2 [3] */
5618                 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
5619                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5620                 0, 0, 0,
5621                 /* IP4_1_0 [2] */
5622                 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
5623         },
5624         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5625                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5626                 /* IP5_31_29 [3] */
5627                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5628                 0, 0, 0, 0, 0,
5629                 /* IP5_28_26 [3] */
5630                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5631                 0, 0, 0, 0,
5632                 /* IP5_25_24 [2] */
5633                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5634                 /* IP5_23_22 [2] */
5635                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5636                 /* IP5_21_20 [2] */
5637                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5638                 /* IP5_19_17 [3] */
5639                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5640                 0, 0, 0, 0,
5641                 /* IP5_16_15 [2] */
5642                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5643                 /* IP5_14_12 [3] */
5644                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5645                 0, 0, 0, 0,
5646                 /* IP5_11_9 [3] */
5647                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5648                 0, 0, 0, 0,
5649                 /* IP5_8_6 [3] */
5650                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5651                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5652                 0, 0,
5653                 /* IP5_5_3 [3] */
5654                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5655                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5656                 0, 0,
5657                 /* IP5_2_0 [3] */
5658                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5659                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5660                 0, 0, }
5661         },
5662         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5663                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5664                 /* IP6_31_30 [2] */
5665                 0, 0, 0, 0,
5666                 /* IP6_29_27 [3] */
5667                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5668                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5669                 0, 0, 0,
5670                 /* IP6_26_24 [3] */
5671                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5672                 FN_GPS_CLK_C, FN_GPS_CLK_D,
5673                 0, 0, 0,
5674                 /* IP6_23_21 [3] */
5675                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5676                 FN_SDA1_E, FN_MSIOF2_SYNC_E,
5677                 0, 0, 0,
5678                 /* IP6_20_19 [2] */
5679                 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
5680                 /* IP6_18_16 [3] */
5681                 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
5682                 0, 0, 0,
5683                 /* IP6_15_14 [2] */
5684                 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5685                 /* IP6_13_12 [2] */
5686                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5687                 /* IP6_11_10 [2] */
5688                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5689                 /* IP6_9_8 [2] */
5690                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5691                 /* IP6_7_6 [2] */
5692                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5693                 /* IP6_5_3 [3] */
5694                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5695                 FN_SCIFA2_RXD, FN_FMIN_E,
5696                 0, 0,
5697                 /* IP6_2_0 [3] */
5698                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5699                 FN_SCIF_CLK, 0, FN_BPFCLK_E,
5700                 0, 0, }
5701         },
5702         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5703                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5704                 /* IP7_31_30 [2] */
5705                 0, 0, 0, 0,
5706                 /* IP7_29_27 [3] */
5707                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5708                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5709                 0, 0,
5710                 /* IP7_26_24 [3] */
5711                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5712                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5713                 0, 0,
5714                 /* IP7_23_21 [3] */
5715                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5716                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5717                 0, 0,
5718                 /* IP7_20_19 [2] */
5719                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
5720                 /* IP7_18_17 [2] */
5721                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
5722                 /* IP7_16_15 [2] */
5723                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
5724                 /* IP7_14_13 [2] */
5725                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
5726                 /* IP7_12_11 [2] */
5727                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
5728                 /* IP7_10_9 [2] */
5729                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
5730                 /* IP7_8_6 [3] */
5731                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
5732                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
5733                 0, 0,
5734                 /* IP7_5_3 [3] */
5735                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
5736                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
5737                 0, 0,
5738                 /* IP7_2_0 [3] */
5739                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
5740                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
5741                 0, 0, }
5742         },
5743         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5744                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5745                 /* IP8_31 [1] */
5746                 0, 0,
5747                 /* IP8_30_28 [3] */
5748                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
5749                 0, 0, 0,
5750                 /* IP8_27_26 [2] */
5751                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
5752                 /* IP8_25_24 [2] */
5753                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
5754                 /* IP8_23_21 [3] */
5755                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
5756                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
5757                 0, 0,
5758                 /* IP8_20_18 [3] */
5759                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
5760                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
5761                 0, 0,
5762                 /* IP8_17_15 [3] */
5763                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
5764                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
5765                 0, 0,
5766                 /* IP8_14_12 [3] */
5767                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
5768                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
5769                 0, 0, 0,
5770                 /* IP8_11_9 [3] */
5771                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
5772                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
5773                 0, 0, 0,
5774                 /* IP8_8_6 [3] */
5775                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
5776                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
5777                 0, 0,
5778                 /* IP8_5_3 [3] */
5779                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
5780                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
5781                 0, 0,
5782                 /* IP8_2_0 [3] */
5783                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
5784                 0, 0, 0, }
5785         },
5786         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5787                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
5788                 /* IP9_31_29 [3] */
5789                 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
5790                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
5791                 /* IP9_28_27 [2] */
5792                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
5793                 /* IP9_26_25 [2] */
5794                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
5795                 /* IP9_24_23 [2] */
5796                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
5797                 /* IP9_22_21 [2] */
5798                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
5799                 /* IP9_20_19 [2] */
5800                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
5801                 /* IP9_18_17 [2] */
5802                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
5803                 /* IP9_16 [1] */
5804                 FN_DU1_DISP, FN_QPOLA,
5805                 /* IP9_15_13 [3] */
5806                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
5807                 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
5808                 0, 0, 0,
5809                 /* IP9_12 [1] */
5810                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
5811                 /* IP9_11 [1] */
5812                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
5813                 /* IP9_10_8 [3] */
5814                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
5815                 FN_TX3_B, FN_SCL2_B, FN_PWM4,
5816                 0, 0,
5817                 /* IP9_7 [1] */
5818                 FN_DU1_DOTCLKOUT0, FN_QCLK,
5819                 /* IP9_6 [1] */
5820                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
5821                 /* IP9_5_3 [3] */
5822                 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
5823                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
5824                 0, 0, 0,
5825                 /* IP9_2_0 [3] */
5826                 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
5827                 0, 0, 0, }
5828         },
5829         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5830                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
5831                 /* IP10_31_29 [3] */
5832                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
5833                 0, 0, 0,
5834                 /* IP10_28_27 [2] */
5835                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
5836                 /* IP10_26_25 [2] */
5837                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
5838                 /* IP10_24_22 [3] */
5839                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
5840                 0, 0, 0,
5841                 /* IP10_21_29 [3] */
5842                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
5843                 FN_TS_SDATA0_C, FN_ATACS11_N,
5844                 0, 0, 0,
5845                 /* IP10_18_17 [2] */
5846                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
5847                 /* IP10_16_15 [2] */
5848                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
5849                 /* IP10_14_12 [3] */
5850                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
5851                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
5852                 /* IP10_11_9 [3] */
5853                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
5854                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
5855                 0, 0,
5856                 /* IP10_8_6 [3] */
5857                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
5858                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
5859                 /* IP10_5_3 [3] */
5860                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
5861                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
5862                 /* IP10_2_0 [3] */
5863                 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
5864                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
5865         },
5866         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5867                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
5868                              3, 3, 3, 3, 3) {
5869                 /* IP11_31_30 [2] */
5870                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
5871                 /* IP11_29_28 [2] */
5872                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
5873                 /* IP11_27 [1] */
5874                 FN_VI1_DATA7, FN_AVB_MDC,
5875                 /* IP11_26 [1] */
5876                 FN_VI1_DATA6, FN_AVB_MAGIC,
5877                 /* IP11_25 [1] */
5878                 FN_VI1_DATA5, FN_AVB_RX_DV,
5879                 /* IP11_24 [1] */
5880                 FN_VI1_DATA4, FN_AVB_MDIO,
5881                 /* IP11_23 [1] */
5882                 FN_VI1_DATA3, FN_AVB_RX_ER,
5883                 /* IP11_22 [1] */
5884                 FN_VI1_DATA2, FN_AVB_RXD7,
5885                 /* IP11_21 [1] */
5886                 FN_VI1_DATA1, FN_AVB_RXD6,
5887                 /* IP11_20 [1] */
5888                 FN_VI1_DATA0, FN_AVB_RXD5,
5889                 /* IP11_19 [1] */
5890                 FN_VI1_CLK, FN_AVB_RXD4,
5891                 /* IP11_18_17 [2] */
5892                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
5893                 /* IP11_16_15 [2] */
5894                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
5895                 /* IP11_14_12 [3] */
5896                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
5897                 FN_RX4_B, FN_SCIFA4_RXD_B,
5898                 0, 0, 0,
5899                 /* IP11_11_9 [3] */
5900                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
5901                 FN_TX4_B, FN_SCIFA4_TXD_B,
5902                 0, 0, 0,
5903                 /* IP11_8_6 [3] */
5904                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
5905                 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
5906                 /* IP11_5_3 [3] */
5907                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
5908                 0, 0, 0,
5909                 /* IP11_2_0 [3] */
5910                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
5911                 0, 0, 0, }
5912         },
5913         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5914                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
5915                 /* IP12_31_30 [2] */
5916                 0, 0, 0, 0,
5917                 /* IP12_29_27 [3] */
5918                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
5919                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
5920                 0, 0, 0,
5921                 /* IP12_26_24 [3] */
5922                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
5923                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
5924                 0, 0, 0,
5925                 /* IP12_23_22 [2] */
5926                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
5927                 /* IP12_21_20 [2] */
5928                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
5929                 /* IP12_19_18 [2] */
5930                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
5931                 /* IP12_17_16 [2] */
5932                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
5933                 /* IP12_15_13 [3] */
5934                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
5935                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
5936                 0, 0, 0,
5937                 /* IP12_12_10 [3] */
5938                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
5939                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
5940                 0, 0, 0,
5941                 /* IP12_9_7 [3] */
5942                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
5943                 FN_SDA2_D, FN_MSIOF1_SCK_E,
5944                 0, 0, 0,
5945                 /* IP12_6_4 [3] */
5946                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
5947                 FN_SCL2_D, FN_MSIOF1_RXD_E,
5948                 0, 0, 0,
5949                 /* IP12_3_2 [2] */
5950                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
5951                 /* IP12_1_0 [2] */
5952                 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
5953         },
5954         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5955                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
5956                              3, 2, 2, 3) {
5957                 /* IP13_31 [1] */
5958                 0, 0,
5959                 /* IP13_30_28 [3] */
5960                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
5961                 0, 0, 0, 0,
5962                 /* IP13_27 [1] */
5963                 FN_SD1_DATA3, FN_IERX_B,
5964                 /* IP13_26 [1] */
5965                 FN_SD1_DATA2, FN_IECLK_B,
5966                 /* IP13_25 [1] */
5967                 FN_SD1_DATA1, FN_IETX_B,
5968                 /* IP13_24_23 [2] */
5969                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
5970                 /* IP13_22 [1] */
5971                 FN_SD1_CMD, FN_REMOCON_B,
5972                 /* IP13_21_19 [3] */
5973                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
5974                 FN_SCIFA5_RXD_B, FN_RX3_C,
5975                 0, 0,
5976                 /* IP13_18_16 [3] */
5977                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
5978                 FN_SCIFA5_TXD_B, FN_TX3_C,
5979                 0, 0,
5980                 /* IP13_15 [1] */
5981                 FN_SD0_DATA3, FN_SSL_B,
5982                 /* IP13_14 [1] */
5983                 FN_SD0_DATA2, FN_IO3_B,
5984                 /* IP13_13 [1] */
5985                 FN_SD0_DATA1, FN_IO2_B,
5986                 /* IP13_12 [1] */
5987                 FN_SD0_DATA0, FN_MISO_IO1_B,
5988                 /* IP13_11 [1] */
5989                 FN_SD0_CMD, FN_MOSI_IO0_B,
5990                 /* IP13_10 [1] */
5991                 FN_SD0_CLK, FN_SPCLK_B,
5992                 /* IP13_9_7 [3] */
5993                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
5994                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
5995                 0, 0, 0,
5996                 /* IP13_6_5 [2] */
5997                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
5998                 /* IP13_4_3 [2] */
5999                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6000                 /* IP13_2_0 [3] */
6001                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6002                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6003                 0, 0, 0, }
6004         },
6005         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6006                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6007                 /* IP14_31_29 [3] */
6008                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6009                 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
6010                 /* IP14_28_26 [3] */
6011                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6012                 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
6013                 /* IP14_25_23 [3] */
6014                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6015                 0, 0, 0,
6016                 /* IP14_22_20 [3] */
6017                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6018                 0, 0, 0,
6019                 /* IP14_19_17 [3] */
6020                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6021                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6022                 0, 0,
6023                 /* IP14_16_14 [3] */
6024                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6025                 FN_VI1_CLK_C, FN_VI1_G0_B,
6026                 0, 0,
6027                 /* IP14_13_11 [3] */
6028                 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6029                 0, 0, 0,
6030                 /* IP14_10_8 [3] */
6031                 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6032                 0, 0, 0,
6033                 /* IP14_7 [1] */
6034                 FN_SD2_DATA3, FN_MMC_D3,
6035                 /* IP14_6 [1] */
6036                 FN_SD2_DATA2, FN_MMC_D2,
6037                 /* IP14_5 [1] */
6038                 FN_SD2_DATA1, FN_MMC_D1,
6039                 /* IP14_4 [1] */
6040                 FN_SD2_DATA0, FN_MMC_D0,
6041                 /* IP14_3 [1] */
6042                 FN_SD2_CMD, FN_MMC_CMD,
6043                 /* IP14_2 [1] */
6044                 FN_SD2_CLK, FN_MMC_CLK,
6045                 /* IP14_1_0 [2] */
6046                 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
6047         },
6048         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6049                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6050                 /* IP15_31_30 [2] */
6051                 0, 0, 0, 0,
6052                 /* IP15_29_27 [3] */
6053                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6054                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6055                 0, 0,
6056                 /* IP15_26_24 [3] */
6057                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6058                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6059                 0, 0,
6060                 /* IP15_23_21 [3] */
6061                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6062                 FN_TCLK2, FN_VI1_DATA3_C, 0,
6063                 /* IP15_20_18 [3] */
6064                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6065                 0, 0, 0,
6066                 /* IP15_17_15 [3] */
6067                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6068                 FN_TCLK1, FN_VI1_DATA1_C,
6069                 0, 0,
6070                 /* IP15_14_12 [3] */
6071                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6072                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6073                 0, 0,
6074                 /* IP15_11_9 [3] */
6075                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6076                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6077                 0, 0,
6078                 /* IP15_8_6 [3] */
6079                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6080                 FN_PWM5_B, FN_SCIFA3_TXD_C,
6081                 0, 0, 0,
6082                 /* IP15_5_4 [2] */
6083                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6084                 /* IP15_3_2 [2] */
6085                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6086                 /* IP15_1_0 [2] */
6087                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6088         },
6089         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6090                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6091                 /* IP16_31_28 [4] */
6092                 0, 0, 0, 0, 0, 0, 0, 0,
6093                 0, 0, 0, 0, 0, 0, 0, 0,
6094                 /* IP16_27_24 [4] */
6095                 0, 0, 0, 0, 0, 0, 0, 0,
6096                 0, 0, 0, 0, 0, 0, 0, 0,
6097                 /* IP16_23_20 [4] */
6098                 0, 0, 0, 0, 0, 0, 0, 0,
6099                 0, 0, 0, 0, 0, 0, 0, 0,
6100                 /* IP16_19_16 [4] */
6101                 0, 0, 0, 0, 0, 0, 0, 0,
6102                 0, 0, 0, 0, 0, 0, 0, 0,
6103                 /* IP16_15_12 [4] */
6104                 0, 0, 0, 0, 0, 0, 0, 0,
6105                 0, 0, 0, 0, 0, 0, 0, 0,
6106                 /* IP16_11_10 [2] */
6107                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6108                 /* IP16_9_8 [2] */
6109                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6110                 /* IP16_7_6 [2] */
6111                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6112                 /* IP16_5_3 [3] */
6113                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6114                 FN_GLO_SS_C, FN_VI1_DATA7_C,
6115                 0, 0, 0,
6116                 /* IP16_2_0 [3] */
6117                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6118                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6119                 0, 0, 0, }
6120         },
6121         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6122                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6123                              3, 2, 2, 2, 1, 2, 2, 2) {
6124                 /* RESERVED [1] */
6125                 0, 0,
6126                 /* SEL_SCIF1 [2] */
6127                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6128                 /* SEL_SCIFB [2] */
6129                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6130                 /* SEL_SCIFB2 [2] */
6131                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6132                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6133                 /* SEL_SCIFB1 [3] */
6134                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6135                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6136                 0, 0, 0, 0,
6137                 /* SEL_SCIFA1 [2] */
6138                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6139                 /* SEL_SSI9 [1] */
6140                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6141                 /* SEL_SCFA [1] */
6142                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6143                 /* SEL_QSP [1] */
6144                 FN_SEL_QSP_0, FN_SEL_QSP_1,
6145                 /* SEL_SSI7 [1] */
6146                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6147                 /* SEL_HSCIF1 [3] */
6148                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6149                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6150                 0, 0, 0,
6151                 /* RESERVED [2] */
6152                 0, 0, 0, 0,
6153                 /* SEL_VI1 [2] */
6154                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6155                 /* RESERVED [2] */
6156                 0, 0, 0, 0,
6157                 /* SEL_TMU [1] */
6158                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6159                 /* SEL_LBS [2] */
6160                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6161                 /* SEL_TSIF0 [2] */
6162                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6163                 /* SEL_SOF0 [2] */
6164                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6165         },
6166         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6167                              3, 1, 1, 3, 2, 1, 1, 2, 2,
6168                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6169                 /* SEL_SCIF0 [3] */
6170                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6171                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6172                 0, 0, 0,
6173                 /* RESERVED [1] */
6174                 0, 0,
6175                 /* SEL_SCIF [1] */
6176                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6177                 /* SEL_CAN0 [3] */
6178                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6179                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6180                 0, 0,
6181                 /* SEL_CAN1 [2] */
6182                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6183                 /* RESERVED [1] */
6184                 0, 0,
6185                 /* SEL_SCIFA2 [1] */
6186                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6187                 /* SEL_SCIF4 [2] */
6188                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6189                 /* RESERVED [2] */
6190                 0, 0, 0, 0,
6191                 /* SEL_ADG [1] */
6192                 FN_SEL_ADG_0, FN_SEL_ADG_1,
6193                 /* SEL_FM [3] */
6194                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6195                 FN_SEL_FM_3, FN_SEL_FM_4,
6196                 0, 0, 0,
6197                 /* SEL_SCIFA5 [2] */
6198                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6199                 /* RESERVED [1] */
6200                 0, 0,
6201                 /* SEL_GPS [2] */
6202                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6203                 /* SEL_SCIFA4 [2] */
6204                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6205                 /* SEL_SCIFA3 [2] */
6206                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6207                 /* SEL_SIM [1] */
6208                 FN_SEL_SIM_0, FN_SEL_SIM_1,
6209                 /* RESERVED [1] */
6210                 0, 0,
6211                 /* SEL_SSI8 [1] */
6212                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6213         },
6214         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6215                              2, 2, 2, 2, 2, 2, 2, 2,
6216                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
6217                 /* SEL_HSCIF2 [2] */
6218                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6219                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6220                 /* SEL_CANCLK [2] */
6221                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6222                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6223                 /* SEL_IIC8 [2] */
6224                 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
6225                 /* SEL_IIC7 [2] */
6226                 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
6227                 /* SEL_IIC4 [2] */
6228                 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
6229                 /* SEL_IIC3 [2] */
6230                 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
6231                 /* SEL_SCIF3 [2] */
6232                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6233                 /* SEL_IEB [2] */
6234                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6235                 /* SEL_MMC [1] */
6236                 FN_SEL_MMC_0, FN_SEL_MMC_1,
6237                 /* SEL_SCIF5 [1] */
6238                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6239                 /* RESERVED [2] */
6240                 0, 0, 0, 0,
6241                 /* SEL_IIC2 [2] */
6242                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
6243                 /* SEL_IIC1 [3] */
6244                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
6245                 FN_SEL_IIC1_4,
6246                 0, 0, 0,
6247                 /* SEL_IIC0 [2] */
6248                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6249                 /* RESERVED [2] */
6250                 0, 0, 0, 0,
6251                 /* RESERVED [2] */
6252                 0, 0, 0, 0,
6253                 /* RESERVED [1] */
6254                 0, 0, }
6255         },
6256         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6257                              3, 2, 2, 1, 1, 1, 1, 3, 2,
6258                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
6259                 /* SEL_SOF1 [3] */
6260                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6261                 FN_SEL_SOF1_4,
6262                 0, 0, 0,
6263                 /* SEL_HSCIF0 [2] */
6264                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6265                 /* SEL_DIS [2] */
6266                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6267                 /* RESERVED [1] */
6268                 0, 0,
6269                 /* SEL_RAD [1] */
6270                 FN_SEL_RAD_0, FN_SEL_RAD_1,
6271                 /* SEL_RCN [1] */
6272                 FN_SEL_RCN_0, FN_SEL_RCN_1,
6273                 /* SEL_RSP [1] */
6274                 FN_SEL_RSP_0, FN_SEL_RSP_1,
6275                 /* SEL_SCIF2 [3] */
6276                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6277                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6278                 0, 0, 0,
6279                 /* RESERVED [2] */
6280                 0, 0, 0, 0,
6281                 /* RESERVED [2] */
6282                 0, 0, 0, 0,
6283                 /* SEL_SOF2 [3] */
6284                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6285                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6286                 0, 0, 0,
6287                 /* RESERVED [1] */
6288                 0, 0,
6289                 /* SEL_SSI1 [1] */
6290                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6291                 /* SEL_SSI0 [1] */
6292                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6293                 /* SEL_SSP [2] */
6294                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6295                 /* RESERVED [2] */
6296                 0, 0, 0, 0,
6297                 /* RESERVED [2] */
6298                 0, 0, 0, 0,
6299                 /* RESERVED [2] */
6300                 0, 0, 0, 0, }
6301         },
6302         { },
6303 };
6304
6305 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6306 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6307         .name = "r8a77910_pfc",
6308         .unlock_reg = 0xe6060000, /* PMMR */
6309
6310         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6311
6312         .pins = pinmux_pins,
6313         .nr_pins = ARRAY_SIZE(pinmux_pins),
6314         .groups = pinmux_groups,
6315         .nr_groups = ARRAY_SIZE(pinmux_groups),
6316         .functions = pinmux_functions,
6317         .nr_functions = ARRAY_SIZE(pinmux_functions),
6318
6319         .cfg_regs = pinmux_config_regs,
6320
6321         .pinmux_data = pinmux_data,
6322         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6323 };
6324 #endif
6325
6326 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6327 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6328         .name = "r8a77930_pfc",
6329         .unlock_reg = 0xe6060000, /* PMMR */
6330
6331         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6332
6333         .pins = pinmux_pins,
6334         .nr_pins = ARRAY_SIZE(pinmux_pins),
6335         .groups = pinmux_groups,
6336         .nr_groups = ARRAY_SIZE(pinmux_groups),
6337         .functions = pinmux_functions,
6338         .nr_functions = ARRAY_SIZE(pinmux_functions),
6339
6340         .cfg_regs = pinmux_config_regs,
6341
6342         .pinmux_data = pinmux_data,
6343         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6344 };
6345 #endif