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sfc: Use consistent types for interrupt coalescing parameters
[linux/fpc-iii.git] / drivers / net / ethernet / sfc / efx.c
blob097ed8b4a79ad46879128a90e56e2cdae245d940
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2011 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/delay.h>
16 #include <linux/notifier.h>
17 #include <linux/ip.h>
18 #include <linux/tcp.h>
19 #include <linux/in.h>
20 #include <linux/crc32.h>
21 #include <linux/ethtool.h>
22 #include <linux/topology.h>
23 #include <linux/gfp.h>
24 #include <linux/cpu_rmap.h>
25 #include "net_driver.h"
26 #include "efx.h"
27 #include "nic.h"
28
29 #include "mcdi.h"
30 #include "workarounds.h"
31
32 /**************************************************************************
33 *
34 * Type name strings
35 *
36 **************************************************************************
37 */
38
39 /* Loopback mode names (see LOOPBACK_MODE()) */
40 const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
41 const char *efx_loopback_mode_names[] = {
42 [LOOPBACK_NONE] = "NONE",
43 [LOOPBACK_DATA] = "DATAPATH",
44 [LOOPBACK_GMAC] = "GMAC",
45 [LOOPBACK_XGMII] = "XGMII",
46 [LOOPBACK_XGXS] = "XGXS",
47 [LOOPBACK_XAUI] = "XAUI",
48 [LOOPBACK_GMII] = "GMII",
49 [LOOPBACK_SGMII] = "SGMII",
50 [LOOPBACK_XGBR] = "XGBR",
51 [LOOPBACK_XFI] = "XFI",
52 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
53 [LOOPBACK_GMII_FAR] = "GMII_FAR",
54 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
55 [LOOPBACK_XFI_FAR] = "XFI_FAR",
56 [LOOPBACK_GPHY] = "GPHY",
57 [LOOPBACK_PHYXS] = "PHYXS",
58 [LOOPBACK_PCS] = "PCS",
59 [LOOPBACK_PMAPMD] = "PMA/PMD",
60 [LOOPBACK_XPORT] = "XPORT",
61 [LOOPBACK_XGMII_WS] = "XGMII_WS",
62 [LOOPBACK_XAUI_WS] = "XAUI_WS",
63 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
64 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
65 [LOOPBACK_GMII_WS] = "GMII_WS",
66 [LOOPBACK_XFI_WS] = "XFI_WS",
67 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
68 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
69 };
70
71 const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
72 const char *efx_reset_type_names[] = {
73 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
74 [RESET_TYPE_ALL] = "ALL",
75 [RESET_TYPE_WORLD] = "WORLD",
76 [RESET_TYPE_DISABLE] = "DISABLE",
77 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
78 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
79 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
80 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH",
81 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH",
82 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
83 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
84 };
85
86 #define EFX_MAX_MTU (9 * 1024)
87
88 /* Reset workqueue. If any NIC has a hardware failure then a reset will be
89 * queued onto this work queue. This is not a per-nic work queue, because
90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
91 */
92 static struct workqueue_struct *reset_workqueue;
93
94 /**************************************************************************
95 *
96 * Configurable values
97 *
98 *************************************************************************/
99
100 /*
101 * Use separate channels for TX and RX events
102 *
103 * Set this to 1 to use separate channels for TX and RX. It allows us
104 * to control interrupt affinity separately for TX and RX.
105 *
106 * This is only used in MSI-X interrupt mode
107 */
108 static unsigned int separate_tx_channels;
109 module_param(separate_tx_channels, uint, 0444);
110 MODULE_PARM_DESC(separate_tx_channels,
111 "Use separate channels for TX and RX");
112
113 /* This is the weight assigned to each of the (per-channel) virtual
114 * NAPI devices.
115 */
116 static int napi_weight = 64;
117
118 /* This is the time (in jiffies) between invocations of the hardware
119 * monitor. On Falcon-based NICs, this will:
120 * - Check the on-board hardware monitor;
121 * - Poll the link state and reconfigure the hardware as necessary.
122 */
123 static unsigned int efx_monitor_interval = 1 * HZ;
124
125 /* This controls whether or not the driver will initialise devices
126 * with invalid MAC addresses stored in the EEPROM or flash. If true,
127 * such devices will be initialised with a random locally-generated
128 * MAC address. This allows for loading the sfc_mtd driver to
129 * reprogram the flash, even if the flash contents (including the MAC
130 * address) have previously been erased.
131 */
132 static unsigned int allow_bad_hwaddr;
133
134 /* Initial interrupt moderation settings. They can be modified after
135 * module load with ethtool.
136 *
137 * The default for RX should strike a balance between increasing the
138 * round-trip latency and reducing overhead.
139 */
140 static unsigned int rx_irq_mod_usec = 60;
141
142 /* Initial interrupt moderation settings. They can be modified after
143 * module load with ethtool.
144 *
145 * This default is chosen to ensure that a 10G link does not go idle
146 * while a TX queue is stopped after it has become full. A queue is
147 * restarted when it drops below half full. The time this takes (assuming
148 * worst case 3 descriptors per packet and 1024 descriptors) is
149 * 512 / 3 * 1.2 = 205 usec.
150 */
151 static unsigned int tx_irq_mod_usec = 150;
152
153 /* This is the first interrupt mode to try out of:
154 * 0 => MSI-X
155 * 1 => MSI
156 * 2 => legacy
157 */
158 static unsigned int interrupt_mode;
159
160 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
161 * i.e. the number of CPUs among which we may distribute simultaneous
162 * interrupt handling.
163 *
164 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
165 * The default (0) means to assign an interrupt to each package (level II cache)
166 */
167 static unsigned int rss_cpus;
168 module_param(rss_cpus, uint, 0444);
169 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
170
171 static int phy_flash_cfg;
172 module_param(phy_flash_cfg, int, 0644);
173 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
174
175 static unsigned irq_adapt_low_thresh = 10000;
176 module_param(irq_adapt_low_thresh, uint, 0644);
177 MODULE_PARM_DESC(irq_adapt_low_thresh,
178 "Threshold score for reducing IRQ moderation");
179
180 static unsigned irq_adapt_high_thresh = 20000;
181 module_param(irq_adapt_high_thresh, uint, 0644);
182 MODULE_PARM_DESC(irq_adapt_high_thresh,
183 "Threshold score for increasing IRQ moderation");
184
185 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
186 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
187 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
188 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
189 module_param(debug, uint, 0);
190 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
191
192 /**************************************************************************
193 *
194 * Utility functions and prototypes
195 *
196 *************************************************************************/
197
198 static void efx_remove_channels(struct efx_nic *efx);
199 static void efx_remove_port(struct efx_nic *efx);
200 static void efx_init_napi(struct efx_nic *efx);
201 static void efx_fini_napi(struct efx_nic *efx);
202 static void efx_fini_napi_channel(struct efx_channel *channel);
203 static void efx_fini_struct(struct efx_nic *efx);
204 static void efx_start_all(struct efx_nic *efx);
205 static void efx_stop_all(struct efx_nic *efx);
206
207 #define EFX_ASSERT_RESET_SERIALISED(efx) \
208 do { \
209 if ((efx->state == STATE_RUNNING) || \
210 (efx->state == STATE_DISABLED)) \
211 ASSERT_RTNL(); \
212 } while (0)
213
214 /**************************************************************************
215 *
216 * Event queue processing
217 *
218 *************************************************************************/
219
220 /* Process channel's event queue
221 *
222 * This function is responsible for processing the event queue of a
223 * single channel. The caller must guarantee that this function will
224 * never be concurrently called more than once on the same channel,
225 * though different channels may be being processed concurrently.
226 */
227 static int efx_process_channel(struct efx_channel *channel, int budget)
228 {
229 struct efx_nic *efx = channel->efx;
230 int spent;
231
232 if (unlikely(efx->reset_pending || !channel->enabled))
233 return 0;
234
235 spent = efx_nic_process_eventq(channel, budget);
236 if (spent == 0)
237 return 0;
238
239 /* Deliver last RX packet. */
240 if (channel->rx_pkt) {
241 __efx_rx_packet(channel, channel->rx_pkt,
242 channel->rx_pkt_csummed);
243 channel->rx_pkt = NULL;
244 }
245
246 efx_rx_strategy(channel);
247
248 efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel));
249
250 return spent;
251 }
252
253 /* Mark channel as finished processing
254 *
255 * Note that since we will not receive further interrupts for this
256 * channel before we finish processing and call the eventq_read_ack()
257 * method, there is no need to use the interrupt hold-off timers.
258 */
259 static inline void efx_channel_processed(struct efx_channel *channel)
260 {
261 /* The interrupt handler for this channel may set work_pending
262 * as soon as we acknowledge the events we've seen. Make sure
263 * it's cleared before then. */
264 channel->work_pending = false;
265 smp_wmb();
266
267 efx_nic_eventq_read_ack(channel);
268 }
269
270 /* NAPI poll handler
271 *
272 * NAPI guarantees serialisation of polls of the same device, which
273 * provides the guarantee required by efx_process_channel().
274 */
275 static int efx_poll(struct napi_struct *napi, int budget)
276 {
277 struct efx_channel *channel =
278 container_of(napi, struct efx_channel, napi_str);
279 struct efx_nic *efx = channel->efx;
280 int spent;
281
282 netif_vdbg(efx, intr, efx->net_dev,
283 "channel %d NAPI poll executing on CPU %d\n",
284 channel->channel, raw_smp_processor_id());
285
286 spent = efx_process_channel(channel, budget);
287
288 if (spent < budget) {
289 if (channel->channel < efx->n_rx_channels &&
290 efx->irq_rx_adaptive &&
291 unlikely(++channel->irq_count == 1000)) {
292 if (unlikely(channel->irq_mod_score <
293 irq_adapt_low_thresh)) {
294 if (channel->irq_moderation > 1) {
295 channel->irq_moderation -= 1;
296 efx->type->push_irq_moderation(channel);
297 }
298 } else if (unlikely(channel->irq_mod_score >
299 irq_adapt_high_thresh)) {
300 if (channel->irq_moderation <
301 efx->irq_rx_moderation) {
302 channel->irq_moderation += 1;
303 efx->type->push_irq_moderation(channel);
304 }
305 }
306 channel->irq_count = 0;
307 channel->irq_mod_score = 0;
308 }
309
310 efx_filter_rfs_expire(channel);
311
312 /* There is no race here; although napi_disable() will
313 * only wait for napi_complete(), this isn't a problem
314 * since efx_channel_processed() will have no effect if
315 * interrupts have already been disabled.
316 */
317 napi_complete(napi);
318 efx_channel_processed(channel);
319 }
320
321 return spent;
322 }
323
324 /* Process the eventq of the specified channel immediately on this CPU
325 *
326 * Disable hardware generated interrupts, wait for any existing
327 * processing to finish, then directly poll (and ack ) the eventq.
328 * Finally reenable NAPI and interrupts.
329 *
330 * This is for use only during a loopback self-test. It must not
331 * deliver any packets up the stack as this can result in deadlock.
332 */
333 void efx_process_channel_now(struct efx_channel *channel)
334 {
335 struct efx_nic *efx = channel->efx;
336
337 BUG_ON(channel->channel >= efx->n_channels);
338 BUG_ON(!channel->enabled);
339 BUG_ON(!efx->loopback_selftest);
340
341 /* Disable interrupts and wait for ISRs to complete */
342 efx_nic_disable_interrupts(efx);
343 if (efx->legacy_irq) {
344 synchronize_irq(efx->legacy_irq);
345 efx->legacy_irq_enabled = false;
346 }
347 if (channel->irq)
348 synchronize_irq(channel->irq);
349
350 /* Wait for any NAPI processing to complete */
351 napi_disable(&channel->napi_str);
352
353 /* Poll the channel */
354 efx_process_channel(channel, channel->eventq_mask + 1);
355
356 /* Ack the eventq. This may cause an interrupt to be generated
357 * when they are reenabled */
358 efx_channel_processed(channel);
359
360 napi_enable(&channel->napi_str);
361 if (efx->legacy_irq)
362 efx->legacy_irq_enabled = true;
363 efx_nic_enable_interrupts(efx);
364 }
365
366 /* Create event queue
367 * Event queue memory allocations are done only once. If the channel
368 * is reset, the memory buffer will be reused; this guards against
369 * errors during channel reset and also simplifies interrupt handling.
370 */
371 static int efx_probe_eventq(struct efx_channel *channel)
372 {
373 struct efx_nic *efx = channel->efx;
374 unsigned long entries;
375
376 netif_dbg(channel->efx, probe, channel->efx->net_dev,
377 "chan %d create event queue\n", channel->channel);
378
379 /* Build an event queue with room for one event per tx and rx buffer,
380 * plus some extra for link state events and MCDI completions. */
381 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
382 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
383 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
384
385 return efx_nic_probe_eventq(channel);
386 }
387
388 /* Prepare channel's event queue */
389 static void efx_init_eventq(struct efx_channel *channel)
390 {
391 netif_dbg(channel->efx, drv, channel->efx->net_dev,
392 "chan %d init event queue\n", channel->channel);
393
394 channel->eventq_read_ptr = 0;
395
396 efx_nic_init_eventq(channel);
397 }
398
399 static void efx_fini_eventq(struct efx_channel *channel)
400 {
401 netif_dbg(channel->efx, drv, channel->efx->net_dev,
402 "chan %d fini event queue\n", channel->channel);
403
404 efx_nic_fini_eventq(channel);
405 }
406
407 static void efx_remove_eventq(struct efx_channel *channel)
408 {
409 netif_dbg(channel->efx, drv, channel->efx->net_dev,
410 "chan %d remove event queue\n", channel->channel);
411
412 efx_nic_remove_eventq(channel);
413 }
414
415 /**************************************************************************
416 *
417 * Channel handling
418 *
419 *************************************************************************/
420
421 /* Allocate and initialise a channel structure, optionally copying
422 * parameters (but not resources) from an old channel structure. */
423 static struct efx_channel *
424 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
425 {
426 struct efx_channel *channel;
427 struct efx_rx_queue *rx_queue;
428 struct efx_tx_queue *tx_queue;
429 int j;
430
431 if (old_channel) {
432 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
433 if (!channel)
434 return NULL;
435
436 *channel = *old_channel;
437
438 channel->napi_dev = NULL;
439 memset(&channel->eventq, 0, sizeof(channel->eventq));
440
441 rx_queue = &channel->rx_queue;
442 rx_queue->buffer = NULL;
443 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
444
445 for (j = 0; j < EFX_TXQ_TYPES; j++) {
446 tx_queue = &channel->tx_queue[j];
447 if (tx_queue->channel)
448 tx_queue->channel = channel;
449 tx_queue->buffer = NULL;
450 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
451 }
452 } else {
453 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
454 if (!channel)
455 return NULL;
456
457 channel->efx = efx;
458 channel->channel = i;
459
460 for (j = 0; j < EFX_TXQ_TYPES; j++) {
461 tx_queue = &channel->tx_queue[j];
462 tx_queue->efx = efx;
463 tx_queue->queue = i * EFX_TXQ_TYPES + j;
464 tx_queue->channel = channel;
465 }
466 }
467
468 rx_queue = &channel->rx_queue;
469 rx_queue->efx = efx;
470 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
471 (unsigned long)rx_queue);
472
473 return channel;
474 }
475
476 static int efx_probe_channel(struct efx_channel *channel)
477 {
478 struct efx_tx_queue *tx_queue;
479 struct efx_rx_queue *rx_queue;
480 int rc;
481
482 netif_dbg(channel->efx, probe, channel->efx->net_dev,
483 "creating channel %d\n", channel->channel);
484
485 rc = efx_probe_eventq(channel);
486 if (rc)
487 goto fail1;
488
489 efx_for_each_channel_tx_queue(tx_queue, channel) {
490 rc = efx_probe_tx_queue(tx_queue);
491 if (rc)
492 goto fail2;
493 }
494
495 efx_for_each_channel_rx_queue(rx_queue, channel) {
496 rc = efx_probe_rx_queue(rx_queue);
497 if (rc)
498 goto fail3;
499 }
500
501 channel->n_rx_frm_trunc = 0;
502
503 return 0;
504
505 fail3:
506 efx_for_each_channel_rx_queue(rx_queue, channel)
507 efx_remove_rx_queue(rx_queue);
508 fail2:
509 efx_for_each_channel_tx_queue(tx_queue, channel)
510 efx_remove_tx_queue(tx_queue);
511 fail1:
512 return rc;
513 }
514
515
516 static void efx_set_channel_names(struct efx_nic *efx)
517 {
518 struct efx_channel *channel;
519 const char *type = "";
520 int number;
521
522 efx_for_each_channel(channel, efx) {
523 number = channel->channel;
524 if (efx->n_channels > efx->n_rx_channels) {
525 if (channel->channel < efx->n_rx_channels) {
526 type = "-rx";
527 } else {
528 type = "-tx";
529 number -= efx->n_rx_channels;
530 }
531 }
532 snprintf(efx->channel_name[channel->channel],
533 sizeof(efx->channel_name[0]),
534 "%s%s-%d", efx->name, type, number);
535 }
536 }
537
538 static int efx_probe_channels(struct efx_nic *efx)
539 {
540 struct efx_channel *channel;
541 int rc;
542
543 /* Restart special buffer allocation */
544 efx->next_buffer_table = 0;
545
546 efx_for_each_channel(channel, efx) {
547 rc = efx_probe_channel(channel);
548 if (rc) {
549 netif_err(efx, probe, efx->net_dev,
550 "failed to create channel %d\n",
551 channel->channel);
552 goto fail;
553 }
554 }
555 efx_set_channel_names(efx);
556
557 return 0;
558
559 fail:
560 efx_remove_channels(efx);
561 return rc;
562 }
563
564 /* Channels are shutdown and reinitialised whilst the NIC is running
565 * to propagate configuration changes (mtu, checksum offload), or
566 * to clear hardware error conditions
567 */
568 static void efx_init_channels(struct efx_nic *efx)
569 {
570 struct efx_tx_queue *tx_queue;
571 struct efx_rx_queue *rx_queue;
572 struct efx_channel *channel;
573
574 /* Calculate the rx buffer allocation parameters required to
575 * support the current MTU, including padding for header
576 * alignment and overruns.
577 */
578 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
579 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
580 efx->type->rx_buffer_hash_size +
581 efx->type->rx_buffer_padding);
582 efx->rx_buffer_order = get_order(efx->rx_buffer_len +
583 sizeof(struct efx_rx_page_state));
584
585 /* Initialise the channels */
586 efx_for_each_channel(channel, efx) {
587 netif_dbg(channel->efx, drv, channel->efx->net_dev,
588 "init chan %d\n", channel->channel);
589
590 efx_init_eventq(channel);
591
592 efx_for_each_channel_tx_queue(tx_queue, channel)
593 efx_init_tx_queue(tx_queue);
594
595 /* The rx buffer allocation strategy is MTU dependent */
596 efx_rx_strategy(channel);
597
598 efx_for_each_channel_rx_queue(rx_queue, channel)
599 efx_init_rx_queue(rx_queue);
600
601 WARN_ON(channel->rx_pkt != NULL);
602 efx_rx_strategy(channel);
603 }
604 }
605
606 /* This enables event queue processing and packet transmission.
607 *
608 * Note that this function is not allowed to fail, since that would
609 * introduce too much complexity into the suspend/resume path.
610 */
611 static void efx_start_channel(struct efx_channel *channel)
612 {
613 struct efx_rx_queue *rx_queue;
614
615 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
616 "starting chan %d\n", channel->channel);
617
618 /* The interrupt handler for this channel may set work_pending
619 * as soon as we enable it. Make sure it's cleared before
620 * then. Similarly, make sure it sees the enabled flag set. */
621 channel->work_pending = false;
622 channel->enabled = true;
623 smp_wmb();
624
625 /* Fill the queues before enabling NAPI */
626 efx_for_each_channel_rx_queue(rx_queue, channel)
627 efx_fast_push_rx_descriptors(rx_queue);
628
629 napi_enable(&channel->napi_str);
630 }
631
632 /* This disables event queue processing and packet transmission.
633 * This function does not guarantee that all queue processing
634 * (e.g. RX refill) is complete.
635 */
636 static void efx_stop_channel(struct efx_channel *channel)
637 {
638 if (!channel->enabled)
639 return;
640
641 netif_dbg(channel->efx, ifdown, channel->efx->net_dev,
642 "stop chan %d\n", channel->channel);
643
644 channel->enabled = false;
645 napi_disable(&channel->napi_str);
646 }
647
648 static void efx_fini_channels(struct efx_nic *efx)
649 {
650 struct efx_channel *channel;
651 struct efx_tx_queue *tx_queue;
652 struct efx_rx_queue *rx_queue;
653 int rc;
654
655 EFX_ASSERT_RESET_SERIALISED(efx);
656 BUG_ON(efx->port_enabled);
657
658 rc = efx_nic_flush_queues(efx);
659 if (rc && EFX_WORKAROUND_7803(efx)) {
660 /* Schedule a reset to recover from the flush failure. The
661 * descriptor caches reference memory we're about to free,
662 * but falcon_reconfigure_mac_wrapper() won't reconnect
663 * the MACs because of the pending reset. */
664 netif_err(efx, drv, efx->net_dev,
665 "Resetting to recover from flush failure\n");
666 efx_schedule_reset(efx, RESET_TYPE_ALL);
667 } else if (rc) {
668 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
669 } else {
670 netif_dbg(efx, drv, efx->net_dev,
671 "successfully flushed all queues\n");
672 }
673
674 efx_for_each_channel(channel, efx) {
675 netif_dbg(channel->efx, drv, channel->efx->net_dev,
676 "shut down chan %d\n", channel->channel);
677
678 efx_for_each_channel_rx_queue(rx_queue, channel)
679 efx_fini_rx_queue(rx_queue);
680 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
681 efx_fini_tx_queue(tx_queue);
682 efx_fini_eventq(channel);
683 }
684 }
685
686 static void efx_remove_channel(struct efx_channel *channel)
687 {
688 struct efx_tx_queue *tx_queue;
689 struct efx_rx_queue *rx_queue;
690
691 netif_dbg(channel->efx, drv, channel->efx->net_dev,
692 "destroy chan %d\n", channel->channel);
693
694 efx_for_each_channel_rx_queue(rx_queue, channel)
695 efx_remove_rx_queue(rx_queue);
696 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
697 efx_remove_tx_queue(tx_queue);
698 efx_remove_eventq(channel);
699 }
700
701 static void efx_remove_channels(struct efx_nic *efx)
702 {
703 struct efx_channel *channel;
704
705 efx_for_each_channel(channel, efx)
706 efx_remove_channel(channel);
707 }
708
709 int
710 efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
711 {
712 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
713 u32 old_rxq_entries, old_txq_entries;
714 unsigned i;
715 int rc;
716
717 efx_stop_all(efx);
718 efx_fini_channels(efx);
719
720 /* Clone channels */
721 memset(other_channel, 0, sizeof(other_channel));
722 for (i = 0; i < efx->n_channels; i++) {
723 channel = efx_alloc_channel(efx, i, efx->channel[i]);
724 if (!channel) {
725 rc = -ENOMEM;
726 goto out;
727 }
728 other_channel[i] = channel;
729 }
730
731 /* Swap entry counts and channel pointers */
732 old_rxq_entries = efx->rxq_entries;
733 old_txq_entries = efx->txq_entries;
734 efx->rxq_entries = rxq_entries;
735 efx->txq_entries = txq_entries;
736 for (i = 0; i < efx->n_channels; i++) {
737 channel = efx->channel[i];
738 efx->channel[i] = other_channel[i];
739 other_channel[i] = channel;
740 }
741
742 rc = efx_probe_channels(efx);
743 if (rc)
744 goto rollback;
745
746 efx_init_napi(efx);
747
748 /* Destroy old channels */
749 for (i = 0; i < efx->n_channels; i++) {
750 efx_fini_napi_channel(other_channel[i]);
751 efx_remove_channel(other_channel[i]);
752 }
753 out:
754 /* Free unused channel structures */
755 for (i = 0; i < efx->n_channels; i++)
756 kfree(other_channel[i]);
757
758 efx_init_channels(efx);
759 efx_start_all(efx);
760 return rc;
761
762 rollback:
763 /* Swap back */
764 efx->rxq_entries = old_rxq_entries;
765 efx->txq_entries = old_txq_entries;
766 for (i = 0; i < efx->n_channels; i++) {
767 channel = efx->channel[i];
768 efx->channel[i] = other_channel[i];
769 other_channel[i] = channel;
770 }
771 goto out;
772 }
773
774 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
775 {
776 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
777 }
778
779 /**************************************************************************
780 *
781 * Port handling
782 *
783 **************************************************************************/
784
785 /* This ensures that the kernel is kept informed (via
786 * netif_carrier_on/off) of the link status, and also maintains the
787 * link status's stop on the port's TX queue.
788 */
789 void efx_link_status_changed(struct efx_nic *efx)
790 {
791 struct efx_link_state *link_state = &efx->link_state;
792
793 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
794 * that no events are triggered between unregister_netdev() and the
795 * driver unloading. A more general condition is that NETDEV_CHANGE
796 * can only be generated between NETDEV_UP and NETDEV_DOWN */
797 if (!netif_running(efx->net_dev))
798 return;
799
800 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
801 efx->n_link_state_changes++;
802
803 if (link_state->up)
804 netif_carrier_on(efx->net_dev);
805 else
806 netif_carrier_off(efx->net_dev);
807 }
808
809 /* Status message for kernel log */
810 if (link_state->up) {
811 netif_info(efx, link, efx->net_dev,
812 "link up at %uMbps %s-duplex (MTU %d)%s\n",
813 link_state->speed, link_state->fd ? "full" : "half",
814 efx->net_dev->mtu,
815 (efx->promiscuous ? " [PROMISC]" : ""));
816 } else {
817 netif_info(efx, link, efx->net_dev, "link down\n");
818 }
819
820 }
821
822 void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
823 {
824 efx->link_advertising = advertising;
825 if (advertising) {
826 if (advertising & ADVERTISED_Pause)
827 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
828 else
829 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
830 if (advertising & ADVERTISED_Asym_Pause)
831 efx->wanted_fc ^= EFX_FC_TX;
832 }
833 }
834
835 void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
836 {
837 efx->wanted_fc = wanted_fc;
838 if (efx->link_advertising) {
839 if (wanted_fc & EFX_FC_RX)
840 efx->link_advertising |= (ADVERTISED_Pause |
841 ADVERTISED_Asym_Pause);
842 else
843 efx->link_advertising &= ~(ADVERTISED_Pause |
844 ADVERTISED_Asym_Pause);
845 if (wanted_fc & EFX_FC_TX)
846 efx->link_advertising ^= ADVERTISED_Asym_Pause;
847 }
848 }
849
850 static void efx_fini_port(struct efx_nic *efx);
851
852 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure
853 * the MAC appropriately. All other PHY configuration changes are pushed
854 * through phy_op->set_settings(), and pushed asynchronously to the MAC
855 * through efx_monitor().
856 *
857 * Callers must hold the mac_lock
858 */
859 int __efx_reconfigure_port(struct efx_nic *efx)
860 {
861 enum efx_phy_mode phy_mode;
862 int rc;
863
864 WARN_ON(!mutex_is_locked(&efx->mac_lock));
865
866 /* Serialise the promiscuous flag with efx_set_multicast_list. */
867 if (efx_dev_registered(efx)) {
868 netif_addr_lock_bh(efx->net_dev);
869 netif_addr_unlock_bh(efx->net_dev);
870 }
871
872 /* Disable PHY transmit in mac level loopbacks */
873 phy_mode = efx->phy_mode;
874 if (LOOPBACK_INTERNAL(efx))
875 efx->phy_mode |= PHY_MODE_TX_DISABLED;
876 else
877 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
878
879 rc = efx->type->reconfigure_port(efx);
880
881 if (rc)
882 efx->phy_mode = phy_mode;
883
884 return rc;
885 }
886
887 /* Reinitialise the MAC to pick up new PHY settings, even if the port is
888 * disabled. */
889 int efx_reconfigure_port(struct efx_nic *efx)
890 {
891 int rc;
892
893 EFX_ASSERT_RESET_SERIALISED(efx);
894
895 mutex_lock(&efx->mac_lock);
896 rc = __efx_reconfigure_port(efx);
897 mutex_unlock(&efx->mac_lock);
898
899 return rc;
900 }
901
902 /* Asynchronous work item for changing MAC promiscuity and multicast
903 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
904 * MAC directly. */
905 static void efx_mac_work(struct work_struct *data)
906 {
907 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
908
909 mutex_lock(&efx->mac_lock);
910 if (efx->port_enabled) {
911 efx->type->push_multicast_hash(efx);
912 efx->mac_op->reconfigure(efx);
913 }
914 mutex_unlock(&efx->mac_lock);
915 }
916
917 static int efx_probe_port(struct efx_nic *efx)
918 {
919 unsigned char *perm_addr;
920 int rc;
921
922 netif_dbg(efx, probe, efx->net_dev, "create port\n");
923
924 if (phy_flash_cfg)
925 efx->phy_mode = PHY_MODE_SPECIAL;
926
927 /* Connect up MAC/PHY operations table */
928 rc = efx->type->probe_port(efx);
929 if (rc)
930 return rc;
931
932 /* Sanity check MAC address */
933 perm_addr = efx->net_dev->perm_addr;
934 if (is_valid_ether_addr(perm_addr)) {
935 memcpy(efx->net_dev->dev_addr, perm_addr, ETH_ALEN);
936 } else {
937 netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n",
938 perm_addr);
939 if (!allow_bad_hwaddr) {
940 rc = -EINVAL;
941 goto err;
942 }
943 random_ether_addr(efx->net_dev->dev_addr);
944 netif_info(efx, probe, efx->net_dev,
945 "using locally-generated MAC %pM\n",
946 efx->net_dev->dev_addr);
947 }
948
949 return 0;
950
951 err:
952 efx->type->remove_port(efx);
953 return rc;
954 }
955
956 static int efx_init_port(struct efx_nic *efx)
957 {
958 int rc;
959
960 netif_dbg(efx, drv, efx->net_dev, "init port\n");
961
962 mutex_lock(&efx->mac_lock);
963
964 rc = efx->phy_op->init(efx);
965 if (rc)
966 goto fail1;
967
968 efx->port_initialized = true;
969
970 /* Reconfigure the MAC before creating dma queues (required for
971 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
972 efx->mac_op->reconfigure(efx);
973
974 /* Ensure the PHY advertises the correct flow control settings */
975 rc = efx->phy_op->reconfigure(efx);
976 if (rc)
977 goto fail2;
978
979 mutex_unlock(&efx->mac_lock);
980 return 0;
981
982 fail2:
983 efx->phy_op->fini(efx);
984 fail1:
985 mutex_unlock(&efx->mac_lock);
986 return rc;
987 }
988
989 static void efx_start_port(struct efx_nic *efx)
990 {
991 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
992 BUG_ON(efx->port_enabled);
993
994 mutex_lock(&efx->mac_lock);
995 efx->port_enabled = true;
996
997 /* efx_mac_work() might have been scheduled after efx_stop_port(),
998 * and then cancelled by efx_flush_all() */
999 efx->type->push_multicast_hash(efx);
1000 efx->mac_op->reconfigure(efx);
1001
1002 mutex_unlock(&efx->mac_lock);
1003 }
1004
1005 /* Prevent efx_mac_work() and efx_monitor() from working */
1006 static void efx_stop_port(struct efx_nic *efx)
1007 {
1008 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
1009
1010 mutex_lock(&efx->mac_lock);
1011 efx->port_enabled = false;
1012 mutex_unlock(&efx->mac_lock);
1013
1014 /* Serialise against efx_set_multicast_list() */
1015 if (efx_dev_registered(efx)) {
1016 netif_addr_lock_bh(efx->net_dev);
1017 netif_addr_unlock_bh(efx->net_dev);
1018 }
1019 }
1020
1021 static void efx_fini_port(struct efx_nic *efx)
1022 {
1023 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
1024
1025 if (!efx->port_initialized)
1026 return;
1027
1028 efx->phy_op->fini(efx);
1029 efx->port_initialized = false;
1030
1031 efx->link_state.up = false;
1032 efx_link_status_changed(efx);
1033 }
1034
1035 static void efx_remove_port(struct efx_nic *efx)
1036 {
1037 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
1038
1039 efx->type->remove_port(efx);
1040 }
1041
1042 /**************************************************************************
1043 *
1044 * NIC handling
1045 *
1046 **************************************************************************/
1047
1048 /* This configures the PCI device to enable I/O and DMA. */
1049 static int efx_init_io(struct efx_nic *efx)
1050 {
1051 struct pci_dev *pci_dev = efx->pci_dev;
1052 dma_addr_t dma_mask = efx->type->max_dma_mask;
1053 bool use_wc;
1054 int rc;
1055
1056 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
1057
1058 rc = pci_enable_device(pci_dev);
1059 if (rc) {
1060 netif_err(efx, probe, efx->net_dev,
1061 "failed to enable PCI device\n");
1062 goto fail1;
1063 }
1064
1065 pci_set_master(pci_dev);
1066
1067 /* Set the PCI DMA mask. Try all possibilities from our
1068 * genuine mask down to 32 bits, because some architectures
1069 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1070 * masks event though they reject 46 bit masks.
1071 */
1072 while (dma_mask > 0x7fffffffUL) {
1073 if (pci_dma_supported(pci_dev, dma_mask) &&
1074 ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0))
1075 break;
1076 dma_mask >>= 1;
1077 }
1078 if (rc) {
1079 netif_err(efx, probe, efx->net_dev,
1080 "could not find a suitable DMA mask\n");
1081 goto fail2;
1082 }
1083 netif_dbg(efx, probe, efx->net_dev,
1084 "using DMA mask %llx\n", (unsigned long long) dma_mask);
1085 rc = pci_set_consistent_dma_mask(pci_dev, dma_mask);
1086 if (rc) {
1087 /* pci_set_consistent_dma_mask() is not *allowed* to
1088 * fail with a mask that pci_set_dma_mask() accepted,
1089 * but just in case...
1090 */
1091 netif_err(efx, probe, efx->net_dev,
1092 "failed to set consistent DMA mask\n");
1093 goto fail2;
1094 }
1095
1096 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1097 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
1098 if (rc) {
1099 netif_err(efx, probe, efx->net_dev,
1100 "request for memory BAR failed\n");
1101 rc = -EIO;
1102 goto fail3;
1103 }
1104
1105 /* bug22643: If SR-IOV is enabled then tx push over a write combined
1106 * mapping is unsafe. We need to disable write combining in this case.
1107 * MSI is unsupported when SR-IOV is enabled, and the firmware will
1108 * have removed the MSI capability. So write combining is safe if
1109 * there is an MSI capability.
1110 */
1111 use_wc = (!EFX_WORKAROUND_22643(efx) ||
1112 pci_find_capability(pci_dev, PCI_CAP_ID_MSI));
1113 if (use_wc)
1114 efx->membase = ioremap_wc(efx->membase_phys,
1115 efx->type->mem_map_size);
1116 else
1117 efx->membase = ioremap_nocache(efx->membase_phys,
1118 efx->type->mem_map_size);
1119 if (!efx->membase) {
1120 netif_err(efx, probe, efx->net_dev,
1121 "could not map memory BAR at %llx+%x\n",
1122 (unsigned long long)efx->membase_phys,
1123 efx->type->mem_map_size);
1124 rc = -ENOMEM;
1125 goto fail4;
1126 }
1127 netif_dbg(efx, probe, efx->net_dev,
1128 "memory BAR at %llx+%x (virtual %p)\n",
1129 (unsigned long long)efx->membase_phys,
1130 efx->type->mem_map_size, efx->membase);
1131
1132 return 0;
1133
1134 fail4:
1135 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
1136 fail3:
1137 efx->membase_phys = 0;
1138 fail2:
1139 pci_disable_device(efx->pci_dev);
1140 fail1:
1141 return rc;
1142 }
1143
1144 static void efx_fini_io(struct efx_nic *efx)
1145 {
1146 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
1147
1148 if (efx->membase) {
1149 iounmap(efx->membase);
1150 efx->membase = NULL;
1151 }
1152
1153 if (efx->membase_phys) {
1154 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
1155 efx->membase_phys = 0;
1156 }
1157
1158 pci_disable_device(efx->pci_dev);
1159 }
1160
1161 /* Get number of channels wanted. Each channel will have its own IRQ,
1162 * 1 RX queue and/or 2 TX queues. */
1163 static int efx_wanted_channels(void)
1164 {
1165 cpumask_var_t core_mask;
1166 int count;
1167 int cpu;
1168
1169 if (rss_cpus)
1170 return rss_cpus;
1171
1172 if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) {
1173 printk(KERN_WARNING
1174 "sfc: RSS disabled due to allocation failure\n");
1175 return 1;
1176 }
1177
1178 count = 0;
1179 for_each_online_cpu(cpu) {
1180 if (!cpumask_test_cpu(cpu, core_mask)) {
1181 ++count;
1182 cpumask_or(core_mask, core_mask,
1183 topology_core_cpumask(cpu));
1184 }
1185 }
1186
1187 free_cpumask_var(core_mask);
1188 return count;
1189 }
1190
1191 static int
1192 efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries)
1193 {
1194 #ifdef CONFIG_RFS_ACCEL
1195 int i, rc;
1196
1197 efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels);
1198 if (!efx->net_dev->rx_cpu_rmap)
1199 return -ENOMEM;
1200 for (i = 0; i < efx->n_rx_channels; i++) {
1201 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
1202 xentries[i].vector);
1203 if (rc) {
1204 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
1205 efx->net_dev->rx_cpu_rmap = NULL;
1206 return rc;
1207 }
1208 }
1209 #endif
1210 return 0;
1211 }
1212
1213 /* Probe the number and type of interrupts we are able to obtain, and
1214 * the resulting numbers of channels and RX queues.
1215 */
1216 static int efx_probe_interrupts(struct efx_nic *efx)
1217 {
1218 int max_channels =
1219 min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
1220 int rc, i;
1221
1222 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
1223 struct msix_entry xentries[EFX_MAX_CHANNELS];
1224 int n_channels;
1225
1226 n_channels = efx_wanted_channels();
1227 if (separate_tx_channels)
1228 n_channels *= 2;
1229 n_channels = min(n_channels, max_channels);
1230
1231 for (i = 0; i < n_channels; i++)
1232 xentries[i].entry = i;
1233 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
1234 if (rc > 0) {
1235 netif_err(efx, drv, efx->net_dev,
1236 "WARNING: Insufficient MSI-X vectors"
1237 " available (%d < %d).\n", rc, n_channels);
1238 netif_err(efx, drv, efx->net_dev,
1239 "WARNING: Performance may be reduced.\n");
1240 EFX_BUG_ON_PARANOID(rc >= n_channels);
1241 n_channels = rc;
1242 rc = pci_enable_msix(efx->pci_dev, xentries,
1243 n_channels);
1244 }
1245
1246 if (rc == 0) {
1247 efx->n_channels = n_channels;
1248 if (separate_tx_channels) {
1249 efx->n_tx_channels =
1250 max(efx->n_channels / 2, 1U);
1251 efx->n_rx_channels =
1252 max(efx->n_channels -
1253 efx->n_tx_channels, 1U);
1254 } else {
1255 efx->n_tx_channels = efx->n_channels;
1256 efx->n_rx_channels = efx->n_channels;
1257 }
1258 rc = efx_init_rx_cpu_rmap(efx, xentries);
1259 if (rc) {
1260 pci_disable_msix(efx->pci_dev);
1261 return rc;
1262 }
1263 for (i = 0; i < n_channels; i++)
1264 efx_get_channel(efx, i)->irq =
1265 xentries[i].vector;
1266 } else {
1267 /* Fall back to single channel MSI */
1268 efx->interrupt_mode = EFX_INT_MODE_MSI;
1269 netif_err(efx, drv, efx->net_dev,
1270 "could not enable MSI-X\n");
1271 }
1272 }
1273
1274 /* Try single interrupt MSI */
1275 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
1276 efx->n_channels = 1;
1277 efx->n_rx_channels = 1;
1278 efx->n_tx_channels = 1;
1279 rc = pci_enable_msi(efx->pci_dev);
1280 if (rc == 0) {
1281 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
1282 } else {
1283 netif_err(efx, drv, efx->net_dev,
1284 "could not enable MSI\n");
1285 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1286 }
1287 }
1288
1289 /* Assume legacy interrupts */
1290 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
1291 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
1292 efx->n_rx_channels = 1;
1293 efx->n_tx_channels = 1;
1294 efx->legacy_irq = efx->pci_dev->irq;
1295 }
1296
1297 return 0;
1298 }
1299
1300 static void efx_remove_interrupts(struct efx_nic *efx)
1301 {
1302 struct efx_channel *channel;
1303
1304 /* Remove MSI/MSI-X interrupts */
1305 efx_for_each_channel(channel, efx)
1306 channel->irq = 0;
1307 pci_disable_msi(efx->pci_dev);
1308 pci_disable_msix(efx->pci_dev);
1309
1310 /* Remove legacy interrupt */
1311 efx->legacy_irq = 0;
1312 }
1313
1314 static void efx_set_channels(struct efx_nic *efx)
1315 {
1316 struct efx_channel *channel;
1317 struct efx_tx_queue *tx_queue;
1318
1319 efx->tx_channel_offset =
1320 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
1321
1322 /* We need to adjust the TX queue numbers if we have separate
1323 * RX-only and TX-only channels.
1324 */
1325 efx_for_each_channel(channel, efx) {
1326 efx_for_each_channel_tx_queue(tx_queue, channel)
1327 tx_queue->queue -= (efx->tx_channel_offset *
1328 EFX_TXQ_TYPES);
1329 }
1330 }
1331
1332 static int efx_probe_nic(struct efx_nic *efx)
1333 {
1334 size_t i;
1335 int rc;
1336
1337 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
1338
1339 /* Carry out hardware-type specific initialisation */
1340 rc = efx->type->probe(efx);
1341 if (rc)
1342 return rc;
1343
1344 /* Determine the number of channels and queues by trying to hook
1345 * in MSI-X interrupts. */
1346 rc = efx_probe_interrupts(efx);
1347 if (rc)
1348 goto fail;
1349
1350 if (efx->n_channels > 1)
1351 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
1352 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
1353 efx->rx_indir_table[i] = i % efx->n_rx_channels;
1354
1355 efx_set_channels(efx);
1356 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1357 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
1358
1359 /* Initialise the interrupt moderation settings */
1360 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true);
1361
1362 return 0;
1363
1364 fail:
1365 efx->type->remove(efx);
1366 return rc;
1367 }
1368
1369 static void efx_remove_nic(struct efx_nic *efx)
1370 {
1371 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
1372
1373 efx_remove_interrupts(efx);
1374 efx->type->remove(efx);
1375 }
1376
1377 /**************************************************************************
1378 *
1379 * NIC startup/shutdown
1380 *
1381 *************************************************************************/
1382
1383 static int efx_probe_all(struct efx_nic *efx)
1384 {
1385 int rc;
1386
1387 rc = efx_probe_nic(efx);
1388 if (rc) {
1389 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
1390 goto fail1;
1391 }
1392
1393 rc = efx_probe_port(efx);
1394 if (rc) {
1395 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
1396 goto fail2;
1397 }
1398
1399 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
1400 rc = efx_probe_channels(efx);
1401 if (rc)
1402 goto fail3;
1403
1404 rc = efx_probe_filters(efx);
1405 if (rc) {
1406 netif_err(efx, probe, efx->net_dev,
1407 "failed to create filter tables\n");
1408 goto fail4;
1409 }
1410
1411 return 0;
1412
1413 fail4:
1414 efx_remove_channels(efx);
1415 fail3:
1416 efx_remove_port(efx);
1417 fail2:
1418 efx_remove_nic(efx);
1419 fail1:
1420 return rc;
1421 }
1422
1423 /* Called after previous invocation(s) of efx_stop_all, restarts the
1424 * port, kernel transmit queue, NAPI processing and hardware interrupts,
1425 * and ensures that the port is scheduled to be reconfigured.
1426 * This function is safe to call multiple times when the NIC is in any
1427 * state. */
1428 static void efx_start_all(struct efx_nic *efx)
1429 {
1430 struct efx_channel *channel;
1431
1432 EFX_ASSERT_RESET_SERIALISED(efx);
1433
1434 /* Check that it is appropriate to restart the interface. All
1435 * of these flags are safe to read under just the rtnl lock */
1436 if (efx->port_enabled)
1437 return;
1438 if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT))
1439 return;
1440 if (efx_dev_registered(efx) && !netif_running(efx->net_dev))
1441 return;
1442
1443 /* Mark the port as enabled so port reconfigurations can start, then
1444 * restart the transmit interface early so the watchdog timer stops */
1445 efx_start_port(efx);
1446
1447 if (efx_dev_registered(efx) && netif_device_present(efx->net_dev))
1448 netif_tx_wake_all_queues(efx->net_dev);
1449
1450 efx_for_each_channel(channel, efx)
1451 efx_start_channel(channel);
1452
1453 if (efx->legacy_irq)
1454 efx->legacy_irq_enabled = true;
1455 efx_nic_enable_interrupts(efx);
1456
1457 /* Switch to event based MCDI completions after enabling interrupts.
1458 * If a reset has been scheduled, then we need to stay in polled mode.
1459 * Rather than serialising efx_mcdi_mode_event() [which sleeps] and
1460 * reset_pending [modified from an atomic context], we instead guarantee
1461 * that efx_mcdi_mode_poll() isn't reverted erroneously */
1462 efx_mcdi_mode_event(efx);
1463 if (efx->reset_pending)
1464 efx_mcdi_mode_poll(efx);
1465
1466 /* Start the hardware monitor if there is one. Otherwise (we're link
1467 * event driven), we have to poll the PHY because after an event queue
1468 * flush, we could have a missed a link state change */
1469 if (efx->type->monitor != NULL) {
1470 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1471 efx_monitor_interval);
1472 } else {
1473 mutex_lock(&efx->mac_lock);
1474 if (efx->phy_op->poll(efx))
1475 efx_link_status_changed(efx);
1476 mutex_unlock(&efx->mac_lock);
1477 }
1478
1479 efx->type->start_stats(efx);
1480 }
1481
1482 /* Flush all delayed work. Should only be called when no more delayed work
1483 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1484 * since we're holding the rtnl_lock at this point. */
1485 static void efx_flush_all(struct efx_nic *efx)
1486 {
1487 /* Make sure the hardware monitor is stopped */
1488 cancel_delayed_work_sync(&efx->monitor_work);
1489 /* Stop scheduled port reconfigurations */
1490 cancel_work_sync(&efx->mac_work);
1491 }
1492
1493 /* Quiesce hardware and software without bringing the link down.
1494 * Safe to call multiple times, when the nic and interface is in any
1495 * state. The caller is guaranteed to subsequently be in a position
1496 * to modify any hardware and software state they see fit without
1497 * taking locks. */
1498 static void efx_stop_all(struct efx_nic *efx)
1499 {
1500 struct efx_channel *channel;
1501
1502 EFX_ASSERT_RESET_SERIALISED(efx);
1503
1504 /* port_enabled can be read safely under the rtnl lock */
1505 if (!efx->port_enabled)
1506 return;
1507
1508 efx->type->stop_stats(efx);
1509
1510 /* Switch to MCDI polling on Siena before disabling interrupts */
1511 efx_mcdi_mode_poll(efx);
1512
1513 /* Disable interrupts and wait for ISR to complete */
1514 efx_nic_disable_interrupts(efx);
1515 if (efx->legacy_irq) {
1516 synchronize_irq(efx->legacy_irq);
1517 efx->legacy_irq_enabled = false;
1518 }
1519 efx_for_each_channel(channel, efx) {
1520 if (channel->irq)
1521 synchronize_irq(channel->irq);
1522 }
1523
1524 /* Stop all NAPI processing and synchronous rx refills */
1525 efx_for_each_channel(channel, efx)
1526 efx_stop_channel(channel);
1527
1528 /* Stop all asynchronous port reconfigurations. Since all
1529 * event processing has already been stopped, there is no
1530 * window to loose phy events */
1531 efx_stop_port(efx);
1532
1533 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
1534 efx_flush_all(efx);
1535
1536 /* Stop the kernel transmit interface late, so the watchdog
1537 * timer isn't ticking over the flush */
1538 if (efx_dev_registered(efx)) {
1539 netif_tx_stop_all_queues(efx->net_dev);
1540 netif_tx_lock_bh(efx->net_dev);
1541 netif_tx_unlock_bh(efx->net_dev);
1542 }
1543 }
1544
1545 static void efx_remove_all(struct efx_nic *efx)
1546 {
1547 efx_remove_filters(efx);
1548 efx_remove_channels(efx);
1549 efx_remove_port(efx);
1550 efx_remove_nic(efx);
1551 }
1552
1553 /**************************************************************************
1554 *
1555 * Interrupt moderation
1556 *
1557 **************************************************************************/
1558
1559 static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int resolution)
1560 {
1561 if (usecs == 0)
1562 return 0;
1563 if (usecs < resolution)
1564 return 1; /* never round down to 0 */
1565 return usecs / resolution;
1566 }
1567
1568 /* Set interrupt moderation parameters */
1569 void efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1570 unsigned int rx_usecs, bool rx_adaptive)
1571 {
1572 struct efx_channel *channel;
1573 unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION);
1574 unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION);
1575
1576 EFX_ASSERT_RESET_SERIALISED(efx);
1577
1578 efx->irq_rx_adaptive = rx_adaptive;
1579 efx->irq_rx_moderation = rx_ticks;
1580 efx_for_each_channel(channel, efx) {
1581 if (efx_channel_has_rx_queue(channel))
1582 channel->irq_moderation = rx_ticks;
1583 else if (efx_channel_has_tx_queues(channel))
1584 channel->irq_moderation = tx_ticks;
1585 }
1586 }
1587
1588 /**************************************************************************
1589 *
1590 * Hardware monitor
1591 *
1592 **************************************************************************/
1593
1594 /* Run periodically off the general workqueue */
1595 static void efx_monitor(struct work_struct *data)
1596 {
1597 struct efx_nic *efx = container_of(data, struct efx_nic,
1598 monitor_work.work);
1599
1600 netif_vdbg(efx, timer, efx->net_dev,
1601 "hardware monitor executing on CPU %d\n",
1602 raw_smp_processor_id());
1603 BUG_ON(efx->type->monitor == NULL);
1604
1605 /* If the mac_lock is already held then it is likely a port
1606 * reconfiguration is already in place, which will likely do
1607 * most of the work of monitor() anyway. */
1608 if (mutex_trylock(&efx->mac_lock)) {
1609 if (efx->port_enabled)
1610 efx->type->monitor(efx);
1611 mutex_unlock(&efx->mac_lock);
1612 }
1613
1614 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1615 efx_monitor_interval);
1616 }
1617
1618 /**************************************************************************
1619 *
1620 * ioctls
1621 *
1622 *************************************************************************/
1623
1624 /* Net device ioctl
1625 * Context: process, rtnl_lock() held.
1626 */
1627 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1628 {
1629 struct efx_nic *efx = netdev_priv(net_dev);
1630 struct mii_ioctl_data *data = if_mii(ifr);
1631
1632 EFX_ASSERT_RESET_SERIALISED(efx);
1633
1634 /* Convert phy_id from older PRTAD/DEVAD format */
1635 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1636 (data->phy_id & 0xfc00) == 0x0400)
1637 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1638
1639 return mdio_mii_ioctl(&efx->mdio, data, cmd);
1640 }
1641
1642 /**************************************************************************
1643 *
1644 * NAPI interface
1645 *
1646 **************************************************************************/
1647
1648 static void efx_init_napi(struct efx_nic *efx)
1649 {
1650 struct efx_channel *channel;
1651
1652 efx_for_each_channel(channel, efx) {
1653 channel->napi_dev = efx->net_dev;
1654 netif_napi_add(channel->napi_dev, &channel->napi_str,
1655 efx_poll, napi_weight);
1656 }
1657 }
1658
1659 static void efx_fini_napi_channel(struct efx_channel *channel)
1660 {
1661 if (channel->napi_dev)
1662 netif_napi_del(&channel->napi_str);
1663 channel->napi_dev = NULL;
1664 }
1665
1666 static void efx_fini_napi(struct efx_nic *efx)
1667 {
1668 struct efx_channel *channel;
1669
1670 efx_for_each_channel(channel, efx)
1671 efx_fini_napi_channel(channel);
1672 }
1673
1674 /**************************************************************************
1675 *
1676 * Kernel netpoll interface
1677 *
1678 *************************************************************************/
1679
1680 #ifdef CONFIG_NET_POLL_CONTROLLER
1681
1682 /* Although in the common case interrupts will be disabled, this is not
1683 * guaranteed. However, all our work happens inside the NAPI callback,
1684 * so no locking is required.
1685 */
1686 static void efx_netpoll(struct net_device *net_dev)
1687 {
1688 struct efx_nic *efx = netdev_priv(net_dev);
1689 struct efx_channel *channel;
1690
1691 efx_for_each_channel(channel, efx)
1692 efx_schedule_channel(channel);
1693 }
1694
1695 #endif
1696
1697 /**************************************************************************
1698 *
1699 * Kernel net device interface
1700 *
1701 *************************************************************************/
1702
1703 /* Context: process, rtnl_lock() held. */
1704 static int efx_net_open(struct net_device *net_dev)
1705 {
1706 struct efx_nic *efx = netdev_priv(net_dev);
1707 EFX_ASSERT_RESET_SERIALISED(efx);
1708
1709 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1710 raw_smp_processor_id());
1711
1712 if (efx->state == STATE_DISABLED)
1713 return -EIO;
1714 if (efx->phy_mode & PHY_MODE_SPECIAL)
1715 return -EBUSY;
1716 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1717 return -EIO;
1718
1719 /* Notify the kernel of the link state polled during driver load,
1720 * before the monitor starts running */
1721 efx_link_status_changed(efx);
1722
1723 efx_start_all(efx);
1724 return 0;
1725 }
1726
1727 /* Context: process, rtnl_lock() held.
1728 * Note that the kernel will ignore our return code; this method
1729 * should really be a void.
1730 */
1731 static int efx_net_stop(struct net_device *net_dev)
1732 {
1733 struct efx_nic *efx = netdev_priv(net_dev);
1734
1735 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1736 raw_smp_processor_id());
1737
1738 if (efx->state != STATE_DISABLED) {
1739 /* Stop the device and flush all the channels */
1740 efx_stop_all(efx);
1741 efx_fini_channels(efx);
1742 efx_init_channels(efx);
1743 }
1744
1745 return 0;
1746 }
1747
1748 /* Context: process, dev_base_lock or RTNL held, non-blocking. */
1749 static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats)
1750 {
1751 struct efx_nic *efx = netdev_priv(net_dev);
1752 struct efx_mac_stats *mac_stats = &efx->mac_stats;
1753
1754 spin_lock_bh(&efx->stats_lock);
1755 efx->type->update_stats(efx);
1756 spin_unlock_bh(&efx->stats_lock);
1757
1758 stats->rx_packets = mac_stats->rx_packets;
1759 stats->tx_packets = mac_stats->tx_packets;
1760 stats->rx_bytes = mac_stats->rx_bytes;
1761 stats->tx_bytes = mac_stats->tx_bytes;
1762 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt;
1763 stats->multicast = mac_stats->rx_multicast;
1764 stats->collisions = mac_stats->tx_collision;
1765 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1766 mac_stats->rx_length_error);
1767 stats->rx_crc_errors = mac_stats->rx_bad;
1768 stats->rx_frame_errors = mac_stats->rx_align_error;
1769 stats->rx_fifo_errors = mac_stats->rx_overflow;
1770 stats->rx_missed_errors = mac_stats->rx_missed;
1771 stats->tx_window_errors = mac_stats->tx_late_collision;
1772
1773 stats->rx_errors = (stats->rx_length_errors +
1774 stats->rx_crc_errors +
1775 stats->rx_frame_errors +
1776 mac_stats->rx_symbol_error);
1777 stats->tx_errors = (stats->tx_window_errors +
1778 mac_stats->tx_bad);
1779
1780 return stats;
1781 }
1782
1783 /* Context: netif_tx_lock held, BHs disabled. */
1784 static void efx_watchdog(struct net_device *net_dev)
1785 {
1786 struct efx_nic *efx = netdev_priv(net_dev);
1787
1788 netif_err(efx, tx_err, efx->net_dev,
1789 "TX stuck with port_enabled=%d: resetting channels\n",
1790 efx->port_enabled);
1791
1792 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
1793 }
1794
1795
1796 /* Context: process, rtnl_lock() held. */
1797 static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1798 {
1799 struct efx_nic *efx = netdev_priv(net_dev);
1800 int rc = 0;
1801
1802 EFX_ASSERT_RESET_SERIALISED(efx);
1803
1804 if (new_mtu > EFX_MAX_MTU)
1805 return -EINVAL;
1806
1807 efx_stop_all(efx);
1808
1809 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
1810
1811 efx_fini_channels(efx);
1812
1813 mutex_lock(&efx->mac_lock);
1814 /* Reconfigure the MAC before enabling the dma queues so that
1815 * the RX buffers don't overflow */
1816 net_dev->mtu = new_mtu;
1817 efx->mac_op->reconfigure(efx);
1818 mutex_unlock(&efx->mac_lock);
1819
1820 efx_init_channels(efx);
1821
1822 efx_start_all(efx);
1823 return rc;
1824 }
1825
1826 static int efx_set_mac_address(struct net_device *net_dev, void *data)
1827 {
1828 struct efx_nic *efx = netdev_priv(net_dev);
1829 struct sockaddr *addr = data;
1830 char *new_addr = addr->sa_data;
1831
1832 EFX_ASSERT_RESET_SERIALISED(efx);
1833
1834 if (!is_valid_ether_addr(new_addr)) {
1835 netif_err(efx, drv, efx->net_dev,
1836 "invalid ethernet MAC address requested: %pM\n",
1837 new_addr);
1838 return -EINVAL;
1839 }
1840
1841 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
1842
1843 /* Reconfigure the MAC */
1844 mutex_lock(&efx->mac_lock);
1845 efx->mac_op->reconfigure(efx);
1846 mutex_unlock(&efx->mac_lock);
1847
1848 return 0;
1849 }
1850
1851 /* Context: netif_addr_lock held, BHs disabled. */
1852 static void efx_set_multicast_list(struct net_device *net_dev)
1853 {
1854 struct efx_nic *efx = netdev_priv(net_dev);
1855 struct netdev_hw_addr *ha;
1856 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1857 u32 crc;
1858 int bit;
1859
1860 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC);
1861
1862 /* Build multicast hash table */
1863 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
1864 memset(mc_hash, 0xff, sizeof(*mc_hash));
1865 } else {
1866 memset(mc_hash, 0x00, sizeof(*mc_hash));
1867 netdev_for_each_mc_addr(ha, net_dev) {
1868 crc = ether_crc_le(ETH_ALEN, ha->addr);
1869 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
1870 set_bit_le(bit, mc_hash->byte);
1871 }
1872
1873 /* Broadcast packets go through the multicast hash filter.
1874 * ether_crc_le() of the broadcast address is 0xbe2612ff
1875 * so we always add bit 0xff to the mask.
1876 */
1877 set_bit_le(0xff, mc_hash->byte);
1878 }
1879
1880 if (efx->port_enabled)
1881 queue_work(efx->workqueue, &efx->mac_work);
1882 /* Otherwise efx_start_port() will do this */
1883 }
1884
1885 static int efx_set_features(struct net_device *net_dev, u32 data)
1886 {
1887 struct efx_nic *efx = netdev_priv(net_dev);
1888
1889 /* If disabling RX n-tuple filtering, clear existing filters */
1890 if (net_dev->features & ~data & NETIF_F_NTUPLE)
1891 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
1892
1893 return 0;
1894 }
1895
1896 static const struct net_device_ops efx_netdev_ops = {
1897 .ndo_open = efx_net_open,
1898 .ndo_stop = efx_net_stop,
1899 .ndo_get_stats64 = efx_net_stats,
1900 .ndo_tx_timeout = efx_watchdog,
1901 .ndo_start_xmit = efx_hard_start_xmit,
1902 .ndo_validate_addr = eth_validate_addr,
1903 .ndo_do_ioctl = efx_ioctl,
1904 .ndo_change_mtu = efx_change_mtu,
1905 .ndo_set_mac_address = efx_set_mac_address,
1906 .ndo_set_rx_mode = efx_set_multicast_list,
1907 .ndo_set_features = efx_set_features,
1908 #ifdef CONFIG_NET_POLL_CONTROLLER
1909 .ndo_poll_controller = efx_netpoll,
1910 #endif
1911 .ndo_setup_tc = efx_setup_tc,
1912 #ifdef CONFIG_RFS_ACCEL
1913 .ndo_rx_flow_steer = efx_filter_rfs,
1914 #endif
1915 };
1916
1917 static void efx_update_name(struct efx_nic *efx)
1918 {
1919 strcpy(efx->name, efx->net_dev->name);
1920 efx_mtd_rename(efx);
1921 efx_set_channel_names(efx);
1922 }
1923
1924 static int efx_netdev_event(struct notifier_block *this,
1925 unsigned long event, void *ptr)
1926 {
1927 struct net_device *net_dev = ptr;
1928
1929 if (net_dev->netdev_ops == &efx_netdev_ops &&
1930 event == NETDEV_CHANGENAME)
1931 efx_update_name(netdev_priv(net_dev));
1932
1933 return NOTIFY_DONE;
1934 }
1935
1936 static struct notifier_block efx_netdev_notifier = {
1937 .notifier_call = efx_netdev_event,
1938 };
1939
1940 static ssize_t
1941 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
1942 {
1943 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
1944 return sprintf(buf, "%d\n", efx->phy_type);
1945 }
1946 static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
1947
1948 static int efx_register_netdev(struct efx_nic *efx)
1949 {
1950 struct net_device *net_dev = efx->net_dev;
1951 struct efx_channel *channel;
1952 int rc;
1953
1954 net_dev->watchdog_timeo = 5 * HZ;
1955 net_dev->irq = efx->pci_dev->irq;
1956 net_dev->netdev_ops = &efx_netdev_ops;
1957 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
1958
1959 /* Clear MAC statistics */
1960 efx->mac_op->update_stats(efx);
1961 memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
1962
1963 rtnl_lock();
1964
1965 rc = dev_alloc_name(net_dev, net_dev->name);
1966 if (rc < 0)
1967 goto fail_locked;
1968 efx_update_name(efx);
1969
1970 rc = register_netdevice(net_dev);
1971 if (rc)
1972 goto fail_locked;
1973
1974 efx_for_each_channel(channel, efx) {
1975 struct efx_tx_queue *tx_queue;
1976 efx_for_each_channel_tx_queue(tx_queue, channel)
1977 efx_init_tx_queue_core_txq(tx_queue);
1978 }
1979
1980 /* Always start with carrier off; PHY events will detect the link */
1981 netif_carrier_off(efx->net_dev);
1982
1983 rtnl_unlock();
1984
1985 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
1986 if (rc) {
1987 netif_err(efx, drv, efx->net_dev,
1988 "failed to init net dev attributes\n");
1989 goto fail_registered;
1990 }
1991
1992 return 0;
1993
1994 fail_locked:
1995 rtnl_unlock();
1996 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
1997 return rc;
1998
1999 fail_registered:
2000 unregister_netdev(net_dev);
2001 return rc;
2002 }
2003
2004 static void efx_unregister_netdev(struct efx_nic *efx)
2005 {
2006 struct efx_channel *channel;
2007 struct efx_tx_queue *tx_queue;
2008
2009 if (!efx->net_dev)
2010 return;
2011
2012 BUG_ON(netdev_priv(efx->net_dev) != efx);
2013
2014 /* Free up any skbs still remaining. This has to happen before
2015 * we try to unregister the netdev as running their destructors
2016 * may be needed to get the device ref. count to 0. */
2017 efx_for_each_channel(channel, efx) {
2018 efx_for_each_channel_tx_queue(tx_queue, channel)
2019 efx_release_tx_buffers(tx_queue);
2020 }
2021
2022 if (efx_dev_registered(efx)) {
2023 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2024 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2025 unregister_netdev(efx->net_dev);
2026 }
2027 }
2028
2029 /**************************************************************************
2030 *
2031 * Device reset and suspend
2032 *
2033 **************************************************************************/
2034
2035 /* Tears down the entire software state and most of the hardware state
2036 * before reset. */
2037 void efx_reset_down(struct efx_nic *efx, enum reset_type method)
2038 {
2039 EFX_ASSERT_RESET_SERIALISED(efx);
2040
2041 efx_stop_all(efx);
2042 mutex_lock(&efx->mac_lock);
2043
2044 efx_fini_channels(efx);
2045 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2046 efx->phy_op->fini(efx);
2047 efx->type->fini(efx);
2048 }
2049
2050 /* This function will always ensure that the locks acquired in
2051 * efx_reset_down() are released. A failure return code indicates
2052 * that we were unable to reinitialise the hardware, and the
2053 * driver should be disabled. If ok is false, then the rx and tx
2054 * engines are not restarted, pending a RESET_DISABLE. */
2055 int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
2056 {
2057 int rc;
2058
2059 EFX_ASSERT_RESET_SERIALISED(efx);
2060
2061 rc = efx->type->init(efx);
2062 if (rc) {
2063 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
2064 goto fail;
2065 }
2066
2067 if (!ok)
2068 goto fail;
2069
2070 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
2071 rc = efx->phy_op->init(efx);
2072 if (rc)
2073 goto fail;
2074 if (efx->phy_op->reconfigure(efx))
2075 netif_err(efx, drv, efx->net_dev,
2076 "could not restore PHY settings\n");
2077 }
2078
2079 efx->mac_op->reconfigure(efx);
2080
2081 efx_init_channels(efx);
2082 efx_restore_filters(efx);
2083
2084 mutex_unlock(&efx->mac_lock);
2085
2086 efx_start_all(efx);
2087
2088 return 0;
2089
2090 fail:
2091 efx->port_initialized = false;
2092
2093 mutex_unlock(&efx->mac_lock);
2094
2095 return rc;
2096 }
2097
2098 /* Reset the NIC using the specified method. Note that the reset may
2099 * fail, in which case the card will be left in an unusable state.
2100 *
2101 * Caller must hold the rtnl_lock.
2102 */
2103 int efx_reset(struct efx_nic *efx, enum reset_type method)
2104 {
2105 int rc, rc2;
2106 bool disabled;
2107
2108 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2109 RESET_TYPE(method));
2110
2111 netif_device_detach(efx->net_dev);
2112 efx_reset_down(efx, method);
2113
2114 rc = efx->type->reset(efx, method);
2115 if (rc) {
2116 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
2117 goto out;
2118 }
2119
2120 /* Clear flags for the scopes we covered. We assume the NIC and
2121 * driver are now quiescent so that there is no race here.
2122 */
2123 efx->reset_pending &= -(1 << (method + 1));
2124
2125 /* Reinitialise bus-mastering, which may have been turned off before
2126 * the reset was scheduled. This is still appropriate, even in the
2127 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2128 * can respond to requests. */
2129 pci_set_master(efx->pci_dev);
2130
2131 out:
2132 /* Leave device stopped if necessary */
2133 disabled = rc || method == RESET_TYPE_DISABLE;
2134 rc2 = efx_reset_up(efx, method, !disabled);
2135 if (rc2) {
2136 disabled = true;
2137 if (!rc)
2138 rc = rc2;
2139 }
2140
2141 if (disabled) {
2142 dev_close(efx->net_dev);
2143 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
2144 efx->state = STATE_DISABLED;
2145 } else {
2146 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
2147 netif_device_attach(efx->net_dev);
2148 }
2149 return rc;
2150 }
2151
2152 /* The worker thread exists so that code that cannot sleep can
2153 * schedule a reset for later.
2154 */
2155 static void efx_reset_work(struct work_struct *data)
2156 {
2157 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
2158 unsigned long pending = ACCESS_ONCE(efx->reset_pending);
2159
2160 if (!pending)
2161 return;
2162
2163 /* If we're not RUNNING then don't reset. Leave the reset_pending
2164 * flags set so that efx_pci_probe_main will be retried */
2165 if (efx->state != STATE_RUNNING) {
2166 netif_info(efx, drv, efx->net_dev,
2167 "scheduled reset quenched. NIC not RUNNING\n");
2168 return;
2169 }
2170
2171 rtnl_lock();
2172 (void)efx_reset(efx, fls(pending) - 1);
2173 rtnl_unlock();
2174 }
2175
2176 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2177 {
2178 enum reset_type method;
2179
2180 switch (type) {
2181 case RESET_TYPE_INVISIBLE:
2182 case RESET_TYPE_ALL:
2183 case RESET_TYPE_WORLD:
2184 case RESET_TYPE_DISABLE:
2185 method = type;
2186 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2187 RESET_TYPE(method));
2188 break;
2189 default:
2190 method = efx->type->map_reset_reason(type);
2191 netif_dbg(efx, drv, efx->net_dev,
2192 "scheduling %s reset for %s\n",
2193 RESET_TYPE(method), RESET_TYPE(type));
2194 break;
2195 }
2196
2197 set_bit(method, &efx->reset_pending);
2198
2199 /* efx_process_channel() will no longer read events once a
2200 * reset is scheduled. So switch back to poll'd MCDI completions. */
2201 efx_mcdi_mode_poll(efx);
2202
2203 queue_work(reset_workqueue, &efx->reset_work);
2204 }
2205
2206 /**************************************************************************
2207 *
2208 * List of NICs we support
2209 *
2210 **************************************************************************/
2211
2212 /* PCI device ID table */
2213 static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
2214 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID),
2215 .driver_data = (unsigned long) &falcon_a1_nic_type},
2216 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID),
2217 .driver_data = (unsigned long) &falcon_b0_nic_type},
2218 {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID),
2219 .driver_data = (unsigned long) &siena_a0_nic_type},
2220 {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID),
2221 .driver_data = (unsigned long) &siena_a0_nic_type},
2222 {0} /* end of list */
2223 };
2224
2225 /**************************************************************************
2226 *
2227 * Dummy PHY/MAC operations
2228 *
2229 * Can be used for some unimplemented operations
2230 * Needed so all function pointers are valid and do not have to be tested
2231 * before use
2232 *
2233 **************************************************************************/
2234 int efx_port_dummy_op_int(struct efx_nic *efx)
2235 {
2236 return 0;
2237 }
2238 void efx_port_dummy_op_void(struct efx_nic *efx) {}
2239
2240 static bool efx_port_dummy_op_poll(struct efx_nic *efx)
2241 {
2242 return false;
2243 }
2244
2245 static const struct efx_phy_operations efx_dummy_phy_operations = {
2246 .init = efx_port_dummy_op_int,
2247 .reconfigure = efx_port_dummy_op_int,
2248 .poll = efx_port_dummy_op_poll,
2249 .fini = efx_port_dummy_op_void,
2250 };
2251
2252 /**************************************************************************
2253 *
2254 * Data housekeeping
2255 *
2256 **************************************************************************/
2257
2258 /* This zeroes out and then fills in the invariants in a struct
2259 * efx_nic (including all sub-structures).
2260 */
2261 static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type,
2262 struct pci_dev *pci_dev, struct net_device *net_dev)
2263 {
2264 int i;
2265
2266 /* Initialise common structures */
2267 memset(efx, 0, sizeof(*efx));
2268 spin_lock_init(&efx->biu_lock);
2269 #ifdef CONFIG_SFC_MTD
2270 INIT_LIST_HEAD(&efx->mtd_list);
2271 #endif
2272 INIT_WORK(&efx->reset_work, efx_reset_work);
2273 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
2274 efx->pci_dev = pci_dev;
2275 efx->msg_enable = debug;
2276 efx->state = STATE_INIT;
2277 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
2278
2279 efx->net_dev = net_dev;
2280 spin_lock_init(&efx->stats_lock);
2281 mutex_init(&efx->mac_lock);
2282 efx->mac_op = type->default_mac_ops;
2283 efx->phy_op = &efx_dummy_phy_operations;
2284 efx->mdio.dev = net_dev;
2285 INIT_WORK(&efx->mac_work, efx_mac_work);
2286
2287 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
2288 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2289 if (!efx->channel[i])
2290 goto fail;
2291 }
2292
2293 efx->type = type;
2294
2295 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
2296
2297 /* Higher numbered interrupt modes are less capable! */
2298 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2299 interrupt_mode);
2300
2301 /* Would be good to use the net_dev name, but we're too early */
2302 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2303 pci_name(pci_dev));
2304 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
2305 if (!efx->workqueue)
2306 goto fail;
2307
2308 return 0;
2309
2310 fail:
2311 efx_fini_struct(efx);
2312 return -ENOMEM;
2313 }
2314
2315 static void efx_fini_struct(struct efx_nic *efx)
2316 {
2317 int i;
2318
2319 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2320 kfree(efx->channel[i]);
2321
2322 if (efx->workqueue) {
2323 destroy_workqueue(efx->workqueue);
2324 efx->workqueue = NULL;
2325 }
2326 }
2327
2328 /**************************************************************************
2329 *
2330 * PCI interface
2331 *
2332 **************************************************************************/
2333
2334 /* Main body of final NIC shutdown code
2335 * This is called only at module unload (or hotplug removal).
2336 */
2337 static void efx_pci_remove_main(struct efx_nic *efx)
2338 {
2339 #ifdef CONFIG_RFS_ACCEL
2340 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
2341 efx->net_dev->rx_cpu_rmap = NULL;
2342 #endif
2343 efx_nic_fini_interrupt(efx);
2344 efx_fini_channels(efx);
2345 efx_fini_port(efx);
2346 efx->type->fini(efx);
2347 efx_fini_napi(efx);
2348 efx_remove_all(efx);
2349 }
2350
2351 /* Final NIC shutdown
2352 * This is called only at module unload (or hotplug removal).
2353 */
2354 static void efx_pci_remove(struct pci_dev *pci_dev)
2355 {
2356 struct efx_nic *efx;
2357
2358 efx = pci_get_drvdata(pci_dev);
2359 if (!efx)
2360 return;
2361
2362 /* Mark the NIC as fini, then stop the interface */
2363 rtnl_lock();
2364 efx->state = STATE_FINI;
2365 dev_close(efx->net_dev);
2366
2367 /* Allow any queued efx_resets() to complete */
2368 rtnl_unlock();
2369
2370 efx_unregister_netdev(efx);
2371
2372 efx_mtd_remove(efx);
2373
2374 /* Wait for any scheduled resets to complete. No more will be
2375 * scheduled from this point because efx_stop_all() has been
2376 * called, we are no longer registered with driverlink, and
2377 * the net_device's have been removed. */
2378 cancel_work_sync(&efx->reset_work);
2379
2380 efx_pci_remove_main(efx);
2381
2382 efx_fini_io(efx);
2383 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
2384
2385 pci_set_drvdata(pci_dev, NULL);
2386 efx_fini_struct(efx);
2387 free_netdev(efx->net_dev);
2388 };
2389
2390 /* Main body of NIC initialisation
2391 * This is called at module load (or hotplug insertion, theoretically).
2392 */
2393 static int efx_pci_probe_main(struct efx_nic *efx)
2394 {
2395 int rc;
2396
2397 /* Do start-of-day initialisation */
2398 rc = efx_probe_all(efx);
2399 if (rc)
2400 goto fail1;
2401
2402 efx_init_napi(efx);
2403
2404 rc = efx->type->init(efx);
2405 if (rc) {
2406 netif_err(efx, probe, efx->net_dev,
2407 "failed to initialise NIC\n");
2408 goto fail3;
2409 }
2410
2411 rc = efx_init_port(efx);
2412 if (rc) {
2413 netif_err(efx, probe, efx->net_dev,
2414 "failed to initialise port\n");
2415 goto fail4;
2416 }
2417
2418 efx_init_channels(efx);
2419
2420 rc = efx_nic_init_interrupt(efx);
2421 if (rc)
2422 goto fail5;
2423
2424 return 0;
2425
2426 fail5:
2427 efx_fini_channels(efx);
2428 efx_fini_port(efx);
2429 fail4:
2430 efx->type->fini(efx);
2431 fail3:
2432 efx_fini_napi(efx);
2433 efx_remove_all(efx);
2434 fail1:
2435 return rc;
2436 }
2437
2438 /* NIC initialisation
2439 *
2440 * This is called at module load (or hotplug insertion,
2441 * theoretically). It sets up PCI mappings, tests and resets the NIC,
2442 * sets up and registers the network devices with the kernel and hooks
2443 * the interrupt service routine. It does not prepare the device for
2444 * transmission; this is left to the first time one of the network
2445 * interfaces is brought up (i.e. efx_net_open).
2446 */
2447 static int __devinit efx_pci_probe(struct pci_dev *pci_dev,
2448 const struct pci_device_id *entry)
2449 {
2450 const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data;
2451 struct net_device *net_dev;
2452 struct efx_nic *efx;
2453 int i, rc;
2454
2455 /* Allocate and initialise a struct net_device and struct efx_nic */
2456 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2457 EFX_MAX_RX_QUEUES);
2458 if (!net_dev)
2459 return -ENOMEM;
2460 net_dev->features |= (type->offload_features | NETIF_F_SG |
2461 NETIF_F_HIGHDMA | NETIF_F_TSO |
2462 NETIF_F_RXCSUM);
2463 if (type->offload_features & NETIF_F_V6_CSUM)
2464 net_dev->features |= NETIF_F_TSO6;
2465 /* Mask for features that also apply to VLAN devices */
2466 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
2467 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2468 NETIF_F_RXCSUM);
2469 /* All offloads can be toggled */
2470 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
2471 efx = netdev_priv(net_dev);
2472 pci_set_drvdata(pci_dev, efx);
2473 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
2474 rc = efx_init_struct(efx, type, pci_dev, net_dev);
2475 if (rc)
2476 goto fail1;
2477
2478 netif_info(efx, probe, efx->net_dev,
2479 "Solarflare NIC detected\n");
2480
2481 /* Set up basic I/O (BAR mappings etc) */
2482 rc = efx_init_io(efx);
2483 if (rc)
2484 goto fail2;
2485
2486 /* No serialisation is required with the reset path because
2487 * we're in STATE_INIT. */
2488 for (i = 0; i < 5; i++) {
2489 rc = efx_pci_probe_main(efx);
2490
2491 /* Serialise against efx_reset(). No more resets will be
2492 * scheduled since efx_stop_all() has been called, and we
2493 * have not and never have been registered with either
2494 * the rtnetlink or driverlink layers. */
2495 cancel_work_sync(&efx->reset_work);
2496
2497 if (rc == 0) {
2498 if (efx->reset_pending) {
2499 /* If there was a scheduled reset during
2500 * probe, the NIC is probably hosed anyway */
2501 efx_pci_remove_main(efx);
2502 rc = -EIO;
2503 } else {
2504 break;
2505 }
2506 }
2507
2508 /* Retry if a recoverably reset event has been scheduled */
2509 if (efx->reset_pending &
2510 ~(1 << RESET_TYPE_INVISIBLE | 1 << RESET_TYPE_ALL) ||
2511 !efx->reset_pending)
2512 goto fail3;
2513
2514 efx->reset_pending = 0;
2515 }
2516
2517 if (rc) {
2518 netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n");
2519 goto fail4;
2520 }
2521
2522 /* Switch to the running state before we expose the device to the OS,
2523 * so that dev_open()|efx_start_all() will actually start the device */
2524 efx->state = STATE_RUNNING;
2525
2526 rc = efx_register_netdev(efx);
2527 if (rc)
2528 goto fail5;
2529
2530 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
2531
2532 rtnl_lock();
2533 efx_mtd_probe(efx); /* allowed to fail */
2534 rtnl_unlock();
2535 return 0;
2536
2537 fail5:
2538 efx_pci_remove_main(efx);
2539 fail4:
2540 fail3:
2541 efx_fini_io(efx);
2542 fail2:
2543 efx_fini_struct(efx);
2544 fail1:
2545 WARN_ON(rc > 0);
2546 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
2547 free_netdev(net_dev);
2548 return rc;
2549 }
2550
2551 static int efx_pm_freeze(struct device *dev)
2552 {
2553 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2554
2555 efx->state = STATE_FINI;
2556
2557 netif_device_detach(efx->net_dev);
2558
2559 efx_stop_all(efx);
2560 efx_fini_channels(efx);
2561
2562 return 0;
2563 }
2564
2565 static int efx_pm_thaw(struct device *dev)
2566 {
2567 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2568
2569 efx->state = STATE_INIT;
2570
2571 efx_init_channels(efx);
2572
2573 mutex_lock(&efx->mac_lock);
2574 efx->phy_op->reconfigure(efx);
2575 mutex_unlock(&efx->mac_lock);
2576
2577 efx_start_all(efx);
2578
2579 netif_device_attach(efx->net_dev);
2580
2581 efx->state = STATE_RUNNING;
2582
2583 efx->type->resume_wol(efx);
2584
2585 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2586 queue_work(reset_workqueue, &efx->reset_work);
2587
2588 return 0;
2589 }
2590
2591 static int efx_pm_poweroff(struct device *dev)
2592 {
2593 struct pci_dev *pci_dev = to_pci_dev(dev);
2594 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2595
2596 efx->type->fini(efx);
2597
2598 efx->reset_pending = 0;
2599
2600 pci_save_state(pci_dev);
2601 return pci_set_power_state(pci_dev, PCI_D3hot);
2602 }
2603
2604 /* Used for both resume and restore */
2605 static int efx_pm_resume(struct device *dev)
2606 {
2607 struct pci_dev *pci_dev = to_pci_dev(dev);
2608 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2609 int rc;
2610
2611 rc = pci_set_power_state(pci_dev, PCI_D0);
2612 if (rc)
2613 return rc;
2614 pci_restore_state(pci_dev);
2615 rc = pci_enable_device(pci_dev);
2616 if (rc)
2617 return rc;
2618 pci_set_master(efx->pci_dev);
2619 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2620 if (rc)
2621 return rc;
2622 rc = efx->type->init(efx);
2623 if (rc)
2624 return rc;
2625 efx_pm_thaw(dev);
2626 return 0;
2627 }
2628
2629 static int efx_pm_suspend(struct device *dev)
2630 {
2631 int rc;
2632
2633 efx_pm_freeze(dev);
2634 rc = efx_pm_poweroff(dev);
2635 if (rc)
2636 efx_pm_resume(dev);
2637 return rc;
2638 }
2639
2640 static struct dev_pm_ops efx_pm_ops = {
2641 .suspend = efx_pm_suspend,
2642 .resume = efx_pm_resume,
2643 .freeze = efx_pm_freeze,
2644 .thaw = efx_pm_thaw,
2645 .poweroff = efx_pm_poweroff,
2646 .restore = efx_pm_resume,
2647 };
2648
2649 static struct pci_driver efx_pci_driver = {
2650 .name = KBUILD_MODNAME,
2651 .id_table = efx_pci_table,
2652 .probe = efx_pci_probe,
2653 .remove = efx_pci_remove,
2654 .driver.pm = &efx_pm_ops,
2655 };
2656
2657 /**************************************************************************
2658 *
2659 * Kernel module interface
2660 *
2661 *************************************************************************/
2662
2663 module_param(interrupt_mode, uint, 0444);
2664 MODULE_PARM_DESC(interrupt_mode,
2665 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2666
2667 static int __init efx_init_module(void)
2668 {
2669 int rc;
2670
2671 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2672
2673 rc = register_netdevice_notifier(&efx_netdev_notifier);
2674 if (rc)
2675 goto err_notifier;
2676
2677 reset_workqueue = create_singlethread_workqueue("sfc_reset");
2678 if (!reset_workqueue) {
2679 rc = -ENOMEM;
2680 goto err_reset;
2681 }
2682
2683 rc = pci_register_driver(&efx_pci_driver);
2684 if (rc < 0)
2685 goto err_pci;
2686
2687 return 0;
2688
2689 err_pci:
2690 destroy_workqueue(reset_workqueue);
2691 err_reset:
2692 unregister_netdevice_notifier(&efx_netdev_notifier);
2693 err_notifier:
2694 return rc;
2695 }
2696
2697 static void __exit efx_exit_module(void)
2698 {
2699 printk(KERN_INFO "Solarflare NET driver unloading\n");
2700
2701 pci_unregister_driver(&efx_pci_driver);
2702 destroy_workqueue(reset_workqueue);
2703 unregister_netdevice_notifier(&efx_netdev_notifier);
2704
2705 }
2706
2707 module_init(efx_init_module);
2708 module_exit(efx_exit_module);
2709
2710 MODULE_AUTHOR("Solarflare Communications and "
2711 "Michael Brown <mbrown@fensystems.co.uk>");
2712 MODULE_DESCRIPTION("Solarflare Communications network driver");
2713 MODULE_LICENSE("GPL");
2714 MODULE_DEVICE_TABLE(pci, efx_pci_table);
Linux with added FPC-III support