drivers/usb/host/xhci.h

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #ifndef __LINUX_XHCI_HCD_H
  24 #define __LINUX_XHCI_HCD_H
  25
  26 #include <linux/usb.h>
  27 #include <linux/timer.h>
  28 #include <linux/kernel.h>
  29 #include <linux/usb/hcd.h>
  30
  31 /* Code sharing between pci-quirks and xhci hcd */
  32 #include        "xhci-ext-caps.h"
  33 #include "pci-quirks.h"
  34
  35 /* xHCI PCI Configuration Registers */
  36 #define XHCI_SBRN_OFFSET        (0x60)
  37
  38 /* Max number of USB devices for any host controller - limit in section 6.1 */
  39 #define MAX_HC_SLOTS            256
  40 /* Section 5.3.3 - MaxPorts */
  41 #define MAX_HC_PORTS            127
  42
  43 /*
  44  * xHCI register interface.
  45  * This corresponds to the eXtensible Host Controller Interface (xHCI)
  46  * Revision 0.95 specification
  47  */
  48
  49 /**
  50  * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
  51  * @hc_capbase:         length of the capabilities register and HC version number
  52  * @hcs_params1:        HCSPARAMS1 - Structural Parameters 1
  53  * @hcs_params2:        HCSPARAMS2 - Structural Parameters 2
  54  * @hcs_params3:        HCSPARAMS3 - Structural Parameters 3
  55  * @hcc_params:         HCCPARAMS - Capability Parameters
  56  * @db_off:             DBOFF - Doorbell array offset
  57  * @run_regs_off:       RTSOFF - Runtime register space offset
  58  */
  59 struct xhci_cap_regs {
  60         __le32  hc_capbase;
  61         __le32  hcs_params1;
  62         __le32  hcs_params2;
  63         __le32  hcs_params3;
  64         __le32  hcc_params;
  65         __le32  db_off;
  66         __le32  run_regs_off;
  67         /* Reserved up to (CAPLENGTH - 0x1C) */
  68 };
  69
  70 /* hc_capbase bitmasks */
  71 /* bits 7:0 - how long is the Capabilities register */
  72 #define HC_LENGTH(p)            XHCI_HC_LENGTH(p)
  73 /* bits 31:16   */
  74 #define HC_VERSION(p)           (((p) >> 16) & 0xffff)
  75
  76 /* HCSPARAMS1 - hcs_params1 - bitmasks */
  77 /* bits 0:7, Max Device Slots */
  78 #define HCS_MAX_SLOTS(p)        (((p) >> 0) & 0xff)
  79 #define HCS_SLOTS_MASK          0xff
  80 /* bits 8:18, Max Interrupters */
  81 #define HCS_MAX_INTRS(p)        (((p) >> 8) & 0x7ff)
  82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
  83 #define HCS_MAX_PORTS(p)        (((p) >> 24) & 0x7f)
  84
  85 /* HCSPARAMS2 - hcs_params2 - bitmasks */
  86 /* bits 0:3, frames or uframes that SW needs to queue transactions
  87  * ahead of the HW to meet periodic deadlines */
  88 #define HCS_IST(p)              (((p) >> 0) & 0xf)
  89 /* bits 4:7, max number of Event Ring segments */
  90 #define HCS_ERST_MAX(p)         (((p) >> 4) & 0xf)
  91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
  92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
  93 #define HCS_MAX_SCRATCHPAD(p)   (((p) >> 27) & 0x1f)
  94
  95 /* HCSPARAMS3 - hcs_params3 - bitmasks */
  96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
  97 #define HCS_U1_LATENCY(p)       (((p) >> 0) & 0xff)
  98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
  99 #define HCS_U2_LATENCY(p)       (((p) >> 16) & 0xffff)
 100
 101 /* HCCPARAMS - hcc_params - bitmasks */
 102 /* true: HC can use 64-bit address pointers */
 103 #define HCC_64BIT_ADDR(p)       ((p) & (1 << 0))
 104 /* true: HC can do bandwidth negotiation */
 105 #define HCC_BANDWIDTH_NEG(p)    ((p) & (1 << 1))
 106 /* true: HC uses 64-byte Device Context structures
 107  * FIXME 64-byte context structures aren't supported yet.
 108  */
 109 #define HCC_64BYTE_CONTEXT(p)   ((p) & (1 << 2))
 110 /* true: HC has port power switches */
 111 #define HCC_PPC(p)              ((p) & (1 << 3))
 112 /* true: HC has port indicators */
 113 #define HCS_INDICATOR(p)        ((p) & (1 << 4))
 114 /* true: HC has Light HC Reset Capability */
 115 #define HCC_LIGHT_RESET(p)      ((p) & (1 << 5))
 116 /* true: HC supports latency tolerance messaging */
 117 #define HCC_LTC(p)              ((p) & (1 << 6))
 118 /* true: no secondary Stream ID Support */
 119 #define HCC_NSS(p)              ((p) & (1 << 7))
 120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
 121 #define HCC_MAX_PSA(p)          (1 << ((((p) >> 12) & 0xf) + 1))
 122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
 123 #define HCC_EXT_CAPS(p)         XHCI_HCC_EXT_CAPS(p)
 124
 125 /* db_off bitmask - bits 0:1 reserved */
 126 #define DBOFF_MASK      (~0x3)
 127
 128 /* run_regs_off bitmask - bits 0:4 reserved */
 129 #define RTSOFF_MASK     (~0x1f)
 130
 131
 132 /* Number of registers per port */
 133 #define NUM_PORT_REGS   4
 134
 135 /**
 136  * struct xhci_op_regs - xHCI Host Controller Operational Registers.
 137  * @command:            USBCMD - xHC command register
 138  * @status:             USBSTS - xHC status register
 139  * @page_size:          This indicates the page size that the host controller
 140  *                      supports.  If bit n is set, the HC supports a page size
 141  *                      of 2^(n+12), up to a 128MB page size.
 142  *                      4K is the minimum page size.
 143  * @cmd_ring:           CRP - 64-bit Command Ring Pointer
 144  * @dcbaa_ptr:          DCBAAP - 64-bit Device Context Base Address Array Pointer
 145  * @config_reg:         CONFIG - Configure Register
 146  * @port_status_base:   PORTSCn - base address for Port Status and Control
 147  *                      Each port has a Port Status and Control register,
 148  *                      followed by a Port Power Management Status and Control
 149  *                      register, a Port Link Info register, and a reserved
 150  *                      register.
 151  * @port_power_base:    PORTPMSCn - base address for
 152  *                      Port Power Management Status and Control
 153  * @port_link_base:     PORTLIn - base address for Port Link Info (current
 154  *                      Link PM state and control) for USB 2.1 and USB 3.0
 155  *                      devices.
 156  */
 157 struct xhci_op_regs {
 158         __le32  command;
 159         __le32  status;
 160         __le32  page_size;
 161         __le32  reserved1;
 162         __le32  reserved2;
 163         __le32  dev_notification;
 164         __le64  cmd_ring;
 165         /* rsvd: offset 0x20-2F */
 166         __le32  reserved3[4];
 167         __le64  dcbaa_ptr;
 168         __le32  config_reg;
 169         /* rsvd: offset 0x3C-3FF */
 170         __le32  reserved4[241];
 171         /* port 1 registers, which serve as a base address for other ports */
 172         __le32  port_status_base;
 173         __le32  port_power_base;
 174         __le32  port_link_base;
 175         __le32  reserved5;
 176         /* registers for ports 2-255 */
 177         __le32  reserved6[NUM_PORT_REGS*254];
 178 };
 179
 180 /* USBCMD - USB command - command bitmasks */
 181 /* start/stop HC execution - do not write unless HC is halted*/
 182 #define CMD_RUN         XHCI_CMD_RUN
 183 /* Reset HC - resets internal HC state machine and all registers (except
 184  * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
 185  * The xHCI driver must reinitialize the xHC after setting this bit.
 186  */
 187 #define CMD_RESET       (1 << 1)
 188 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
 189 #define CMD_EIE         XHCI_CMD_EIE
 190 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
 191 #define CMD_HSEIE       XHCI_CMD_HSEIE
 192 /* bits 4:6 are reserved (and should be preserved on writes). */
 193 /* light reset (port status stays unchanged) - reset completed when this is 0 */
 194 #define CMD_LRESET      (1 << 7)
 195 /* host controller save/restore state. */
 196 #define CMD_CSS         (1 << 8)
 197 #define CMD_CRS         (1 << 9)
 198 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
 199 #define CMD_EWE         XHCI_CMD_EWE
 200 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
 201  * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
 202  * '0' means the xHC can power it off if all ports are in the disconnect,
 203  * disabled, or powered-off state.
 204  */
 205 #define CMD_PM_INDEX    (1 << 11)
 206 /* bits 12:31 are reserved (and should be preserved on writes). */
 207
 208 /* IMAN - Interrupt Management Register */
 209 #define IMAN_IE         (1 << 1)
 210 #define IMAN_IP         (1 << 0)
 211
 212 /* USBSTS - USB status - status bitmasks */
 213 /* HC not running - set to 1 when run/stop bit is cleared. */
 214 #define STS_HALT        XHCI_STS_HALT
 215 /* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
 216 #define STS_FATAL       (1 << 2)
 217 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
 218 #define STS_EINT        (1 << 3)
 219 /* port change detect */
 220 #define STS_PORT        (1 << 4)
 221 /* bits 5:7 reserved and zeroed */
 222 /* save state status - '1' means xHC is saving state */
 223 #define STS_SAVE        (1 << 8)
 224 /* restore state status - '1' means xHC is restoring state */
 225 #define STS_RESTORE     (1 << 9)
 226 /* true: save or restore error */
 227 #define STS_SRE         (1 << 10)
 228 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
 229 #define STS_CNR         XHCI_STS_CNR
 230 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
 231 #define STS_HCE         (1 << 12)
 232 /* bits 13:31 reserved and should be preserved */
 233
 234 /*
 235  * DNCTRL - Device Notification Control Register - dev_notification bitmasks
 236  * Generate a device notification event when the HC sees a transaction with a
 237  * notification type that matches a bit set in this bit field.
 238  */
 239 #define DEV_NOTE_MASK           (0xffff)
 240 #define ENABLE_DEV_NOTE(x)      (1 << (x))
 241 /* Most of the device notification types should only be used for debug.
 242  * SW does need to pay attention to function wake notifications.
 243  */
 244 #define DEV_NOTE_FWAKE          ENABLE_DEV_NOTE(1)
 245
 246 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
 247 /* bit 0 is the command ring cycle state */
 248 /* stop ring operation after completion of the currently executing command */
 249 #define CMD_RING_PAUSE          (1 << 1)
 250 /* stop ring immediately - abort the currently executing command */
 251 #define CMD_RING_ABORT          (1 << 2)
 252 /* true: command ring is running */
 253 #define CMD_RING_RUNNING        (1 << 3)
 254 /* bits 4:5 reserved and should be preserved */
 255 /* Command Ring pointer - bit mask for the lower 32 bits. */
 256 #define CMD_RING_RSVD_BITS      (0x3f)
 257
 258 /* CONFIG - Configure Register - config_reg bitmasks */
 259 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
 260 #define MAX_DEVS(p)     ((p) & 0xff)
 261 /* bits 8:31 - reserved and should be preserved */
 262
 263 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
 264 /* true: device connected */
 265 #define PORT_CONNECT    (1 << 0)
 266 /* true: port enabled */
 267 #define PORT_PE         (1 << 1)
 268 /* bit 2 reserved and zeroed */
 269 /* true: port has an over-current condition */
 270 #define PORT_OC         (1 << 3)
 271 /* true: port reset signaling asserted */
 272 #define PORT_RESET      (1 << 4)
 273 /* Port Link State - bits 5:8
 274  * A read gives the current link PM state of the port,
 275  * a write with Link State Write Strobe set sets the link state.
 276  */
 277 #define PORT_PLS_MASK   (0xf << 5)
 278 #define XDEV_U0         (0x0 << 5)
 279 #define XDEV_U2         (0x2 << 5)
 280 #define XDEV_U3         (0x3 << 5)
 281 #define XDEV_RESUME     (0xf << 5)
 282 /* true: port has power (see HCC_PPC) */
 283 #define PORT_POWER      (1 << 9)
 284 /* bits 10:13 indicate device speed:
 285  * 0 - undefined speed - port hasn't be initialized by a reset yet
 286  * 1 - full speed
 287  * 2 - low speed
 288  * 3 - high speed
 289  * 4 - super speed
 290  * 5-15 reserved
 291  */
 292 #define DEV_SPEED_MASK          (0xf << 10)
 293 #define XDEV_FS                 (0x1 << 10)
 294 #define XDEV_LS                 (0x2 << 10)
 295 #define XDEV_HS                 (0x3 << 10)
 296 #define XDEV_SS                 (0x4 << 10)
 297 #define DEV_UNDEFSPEED(p)       (((p) & DEV_SPEED_MASK) == (0x0<<10))
 298 #define DEV_FULLSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_FS)
 299 #define DEV_LOWSPEED(p)         (((p) & DEV_SPEED_MASK) == XDEV_LS)
 300 #define DEV_HIGHSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_HS)
 301 #define DEV_SUPERSPEED(p)       (((p) & DEV_SPEED_MASK) == XDEV_SS)
 302 /* Bits 20:23 in the Slot Context are the speed for the device */
 303 #define SLOT_SPEED_FS           (XDEV_FS << 10)
 304 #define SLOT_SPEED_LS           (XDEV_LS << 10)
 305 #define SLOT_SPEED_HS           (XDEV_HS << 10)
 306 #define SLOT_SPEED_SS           (XDEV_SS << 10)
 307 /* Port Indicator Control */
 308 #define PORT_LED_OFF    (0 << 14)
 309 #define PORT_LED_AMBER  (1 << 14)
 310 #define PORT_LED_GREEN  (2 << 14)
 311 #define PORT_LED_MASK   (3 << 14)
 312 /* Port Link State Write Strobe - set this when changing link state */
 313 #define PORT_LINK_STROBE        (1 << 16)
 314 /* true: connect status change */
 315 #define PORT_CSC        (1 << 17)
 316 /* true: port enable change */
 317 #define PORT_PEC        (1 << 18)
 318 /* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
 319  * into an enabled state, and the device into the default state.  A "warm" reset
 320  * also resets the link, forcing the device through the link training sequence.
 321  * SW can also look at the Port Reset register to see when warm reset is done.
 322  */
 323 #define PORT_WRC        (1 << 19)
 324 /* true: over-current change */
 325 #define PORT_OCC        (1 << 20)
 326 /* true: reset change - 1 to 0 transition of PORT_RESET */
 327 #define PORT_RC         (1 << 21)
 328 /* port link status change - set on some port link state transitions:
 329  *  Transition                          Reason
 330  *  ------------------------------------------------------------------------------
 331  *  - U3 to Resume                      Wakeup signaling from a device
 332  *  - Resume to Recovery to U0          USB 3.0 device resume
 333  *  - Resume to U0                      USB 2.0 device resume
 334  *  - U3 to Recovery to U0              Software resume of USB 3.0 device complete
 335  *  - U3 to U0                          Software resume of USB 2.0 device complete
 336  *  - U2 to U0                          L1 resume of USB 2.1 device complete
 337  *  - U0 to U0 (???)                    L1 entry rejection by USB 2.1 device
 338  *  - U0 to disabled                    L1 entry error with USB 2.1 device
 339  *  - Any state to inactive             Error on USB 3.0 port
 340  */
 341 #define PORT_PLC        (1 << 22)
 342 /* port configure error change - port failed to configure its link partner */
 343 #define PORT_CEC        (1 << 23)
 344 /* Cold Attach Status - xHC can set this bit to report device attached during
 345  * Sx state. Warm port reset should be perfomed to clear this bit and move port
 346  * to connected state.
 347  */
 348 #define PORT_CAS        (1 << 24)
 349 /* wake on connect (enable) */
 350 #define PORT_WKCONN_E   (1 << 25)
 351 /* wake on disconnect (enable) */
 352 #define PORT_WKDISC_E   (1 << 26)
 353 /* wake on over-current (enable) */
 354 #define PORT_WKOC_E     (1 << 27)
 355 /* bits 28:29 reserved */
 356 /* true: device is removable - for USB 3.0 roothub emulation */
 357 #define PORT_DEV_REMOVE (1 << 30)
 358 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
 359 #define PORT_WR         (1 << 31)
 360
 361 /* We mark duplicate entries with -1 */
 362 #define DUPLICATE_ENTRY ((u8)(-1))
 363
 364 /* Port Power Management Status and Control - port_power_base bitmasks */
 365 /* Inactivity timer value for transitions into U1, in microseconds.
 366  * Timeout can be up to 127us.  0xFF means an infinite timeout.
 367  */
 368 #define PORT_U1_TIMEOUT(p)      ((p) & 0xff)
 369 #define PORT_U1_TIMEOUT_MASK    0xff
 370 /* Inactivity timer value for transitions into U2 */
 371 #define PORT_U2_TIMEOUT(p)      (((p) & 0xff) << 8)
 372 #define PORT_U2_TIMEOUT_MASK    (0xff << 8)
 373 /* Bits 24:31 for port testing */
 374
 375 /* USB2 Protocol PORTSPMSC */
 376 #define PORT_L1S_MASK           7
 377 #define PORT_L1S_SUCCESS        1
 378 #define PORT_RWE                (1 << 3)
 379 #define PORT_HIRD(p)            (((p) & 0xf) << 4)
 380 #define PORT_HIRD_MASK          (0xf << 4)
 381 #define PORT_L1DS(p)            (((p) & 0xff) << 8)
 382 #define PORT_HLE                (1 << 16)
 383
 384 /**
 385  * struct xhci_intr_reg - Interrupt Register Set
 386  * @irq_pending:        IMAN - Interrupt Management Register.  Used to enable
 387  *                      interrupts and check for pending interrupts.
 388  * @irq_control:        IMOD - Interrupt Moderation Register.
 389  *                      Used to throttle interrupts.
 390  * @erst_size:          Number of segments in the Event Ring Segment Table (ERST).
 391  * @erst_base:          ERST base address.
 392  * @erst_dequeue:       Event ring dequeue pointer.
 393  *
 394  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
 395  * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
 396  * multiple segments of the same size.  The HC places events on the ring and
 397  * "updates the Cycle bit in the TRBs to indicate to software the current
 398  * position of the Enqueue Pointer." The HCD (Linux) processes those events and
 399  * updates the dequeue pointer.
 400  */
 401 struct xhci_intr_reg {
 402         __le32  irq_pending;
 403         __le32  irq_control;
 404         __le32  erst_size;
 405         __le32  rsvd;
 406         __le64  erst_base;
 407         __le64  erst_dequeue;
 408 };
 409
 410 /* irq_pending bitmasks */
 411 #define ER_IRQ_PENDING(p)       ((p) & 0x1)
 412 /* bits 2:31 need to be preserved */
 413 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
 414 #define ER_IRQ_CLEAR(p)         ((p) & 0xfffffffe)
 415 #define ER_IRQ_ENABLE(p)        ((ER_IRQ_CLEAR(p)) | 0x2)
 416 #define ER_IRQ_DISABLE(p)       ((ER_IRQ_CLEAR(p)) & ~(0x2))
 417
 418 /* irq_control bitmasks */
 419 /* Minimum interval between interrupts (in 250ns intervals).  The interval
 420  * between interrupts will be longer if there are no events on the event ring.
 421  * Default is 4000 (1 ms).
 422  */
 423 #define ER_IRQ_INTERVAL_MASK    (0xffff)
 424 /* Counter used to count down the time to the next interrupt - HW use only */
 425 #define ER_IRQ_COUNTER_MASK     (0xffff << 16)
 426
 427 /* erst_size bitmasks */
 428 /* Preserve bits 16:31 of erst_size */
 429 #define ERST_SIZE_MASK          (0xffff << 16)
 430
 431 /* erst_dequeue bitmasks */
 432 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
 433  * where the current dequeue pointer lies.  This is an optional HW hint.
 434  */
 435 #define ERST_DESI_MASK          (0x7)
 436 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
 437  * a work queue (or delayed service routine)?
 438  */
 439 #define ERST_EHB                (1 << 3)
 440 #define ERST_PTR_MASK           (0xf)
 441
 442 /**
 443  * struct xhci_run_regs
 444  * @microframe_index:
 445  *              MFINDEX - current microframe number
 446  *
 447  * Section 5.5 Host Controller Runtime Registers:
 448  * "Software should read and write these registers using only Dword (32 bit)
 449  * or larger accesses"
 450  */
 451 struct xhci_run_regs {
 452         __le32                  microframe_index;
 453         __le32                  rsvd[7];
 454         struct xhci_intr_reg    ir_set[128];
 455 };
 456
 457 /**
 458  * struct doorbell_array
 459  *
 460  * Bits  0 -  7: Endpoint target
 461  * Bits  8 - 15: RsvdZ
 462  * Bits 16 - 31: Stream ID
 463  *
 464  * Section 5.6
 465  */
 466 struct xhci_doorbell_array {
 467         __le32  doorbell[256];
 468 };
 469
 470 #define DB_VALUE(ep, stream)    ((((ep) + 1) & 0xff) | ((stream) << 16))
 471 #define DB_VALUE_HOST           0x00000000
 472
 473 /**
 474  * struct xhci_protocol_caps
 475  * @revision:           major revision, minor revision, capability ID,
 476  *                      and next capability pointer.
 477  * @name_string:        Four ASCII characters to say which spec this xHC
 478  *                      follows, typically "USB ".
 479  * @port_info:          Port offset, count, and protocol-defined information.
 480  */
 481 struct xhci_protocol_caps {
 482         u32     revision;
 483         u32     name_string;
 484         u32     port_info;
 485 };
 486
 487 #define XHCI_EXT_PORT_MAJOR(x)  (((x) >> 24) & 0xff)
 488 #define XHCI_EXT_PORT_OFF(x)    ((x) & 0xff)
 489 #define XHCI_EXT_PORT_COUNT(x)  (((x) >> 8) & 0xff)
 490
 491 /**
 492  * struct xhci_container_ctx
 493  * @type: Type of context.  Used to calculated offsets to contained contexts.
 494  * @size: Size of the context data
 495  * @bytes: The raw context data given to HW
 496  * @dma: dma address of the bytes
 497  *
 498  * Represents either a Device or Input context.  Holds a pointer to the raw
 499  * memory used for the context (bytes) and dma address of it (dma).
 500  */
 501 struct xhci_container_ctx {
 502         unsigned type;
 503 #define XHCI_CTX_TYPE_DEVICE  0x1
 504 #define XHCI_CTX_TYPE_INPUT   0x2
 505
 506         int size;
 507
 508         u8 *bytes;
 509         dma_addr_t dma;
 510 };
 511
 512 /**
 513  * struct xhci_slot_ctx
 514  * @dev_info:   Route string, device speed, hub info, and last valid endpoint
 515  * @dev_info2:  Max exit latency for device number, root hub port number
 516  * @tt_info:    tt_info is used to construct split transaction tokens
 517  * @dev_state:  slot state and device address
 518  *
 519  * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
 520  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 521  * reserved at the end of the slot context for HC internal use.
 522  */
 523 struct xhci_slot_ctx {
 524         __le32  dev_info;
 525         __le32  dev_info2;
 526         __le32  tt_info;
 527         __le32  dev_state;
 528         /* offset 0x10 to 0x1f reserved for HC internal use */
 529         __le32  reserved[4];
 530 };
 531
 532 /* dev_info bitmasks */
 533 /* Route String - 0:19 */
 534 #define ROUTE_STRING_MASK       (0xfffff)
 535 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
 536 #define DEV_SPEED       (0xf << 20)
 537 /* bit 24 reserved */
 538 /* Is this LS/FS device connected through a HS hub? - bit 25 */
 539 #define DEV_MTT         (0x1 << 25)
 540 /* Set if the device is a hub - bit 26 */
 541 #define DEV_HUB         (0x1 << 26)
 542 /* Index of the last valid endpoint context in this device context - 27:31 */
 543 #define LAST_CTX_MASK   (0x1f << 27)
 544 #define LAST_CTX(p)     ((p) << 27)
 545 #define LAST_CTX_TO_EP_NUM(p)   (((p) >> 27) - 1)
 546 #define SLOT_FLAG       (1 << 0)
 547 #define EP0_FLAG        (1 << 1)
 548
 549 /* dev_info2 bitmasks */
 550 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
 551 #define MAX_EXIT        (0xffff)
 552 /* Root hub port number that is needed to access the USB device */
 553 #define ROOT_HUB_PORT(p)        (((p) & 0xff) << 16)
 554 #define DEVINFO_TO_ROOT_HUB_PORT(p)     (((p) >> 16) & 0xff)
 555 /* Maximum number of ports under a hub device */
 556 #define XHCI_MAX_PORTS(p)       (((p) & 0xff) << 24)
 557
 558 /* tt_info bitmasks */
 559 /*
 560  * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
 561  * The Slot ID of the hub that isolates the high speed signaling from
 562  * this low or full-speed device.  '0' if attached to root hub port.
 563  */
 564 #define TT_SLOT         (0xff)
 565 /*
 566  * The number of the downstream facing port of the high-speed hub
 567  * '0' if the device is not low or full speed.
 568  */
 569 #define TT_PORT         (0xff << 8)
 570 #define TT_THINK_TIME(p)        (((p) & 0x3) << 16)
 571
 572 /* dev_state bitmasks */
 573 /* USB device address - assigned by the HC */
 574 #define DEV_ADDR_MASK   (0xff)
 575 /* bits 8:26 reserved */
 576 /* Slot state */
 577 #define SLOT_STATE      (0x1f << 27)
 578 #define GET_SLOT_STATE(p)       (((p) & (0x1f << 27)) >> 27)
 579
 580 #define SLOT_STATE_DISABLED     0
 581 #define SLOT_STATE_ENABLED      SLOT_STATE_DISABLED
 582 #define SLOT_STATE_DEFAULT      1
 583 #define SLOT_STATE_ADDRESSED    2
 584 #define SLOT_STATE_CONFIGURED   3
 585
 586 /**
 587  * struct xhci_ep_ctx
 588  * @ep_info:    endpoint state, streams, mult, and interval information.
 589  * @ep_info2:   information on endpoint type, max packet size, max burst size,
 590  *              error count, and whether the HC will force an event for all
 591  *              transactions.
 592  * @deq:        64-bit ring dequeue pointer address.  If the endpoint only
 593  *              defines one stream, this points to the endpoint transfer ring.
 594  *              Otherwise, it points to a stream context array, which has a
 595  *              ring pointer for each flow.
 596  * @tx_info:
 597  *              Average TRB lengths for the endpoint ring and
 598  *              max payload within an Endpoint Service Interval Time (ESIT).
 599  *
 600  * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
 601  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 602  * reserved at the end of the endpoint context for HC internal use.
 603  */
 604 struct xhci_ep_ctx {
 605         __le32  ep_info;
 606         __le32  ep_info2;
 607         __le64  deq;
 608         __le32  tx_info;
 609         /* offset 0x14 - 0x1f reserved for HC internal use */
 610         __le32  reserved[3];
 611 };
 612
 613 /* ep_info bitmasks */
 614 /*
 615  * Endpoint State - bits 0:2
 616  * 0 - disabled
 617  * 1 - running
 618  * 2 - halted due to halt condition - ok to manipulate endpoint ring
 619  * 3 - stopped
 620  * 4 - TRB error
 621  * 5-7 - reserved
 622  */
 623 #define EP_STATE_MASK           (0xf)
 624 #define EP_STATE_DISABLED       0
 625 #define EP_STATE_RUNNING        1
 626 #define EP_STATE_HALTED         2
 627 #define EP_STATE_STOPPED        3
 628 #define EP_STATE_ERROR          4
 629 /* Mult - Max number of burtst within an interval, in EP companion desc. */
 630 #define EP_MULT(p)              (((p) & 0x3) << 8)
 631 #define CTX_TO_EP_MULT(p)       (((p) >> 8) & 0x3)
 632 /* bits 10:14 are Max Primary Streams */
 633 /* bit 15 is Linear Stream Array */
 634 /* Interval - period between requests to an endpoint - 125u increments. */
 635 #define EP_INTERVAL(p)          (((p) & 0xff) << 16)
 636 #define EP_INTERVAL_TO_UFRAMES(p)               (1 << (((p) >> 16) & 0xff))
 637 #define CTX_TO_EP_INTERVAL(p)   (((p) >> 16) & 0xff)
 638 #define EP_MAXPSTREAMS_MASK     (0x1f << 10)
 639 #define EP_MAXPSTREAMS(p)       (((p) << 10) & EP_MAXPSTREAMS_MASK)
 640 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
 641 #define EP_HAS_LSA              (1 << 15)
 642
 643 /* ep_info2 bitmasks */
 644 /*
 645  * Force Event - generate transfer events for all TRBs for this endpoint
 646  * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
 647  */
 648 #define FORCE_EVENT     (0x1)
 649 #define ERROR_COUNT(p)  (((p) & 0x3) << 1)
 650 #define CTX_TO_EP_TYPE(p)       (((p) >> 3) & 0x7)
 651 #define EP_TYPE(p)      ((p) << 3)
 652 #define ISOC_OUT_EP     1
 653 #define BULK_OUT_EP     2
 654 #define INT_OUT_EP      3
 655 #define CTRL_EP         4
 656 #define ISOC_IN_EP      5
 657 #define BULK_IN_EP      6
 658 #define INT_IN_EP       7
 659 /* bit 6 reserved */
 660 /* bit 7 is Host Initiate Disable - for disabling stream selection */
 661 #define MAX_BURST(p)    (((p)&0xff) << 8)
 662 #define CTX_TO_MAX_BURST(p)     (((p) >> 8) & 0xff)
 663 #define MAX_PACKET(p)   (((p)&0xffff) << 16)
 664 #define MAX_PACKET_MASK         (0xffff << 16)
 665 #define MAX_PACKET_DECODED(p)   (((p) >> 16) & 0xffff)
 666
 667 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
 668  * USB2.0 spec 9.6.6.
 669  */
 670 #define GET_MAX_PACKET(p)       ((p) & 0x7ff)
 671
 672 /* tx_info bitmasks */
 673 #define AVG_TRB_LENGTH_FOR_EP(p)        ((p) & 0xffff)
 674 #define MAX_ESIT_PAYLOAD_FOR_EP(p)      (((p) & 0xffff) << 16)
 675 #define CTX_TO_MAX_ESIT_PAYLOAD(p)      (((p) >> 16) & 0xffff)
 676
 677 /* deq bitmasks */
 678 #define EP_CTX_CYCLE_MASK               (1 << 0)
 679
 680
 681 /**
 682  * struct xhci_input_control_context
 683  * Input control context; see section 6.2.5.
 684  *
 685  * @drop_context:       set the bit of the endpoint context you want to disable
 686  * @add_context:        set the bit of the endpoint context you want to enable
 687  */
 688 struct xhci_input_control_ctx {
 689         __le32  drop_flags;
 690         __le32  add_flags;
 691         __le32  rsvd2[6];
 692 };
 693
 694 #define EP_IS_ADDED(ctrl_ctx, i) \
 695         (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
 696 #define EP_IS_DROPPED(ctrl_ctx, i)       \
 697         (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
 698
 699 /* Represents everything that is needed to issue a command on the command ring.
 700  * It's useful to pre-allocate these for commands that cannot fail due to
 701  * out-of-memory errors, like freeing streams.
 702  */
 703 struct xhci_command {
 704         /* Input context for changing device state */
 705         struct xhci_container_ctx       *in_ctx;
 706         u32                             status;
 707         /* If completion is null, no one is waiting on this command
 708          * and the structure can be freed after the command completes.
 709          */
 710         struct completion               *completion;
 711         union xhci_trb                  *command_trb;
 712         struct list_head                cmd_list;
 713 };
 714
 715 /* drop context bitmasks */
 716 #define DROP_EP(x)      (0x1 << x)
 717 /* add context bitmasks */
 718 #define ADD_EP(x)       (0x1 << x)
 719
 720 struct xhci_stream_ctx {
 721         /* 64-bit stream ring address, cycle state, and stream type */
 722         __le64  stream_ring;
 723         /* offset 0x14 - 0x1f reserved for HC internal use */
 724         __le32  reserved[2];
 725 };
 726
 727 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
 728 #define SCT_FOR_CTX(p)          (((p) << 1) & 0x7)
 729 /* Secondary stream array type, dequeue pointer is to a transfer ring */
 730 #define SCT_SEC_TR              0
 731 /* Primary stream array type, dequeue pointer is to a transfer ring */
 732 #define SCT_PRI_TR              1
 733 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
 734 #define SCT_SSA_8               2
 735 #define SCT_SSA_16              3
 736 #define SCT_SSA_32              4
 737 #define SCT_SSA_64              5
 738 #define SCT_SSA_128             6
 739 #define SCT_SSA_256             7
 740
 741 /* Assume no secondary streams for now */
 742 struct xhci_stream_info {
 743         struct xhci_ring                **stream_rings;
 744         /* Number of streams, including stream 0 (which drivers can't use) */
 745         unsigned int                    num_streams;
 746         /* The stream context array may be bigger than
 747          * the number of streams the driver asked for
 748          */
 749         struct xhci_stream_ctx          *stream_ctx_array;
 750         unsigned int                    num_stream_ctxs;
 751         dma_addr_t                      ctx_array_dma;
 752         /* For mapping physical TRB addresses to segments in stream rings */
 753         struct radix_tree_root          trb_address_map;
 754         struct xhci_command             *free_streams_command;
 755 };
 756
 757 #define SMALL_STREAM_ARRAY_SIZE         256
 758 #define MEDIUM_STREAM_ARRAY_SIZE        1024
 759
 760 /* Some Intel xHCI host controllers need software to keep track of the bus
 761  * bandwidth.  Keep track of endpoint info here.  Each root port is allocated
 762  * the full bus bandwidth.  We must also treat TTs (including each port under a
 763  * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
 764  * (DMI) also limits the total bandwidth (across all domains) that can be used.
 765  */
 766 struct xhci_bw_info {
 767         /* ep_interval is zero-based */
 768         unsigned int            ep_interval;
 769         /* mult and num_packets are one-based */
 770         unsigned int            mult;
 771         unsigned int            num_packets;
 772         unsigned int            max_packet_size;
 773         unsigned int            max_esit_payload;
 774         unsigned int            type;
 775 };
 776
 777 /* "Block" sizes in bytes the hardware uses for different device speeds.
 778  * The logic in this part of the hardware limits the number of bits the hardware
 779  * can use, so must represent bandwidth in a less precise manner to mimic what
 780  * the scheduler hardware computes.
 781  */
 782 #define FS_BLOCK        1
 783 #define HS_BLOCK        4
 784 #define SS_BLOCK        16
 785 #define DMI_BLOCK       32
 786
 787 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
 788  * with each byte transferred.  SuperSpeed devices have an initial overhead to
 789  * set up bursts.  These are in blocks, see above.  LS overhead has already been
 790  * translated into FS blocks.
 791  */
 792 #define DMI_OVERHEAD 8
 793 #define DMI_OVERHEAD_BURST 4
 794 #define SS_OVERHEAD 8
 795 #define SS_OVERHEAD_BURST 32
 796 #define HS_OVERHEAD 26
 797 #define FS_OVERHEAD 20
 798 #define LS_OVERHEAD 128
 799 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
 800  * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
 801  * of overhead associated with split transfers crossing microframe boundaries.
 802  * 31 blocks is pure protocol overhead.
 803  */
 804 #define TT_HS_OVERHEAD (31 + 94)
 805 #define TT_DMI_OVERHEAD (25 + 12)
 806
 807 /* Bandwidth limits in blocks */
 808 #define FS_BW_LIMIT             1285
 809 #define TT_BW_LIMIT             1320
 810 #define HS_BW_LIMIT             1607
 811 #define SS_BW_LIMIT_IN          3906
 812 #define DMI_BW_LIMIT_IN         3906
 813 #define SS_BW_LIMIT_OUT         3906
 814 #define DMI_BW_LIMIT_OUT        3906
 815
 816 /* Percentage of bus bandwidth reserved for non-periodic transfers */
 817 #define FS_BW_RESERVED          10
 818 #define HS_BW_RESERVED          20
 819 #define SS_BW_RESERVED          10
 820
 821 struct xhci_virt_ep {
 822         struct xhci_ring                *ring;
 823         /* Related to endpoints that are configured to use stream IDs only */
 824         struct xhci_stream_info         *stream_info;
 825         /* Temporary storage in case the configure endpoint command fails and we
 826          * have to restore the device state to the previous state
 827          */
 828         struct xhci_ring                *new_ring;
 829         unsigned int                    ep_state;
 830 #define SET_DEQ_PENDING         (1 << 0)
 831 #define EP_HALTED               (1 << 1)        /* For stall handling */
 832 #define EP_HALT_PENDING         (1 << 2)        /* For URB cancellation */
 833 /* Transitioning the endpoint to using streams, don't enqueue URBs */
 834 #define EP_GETTING_STREAMS      (1 << 3)
 835 #define EP_HAS_STREAMS          (1 << 4)
 836 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
 837 #define EP_GETTING_NO_STREAMS   (1 << 5)
 838         /* ----  Related to URB cancellation ---- */
 839         struct list_head        cancelled_td_list;
 840         /* The TRB that was last reported in a stopped endpoint ring */
 841         union xhci_trb          *stopped_trb;
 842         struct xhci_td          *stopped_td;
 843         unsigned int            stopped_stream;
 844         /* Watchdog timer for stop endpoint command to cancel URBs */
 845         struct timer_list       stop_cmd_timer;
 846         int                     stop_cmds_pending;
 847         struct xhci_hcd         *xhci;
 848         /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
 849          * command.  We'll need to update the ring's dequeue segment and dequeue
 850          * pointer after the command completes.
 851          */
 852         struct xhci_segment     *queued_deq_seg;
 853         union xhci_trb          *queued_deq_ptr;
 854         /*
 855          * Sometimes the xHC can not process isochronous endpoint ring quickly
 856          * enough, and it will miss some isoc tds on the ring and generate
 857          * a Missed Service Error Event.
 858          * Set skip flag when receive a Missed Service Error Event and
 859          * process the missed tds on the endpoint ring.
 860          */
 861         bool                    skip;
 862         /* Bandwidth checking storage */
 863         struct xhci_bw_info     bw_info;
 864         struct list_head        bw_endpoint_list;
 865 };
 866
 867 enum xhci_overhead_type {
 868         LS_OVERHEAD_TYPE = 0,
 869         FS_OVERHEAD_TYPE,
 870         HS_OVERHEAD_TYPE,
 871 };
 872
 873 struct xhci_interval_bw {
 874         unsigned int            num_packets;
 875         /* Sorted by max packet size.
 876          * Head of the list is the greatest max packet size.
 877          */
 878         struct list_head        endpoints;
 879         /* How many endpoints of each speed are present. */
 880         unsigned int            overhead[3];
 881 };
 882
 883 #define XHCI_MAX_INTERVAL       16
 884
 885 struct xhci_interval_bw_table {
 886         unsigned int            interval0_esit_payload;
 887         struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
 888         /* Includes reserved bandwidth for async endpoints */
 889         unsigned int            bw_used;
 890         unsigned int            ss_bw_in;
 891         unsigned int            ss_bw_out;
 892 };
 893
 894
 895 struct xhci_virt_device {
 896         struct usb_device               *udev;
 897         /*
 898          * Commands to the hardware are passed an "input context" that
 899          * tells the hardware what to change in its data structures.
 900          * The hardware will return changes in an "output context" that
 901          * software must allocate for the hardware.  We need to keep
 902          * track of input and output contexts separately because
 903          * these commands might fail and we don't trust the hardware.
 904          */
 905         struct xhci_container_ctx       *out_ctx;
 906         /* Used for addressing devices and configuration changes */
 907         struct xhci_container_ctx       *in_ctx;
 908         /* Rings saved to ensure old alt settings can be re-instated */
 909         struct xhci_ring                **ring_cache;
 910         int                             num_rings_cached;
 911         /* Store xHC assigned device address */
 912         int                             address;
 913 #define XHCI_MAX_RINGS_CACHED   31
 914         struct xhci_virt_ep             eps[31];
 915         struct completion               cmd_completion;
 916         /* Status of the last command issued for this device */
 917         u32                             cmd_status;
 918         struct list_head                cmd_list;
 919         u8                              fake_port;
 920         u8                              real_port;
 921         struct xhci_interval_bw_table   *bw_table;
 922         struct xhci_tt_bw_info          *tt_info;
 923         /* The current max exit latency for the enabled USB3 link states. */
 924         u16                             current_mel;
 925 };
 926
 927 /*
 928  * For each roothub, keep track of the bandwidth information for each periodic
 929  * interval.
 930  *
 931  * If a high speed hub is attached to the roothub, each TT associated with that
 932  * hub is a separate bandwidth domain.  The interval information for the
 933  * endpoints on the devices under that TT will appear in the TT structure.
 934  */
 935 struct xhci_root_port_bw_info {
 936         struct list_head                tts;
 937         unsigned int                    num_active_tts;
 938         struct xhci_interval_bw_table   bw_table;
 939 };
 940
 941 struct xhci_tt_bw_info {
 942         struct list_head                tt_list;
 943         int                             slot_id;
 944         int                             ttport;
 945         struct xhci_interval_bw_table   bw_table;
 946         int                             active_eps;
 947 };
 948
 949
 950 /**
 951  * struct xhci_device_context_array
 952  * @dev_context_ptr     array of 64-bit DMA addresses for device contexts
 953  */
 954 struct xhci_device_context_array {
 955         /* 64-bit device addresses; we only write 32-bit addresses */
 956         __le64                  dev_context_ptrs[MAX_HC_SLOTS];
 957         /* private xHCD pointers */
 958         dma_addr_t      dma;
 959 };
 960 /* TODO: write function to set the 64-bit device DMA address */
 961 /*
 962  * TODO: change this to be dynamically sized at HC mem init time since the HC
 963  * might not be able to handle the maximum number of devices possible.
 964  */
 965
 966
 967 struct xhci_transfer_event {
 968         /* 64-bit buffer address, or immediate data */
 969         __le64  buffer;
 970         __le32  transfer_len;
 971         /* This field is interpreted differently based on the type of TRB */
 972         __le32  flags;
 973 };
 974
 975 /* Transfer event TRB length bit mask */
 976 /* bits 0:23 */
 977 #define EVENT_TRB_LEN(p)                ((p) & 0xffffff)
 978
 979 /** Transfer Event bit fields **/
 980 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
 981
 982 /* Completion Code - only applicable for some types of TRBs */
 983 #define COMP_CODE_MASK          (0xff << 24)
 984 #define GET_COMP_CODE(p)        (((p) & COMP_CODE_MASK) >> 24)
 985 #define COMP_SUCCESS    1
 986 /* Data Buffer Error */
 987 #define COMP_DB_ERR     2
 988 /* Babble Detected Error */
 989 #define COMP_BABBLE     3
 990 /* USB Transaction Error */
 991 #define COMP_TX_ERR     4
 992 /* TRB Error - some TRB field is invalid */
 993 #define COMP_TRB_ERR    5
 994 /* Stall Error - USB device is stalled */
 995 #define COMP_STALL      6
 996 /* Resource Error - HC doesn't have memory for that device configuration */
 997 #define COMP_ENOMEM     7
 998 /* Bandwidth Error - not enough room in schedule for this dev config */
 999 #define COMP_BW_ERR     8
1000 /* No Slots Available Error - HC ran out of device slots */
1001 #define COMP_ENOSLOTS   9
1002 /* Invalid Stream Type Error */
1003 #define COMP_STREAM_ERR 10
1004 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1005 #define COMP_EBADSLT    11
1006 /* Endpoint Not Enabled Error */
1007 #define COMP_EBADEP     12
1008 /* Short Packet */
1009 #define COMP_SHORT_TX   13
1010 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1011 #define COMP_UNDERRUN   14
1012 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1013 #define COMP_OVERRUN    15
1014 /* Virtual Function Event Ring Full Error */
1015 #define COMP_VF_FULL    16
1016 /* Parameter Error - Context parameter is invalid */
1017 #define COMP_EINVAL     17
1018 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1019 #define COMP_BW_OVER    18
1020 /* Context State Error - illegal context state transition requested */
1021 #define COMP_CTX_STATE  19
1022 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1023 #define COMP_PING_ERR   20
1024 /* Event Ring is full */
1025 #define COMP_ER_FULL    21
1026 /* Incompatible Device Error */
1027 #define COMP_DEV_ERR    22
1028 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1029 #define COMP_MISSED_INT 23
1030 /* Successfully stopped command ring */
1031 #define COMP_CMD_STOP   24
1032 /* Successfully aborted current command and stopped command ring */
1033 #define COMP_CMD_ABORT  25
1034 /* Stopped - transfer was terminated by a stop endpoint command */
1035 #define COMP_STOP       26
1036 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1037 #define COMP_STOP_INVAL 27
1038 /* Control Abort Error - Debug Capability - control pipe aborted */
1039 #define COMP_DBG_ABORT  28
1040 /* Max Exit Latency Too Large Error */
1041 #define COMP_MEL_ERR    29
1042 /* TRB type 30 reserved */
1043 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1044 #define COMP_BUFF_OVER  31
1045 /* Event Lost Error - xHC has an "internal event overrun condition" */
1046 #define COMP_ISSUES     32
1047 /* Undefined Error - reported when other error codes don't apply */
1048 #define COMP_UNKNOWN    33
1049 /* Invalid Stream ID Error */
1050 #define COMP_STRID_ERR  34
1051 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1052 #define COMP_2ND_BW_ERR 35
1053 /* Split Transaction Error */
1054 #define COMP_SPLIT_ERR  36
1055
1056 struct xhci_link_trb {
1057         /* 64-bit segment pointer*/
1058         __le64 segment_ptr;
1059         __le32 intr_target;
1060         __le32 control;
1061 };
1062
1063 /* control bitfields */
1064 #define LINK_TOGGLE     (0x1<<1)
1065
1066 /* Command completion event TRB */
1067 struct xhci_event_cmd {
1068         /* Pointer to command TRB, or the value passed by the event data trb */
1069         __le64 cmd_trb;
1070         __le32 status;
1071         __le32 flags;
1072 };
1073
1074 /* flags bitmasks */
1075 /* bits 16:23 are the virtual function ID */
1076 /* bits 24:31 are the slot ID */
1077 #define TRB_TO_SLOT_ID(p)       (((p) & (0xff<<24)) >> 24)
1078 #define SLOT_ID_FOR_TRB(p)      (((p) & 0xff) << 24)
1079
1080 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1081 #define TRB_TO_EP_INDEX(p)              ((((p) & (0x1f << 16)) >> 16) - 1)
1082 #define EP_ID_FOR_TRB(p)                ((((p) + 1) & 0x1f) << 16)
1083
1084 #define SUSPEND_PORT_FOR_TRB(p)         (((p) & 1) << 23)
1085 #define TRB_TO_SUSPEND_PORT(p)          (((p) & (1 << 23)) >> 23)
1086 #define LAST_EP_INDEX                   30
1087
1088 /* Set TR Dequeue Pointer command TRB fields */
1089 #define TRB_TO_STREAM_ID(p)             ((((p) & (0xffff << 16)) >> 16))
1090 #define STREAM_ID_FOR_TRB(p)            ((((p)) & 0xffff) << 16)
1091
1092
1093 /* Port Status Change Event TRB fields */
1094 /* Port ID - bits 31:24 */
1095 #define GET_PORT_ID(p)          (((p) & (0xff << 24)) >> 24)
1096
1097 /* Normal TRB fields */
1098 /* transfer_len bitmasks - bits 0:16 */
1099 #define TRB_LEN(p)              ((p) & 0x1ffff)
1100 /* Interrupter Target - which MSI-X vector to target the completion event at */
1101 #define TRB_INTR_TARGET(p)      (((p) & 0x3ff) << 22)
1102 #define GET_INTR_TARGET(p)      (((p) >> 22) & 0x3ff)
1103 #define TRB_TBC(p)              (((p) & 0x3) << 7)
1104 #define TRB_TLBPC(p)            (((p) & 0xf) << 16)
1105
1106 /* Cycle bit - indicates TRB ownership by HC or HCD */
1107 #define TRB_CYCLE               (1<<0)
1108 /*
1109  * Force next event data TRB to be evaluated before task switch.
1110  * Used to pass OS data back after a TD completes.
1111  */
1112 #define TRB_ENT                 (1<<1)
1113 /* Interrupt on short packet */
1114 #define TRB_ISP                 (1<<2)
1115 /* Set PCIe no snoop attribute */
1116 #define TRB_NO_SNOOP            (1<<3)
1117 /* Chain multiple TRBs into a TD */
1118 #define TRB_CHAIN               (1<<4)
1119 /* Interrupt on completion */
1120 #define TRB_IOC                 (1<<5)
1121 /* The buffer pointer contains immediate data */
1122 #define TRB_IDT                 (1<<6)
1123
1124 /* Block Event Interrupt */
1125 #define TRB_BEI                 (1<<9)
1126
1127 /* Control transfer TRB specific fields */
1128 #define TRB_DIR_IN              (1<<16)
1129 #define TRB_TX_TYPE(p)          ((p) << 16)
1130 #define TRB_DATA_OUT            2
1131 #define TRB_DATA_IN             3
1132
1133 /* Isochronous TRB specific fields */
1134 #define TRB_SIA                 (1<<31)
1135
1136 struct xhci_generic_trb {
1137         __le32 field[4];
1138 };
1139
1140 union xhci_trb {
1141         struct xhci_link_trb            link;
1142         struct xhci_transfer_event      trans_event;
1143         struct xhci_event_cmd           event_cmd;
1144         struct xhci_generic_trb         generic;
1145 };
1146
1147 /* TRB bit mask */
1148 #define TRB_TYPE_BITMASK        (0xfc00)
1149 #define TRB_TYPE(p)             ((p) << 10)
1150 #define TRB_FIELD_TO_TYPE(p)    (((p) & TRB_TYPE_BITMASK) >> 10)
1151 /* TRB type IDs */
1152 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1153 #define TRB_NORMAL              1
1154 /* setup stage for control transfers */
1155 #define TRB_SETUP               2
1156 /* data stage for control transfers */
1157 #define TRB_DATA                3
1158 /* status stage for control transfers */
1159 #define TRB_STATUS              4
1160 /* isoc transfers */
1161 #define TRB_ISOC                5
1162 /* TRB for linking ring segments */
1163 #define TRB_LINK                6
1164 #define TRB_EVENT_DATA          7
1165 /* Transfer Ring No-op (not for the command ring) */
1166 #define TRB_TR_NOOP             8
1167 /* Command TRBs */
1168 /* Enable Slot Command */
1169 #define TRB_ENABLE_SLOT         9
1170 /* Disable Slot Command */
1171 #define TRB_DISABLE_SLOT        10
1172 /* Address Device Command */
1173 #define TRB_ADDR_DEV            11
1174 /* Configure Endpoint Command */
1175 #define TRB_CONFIG_EP           12
1176 /* Evaluate Context Command */
1177 #define TRB_EVAL_CONTEXT        13
1178 /* Reset Endpoint Command */
1179 #define TRB_RESET_EP            14
1180 /* Stop Transfer Ring Command */
1181 #define TRB_STOP_RING           15
1182 /* Set Transfer Ring Dequeue Pointer Command */
1183 #define TRB_SET_DEQ             16
1184 /* Reset Device Command */
1185 #define TRB_RESET_DEV           17
1186 /* Force Event Command (opt) */
1187 #define TRB_FORCE_EVENT         18
1188 /* Negotiate Bandwidth Command (opt) */
1189 #define TRB_NEG_BANDWIDTH       19
1190 /* Set Latency Tolerance Value Command (opt) */
1191 #define TRB_SET_LT              20
1192 /* Get port bandwidth Command */
1193 #define TRB_GET_BW              21
1194 /* Force Header Command - generate a transaction or link management packet */
1195 #define TRB_FORCE_HEADER        22
1196 /* No-op Command - not for transfer rings */
1197 #define TRB_CMD_NOOP            23
1198 /* TRB IDs 24-31 reserved */
1199 /* Event TRBS */
1200 /* Transfer Event */
1201 #define TRB_TRANSFER            32
1202 /* Command Completion Event */
1203 #define TRB_COMPLETION          33
1204 /* Port Status Change Event */
1205 #define TRB_PORT_STATUS         34
1206 /* Bandwidth Request Event (opt) */
1207 #define TRB_BANDWIDTH_EVENT     35
1208 /* Doorbell Event (opt) */
1209 #define TRB_DOORBELL            36
1210 /* Host Controller Event */
1211 #define TRB_HC_EVENT            37
1212 /* Device Notification Event - device sent function wake notification */
1213 #define TRB_DEV_NOTE            38
1214 /* MFINDEX Wrap Event - microframe counter wrapped */
1215 #define TRB_MFINDEX_WRAP        39
1216 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1217
1218 /* Nec vendor-specific command completion event. */
1219 #define TRB_NEC_CMD_COMP        48
1220 /* Get NEC firmware revision. */
1221 #define TRB_NEC_GET_FW          49
1222
1223 #define TRB_TYPE_LINK(x)        (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1224 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1225 #define TRB_TYPE_LINK_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1226                                  cpu_to_le32(TRB_TYPE(TRB_LINK)))
1227 #define TRB_TYPE_NOOP_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1228                                  cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1229
1230 #define NEC_FW_MINOR(p)         (((p) >> 0) & 0xff)
1231 #define NEC_FW_MAJOR(p)         (((p) >> 8) & 0xff)
1232
1233 /*
1234  * TRBS_PER_SEGMENT must be a multiple of 4,
1235  * since the command ring is 64-byte aligned.
1236  * It must also be greater than 16.
1237  */
1238 #define TRBS_PER_SEGMENT        64
1239 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1240 #define MAX_RSVD_CMD_TRBS       (TRBS_PER_SEGMENT - 3)
1241 #define TRB_SEGMENT_SIZE        (TRBS_PER_SEGMENT*16)
1242 #define TRB_SEGMENT_SHIFT       (ilog2(TRB_SEGMENT_SIZE))
1243 /* TRB buffer pointers can't cross 64KB boundaries */
1244 #define TRB_MAX_BUFF_SHIFT              16
1245 #define TRB_MAX_BUFF_SIZE       (1 << TRB_MAX_BUFF_SHIFT)
1246
1247 struct xhci_segment {
1248         union xhci_trb          *trbs;
1249         /* private to HCD */
1250         struct xhci_segment     *next;
1251         dma_addr_t              dma;
1252 };
1253
1254 struct xhci_td {
1255         struct list_head        td_list;
1256         struct list_head        cancelled_td_list;
1257         struct urb              *urb;
1258         struct xhci_segment     *start_seg;
1259         union xhci_trb          *first_trb;
1260         union xhci_trb          *last_trb;
1261 };
1262
1263 /* xHCI command default timeout value */
1264 #define XHCI_CMD_DEFAULT_TIMEOUT        (5 * HZ)
1265
1266 /* command descriptor */
1267 struct xhci_cd {
1268         struct list_head        cancel_cmd_list;
1269         struct xhci_command     *command;
1270         union xhci_trb          *cmd_trb;
1271 };
1272
1273 struct xhci_dequeue_state {
1274         struct xhci_segment *new_deq_seg;
1275         union xhci_trb *new_deq_ptr;
1276         int new_cycle_state;
1277 };
1278
1279 enum xhci_ring_type {
1280         TYPE_CTRL = 0,
1281         TYPE_ISOC,
1282         TYPE_BULK,
1283         TYPE_INTR,
1284         TYPE_STREAM,
1285         TYPE_COMMAND,
1286         TYPE_EVENT,
1287 };
1288
1289 struct xhci_ring {
1290         struct xhci_segment     *first_seg;
1291         struct xhci_segment     *last_seg;
1292         union  xhci_trb         *enqueue;
1293         struct xhci_segment     *enq_seg;
1294         unsigned int            enq_updates;
1295         union  xhci_trb         *dequeue;
1296         struct xhci_segment     *deq_seg;
1297         unsigned int            deq_updates;
1298         struct list_head        td_list;
1299         /*
1300          * Write the cycle state into the TRB cycle field to give ownership of
1301          * the TRB to the host controller (if we are the producer), or to check
1302          * if we own the TRB (if we are the consumer).  See section 4.9.1.
1303          */
1304         u32                     cycle_state;
1305         unsigned int            stream_id;
1306         unsigned int            num_segs;
1307         unsigned int            num_trbs_free;
1308         unsigned int            num_trbs_free_temp;
1309         enum xhci_ring_type     type;
1310         bool                    last_td_was_short;
1311 };
1312
1313 struct xhci_erst_entry {
1314         /* 64-bit event ring segment address */
1315         __le64  seg_addr;
1316         __le32  seg_size;
1317         /* Set to zero */
1318         __le32  rsvd;
1319 };
1320
1321 struct xhci_erst {
1322         struct xhci_erst_entry  *entries;
1323         unsigned int            num_entries;
1324         /* xhci->event_ring keeps track of segment dma addresses */
1325         dma_addr_t              erst_dma_addr;
1326         /* Num entries the ERST can contain */
1327         unsigned int            erst_size;
1328 };
1329
1330 struct xhci_scratchpad {
1331         u64 *sp_array;
1332         dma_addr_t sp_dma;
1333         void **sp_buffers;
1334         dma_addr_t *sp_dma_buffers;
1335 };
1336
1337 struct urb_priv {
1338         int     length;
1339         int     td_cnt;
1340         struct  xhci_td *td[0];
1341 };
1342
1343 /*
1344  * Each segment table entry is 4*32bits long.  1K seems like an ok size:
1345  * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1346  * meaning 64 ring segments.
1347  * Initial allocated size of the ERST, in number of entries */
1348 #define ERST_NUM_SEGS   1
1349 /* Initial allocated size of the ERST, in number of entries */
1350 #define ERST_SIZE       64
1351 /* Initial number of event segment rings allocated */
1352 #define ERST_ENTRIES    1
1353 /* Poll every 60 seconds */
1354 #define POLL_TIMEOUT    60
1355 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1356 #define XHCI_STOP_EP_CMD_TIMEOUT        5
1357 /* XXX: Make these module parameters */
1358
1359 struct s3_save {
1360         u32     command;
1361         u32     dev_nt;
1362         u64     dcbaa_ptr;
1363         u32     config_reg;
1364         u32     irq_pending;
1365         u32     irq_control;
1366         u32     erst_size;
1367         u64     erst_base;
1368         u64     erst_dequeue;
1369 };
1370
1371 /* Use for lpm */
1372 struct dev_info {
1373         u32                     dev_id;
1374         struct  list_head       list;
1375 };
1376
1377 struct xhci_bus_state {
1378         unsigned long           bus_suspended;
1379         unsigned long           next_statechange;
1380
1381         /* Port suspend arrays are indexed by the portnum of the fake roothub */
1382         /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1383         u32                     port_c_suspend;
1384         u32                     suspended_ports;
1385         u32                     port_remote_wakeup;
1386         unsigned long           resume_done[USB_MAXCHILDREN];
1387         /* which ports have started to resume */
1388         unsigned long           resuming_ports;
1389 };
1390
1391 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1392 {
1393         if (hcd->speed == HCD_USB3)
1394                 return 0;
1395         else
1396                 return 1;
1397 }
1398
1399 /* There is one xhci_hcd structure per controller */
1400 struct xhci_hcd {
1401         struct usb_hcd *main_hcd;
1402         struct usb_hcd *shared_hcd;
1403         /* glue to PCI and HCD framework */
1404         struct xhci_cap_regs __iomem *cap_regs;
1405         struct xhci_op_regs __iomem *op_regs;
1406         struct xhci_run_regs __iomem *run_regs;
1407         struct xhci_doorbell_array __iomem *dba;
1408         /* Our HCD's current interrupter register set */
1409         struct  xhci_intr_reg __iomem *ir_set;
1410
1411         /* Cached register copies of read-only HC data */
1412         __u32           hcs_params1;
1413         __u32           hcs_params2;
1414         __u32           hcs_params3;
1415         __u32           hcc_params;
1416
1417         spinlock_t      lock;
1418
1419         /* packed release number */
1420         u8              sbrn;
1421         u16             hci_version;
1422         u8              max_slots;
1423         u8              max_interrupters;
1424         u8              max_ports;
1425         u8              isoc_threshold;
1426         int             event_ring_max;
1427         int             addr_64;
1428         /* 4KB min, 128MB max */
1429         int             page_size;
1430         /* Valid values are 12 to 20, inclusive */
1431         int             page_shift;
1432         /* msi-x vectors */
1433         int             msix_count;
1434         struct msix_entry       *msix_entries;
1435         /* data structures */
1436         struct xhci_device_context_array *dcbaa;
1437         struct xhci_ring        *cmd_ring;
1438         unsigned int            cmd_ring_state;
1439 #define CMD_RING_STATE_RUNNING         (1 << 0)
1440 #define CMD_RING_STATE_ABORTED         (1 << 1)
1441 #define CMD_RING_STATE_STOPPED         (1 << 2)
1442         struct list_head        cancel_cmd_list;
1443         unsigned int            cmd_ring_reserved_trbs;
1444         struct xhci_ring        *event_ring;
1445         struct xhci_erst        erst;
1446         /* Scratchpad */
1447         struct xhci_scratchpad  *scratchpad;
1448         /* Store LPM test failed devices' information */
1449         struct list_head        lpm_failed_devs;
1450
1451         /* slot enabling and address device helpers */
1452         struct completion       addr_dev;
1453         int slot_id;
1454         /* For USB 3.0 LPM enable/disable. */
1455         struct xhci_command             *lpm_command;
1456         /* Internal mirror of the HW's dcbaa */
1457         struct xhci_virt_device *devs[MAX_HC_SLOTS];
1458         /* For keeping track of bandwidth domains per roothub. */
1459         struct xhci_root_port_bw_info   *rh_bw;
1460
1461         /* DMA pools */
1462         struct dma_pool *device_pool;
1463         struct dma_pool *segment_pool;
1464         struct dma_pool *small_streams_pool;
1465         struct dma_pool *medium_streams_pool;
1466
1467 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1468         /* Poll the rings - for debugging */
1469         struct timer_list       event_ring_timer;
1470         int                     zombie;
1471 #endif
1472         /* Host controller watchdog timer structures */
1473         unsigned int            xhc_state;
1474
1475         u32                     command;
1476         struct s3_save          s3;
1477 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1478  *
1479  * xHC interrupts have been disabled and a watchdog timer will (or has already)
1480  * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1481  * that sees this status (other than the timer that set it) should stop touching
1482  * hardware immediately.  Interrupt handlers should return immediately when
1483  * they see this status (any time they drop and re-acquire xhci->lock).
1484  * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1485  * putting the TD on the canceled list, etc.
1486  *
1487  * There are no reports of xHCI host controllers that display this issue.
1488  */
1489 #define XHCI_STATE_DYING        (1 << 0)
1490 #define XHCI_STATE_HALTED       (1 << 1)
1491         /* Statistics */
1492         int                     error_bitmask;
1493         unsigned int            quirks;
1494 #define XHCI_LINK_TRB_QUIRK     (1 << 0)
1495 #define XHCI_RESET_EP_QUIRK     (1 << 1)
1496 #define XHCI_NEC_HOST           (1 << 2)
1497 #define XHCI_AMD_PLL_FIX        (1 << 3)
1498 #define XHCI_SPURIOUS_SUCCESS   (1 << 4)
1499 /*
1500  * Certain Intel host controllers have a limit to the number of endpoint
1501  * contexts they can handle.  Ideally, they would signal that they can't handle
1502  * anymore endpoint contexts by returning a Resource Error for the Configure
1503  * Endpoint command, but they don't.  Instead they expect software to keep track
1504  * of the number of active endpoints for them, across configure endpoint
1505  * commands, reset device commands, disable slot commands, and address device
1506  * commands.
1507  */
1508 #define XHCI_EP_LIMIT_QUIRK     (1 << 5)
1509 #define XHCI_BROKEN_MSI         (1 << 6)
1510 #define XHCI_RESET_ON_RESUME    (1 << 7)
1511 #define XHCI_SW_BW_CHECKING     (1 << 8)
1512 #define XHCI_AMD_0x96_HOST      (1 << 9)
1513 #define XHCI_TRUST_TX_LENGTH    (1 << 10)
1514 #define XHCI_LPM_SUPPORT        (1 << 11)
1515 #define XHCI_INTEL_HOST         (1 << 12)
1516 #define XHCI_SPURIOUS_REBOOT    (1 << 13)
1517 #define XHCI_COMP_MODE_QUIRK    (1 << 14)
1518 #define XHCI_AVOID_BEI          (1 << 15)
1519         unsigned int            num_active_eps;
1520         unsigned int            limit_active_eps;
1521         /* There are two roothubs to keep track of bus suspend info for */
1522         struct xhci_bus_state   bus_state[2];
1523         /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1524         u8                      *port_array;
1525         /* Array of pointers to USB 3.0 PORTSC registers */
1526         __le32 __iomem          **usb3_ports;
1527         unsigned int            num_usb3_ports;
1528         /* Array of pointers to USB 2.0 PORTSC registers */
1529         __le32 __iomem          **usb2_ports;
1530         unsigned int            num_usb2_ports;
1531         /* support xHCI 0.96 spec USB2 software LPM */
1532         unsigned                sw_lpm_support:1;
1533         /* support xHCI 1.0 spec USB2 hardware LPM */
1534         unsigned                hw_lpm_support:1;
1535         /* cached usb2 extened protocol capabilites */
1536         u32                     *ext_caps;
1537         unsigned int            num_ext_caps;
1538         /* Compliance Mode Recovery Data */
1539         struct timer_list       comp_mode_recovery_timer;
1540         u32                     port_status_u0;
1541 /* Compliance Mode Timer Triggered every 2 seconds */
1542 #define COMP_MODE_RCVRY_MSECS 2000
1543 };
1544
1545 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1546 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1547 {
1548         return *((struct xhci_hcd **) (hcd->hcd_priv));
1549 }
1550
1551 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1552 {
1553         return xhci->main_hcd;
1554 }
1555
1556 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1557 #define XHCI_DEBUG      1
1558 #else
1559 #define XHCI_DEBUG      0
1560 #endif
1561
1562 #define xhci_dbg(xhci, fmt, args...) \
1563         do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1564 #define xhci_info(xhci, fmt, args...) \
1565         do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1566 #define xhci_err(xhci, fmt, args...) \
1567         dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1568 #define xhci_warn(xhci, fmt, args...) \
1569         dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1570 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1571         dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1572
1573 /* TODO: copied from ehci.h - can be refactored? */
1574 /* xHCI spec says all registers are little endian */
1575 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1576                 __le32 __iomem *regs)
1577 {
1578         return readl(regs);
1579 }
1580 static inline void xhci_writel(struct xhci_hcd *xhci,
1581                 const unsigned int val, __le32 __iomem *regs)
1582 {
1583         writel(val, regs);
1584 }
1585
1586 /*
1587  * Registers should always be accessed with double word or quad word accesses.
1588  *
1589  * Some xHCI implementations may support 64-bit address pointers.  Registers
1590  * with 64-bit address pointers should be written to with dword accesses by
1591  * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1592  * xHCI implementations that do not support 64-bit address pointers will ignore
1593  * the high dword, and write order is irrelevant.
1594  */
1595 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1596                 __le64 __iomem *regs)
1597 {
1598         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1599         u64 val_lo = readl(ptr);
1600         u64 val_hi = readl(ptr + 1);
1601         return val_lo + (val_hi << 32);
1602 }
1603 static inline void xhci_write_64(struct xhci_hcd *xhci,
1604                                  const u64 val, __le64 __iomem *regs)
1605 {
1606         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1607         u32 val_lo = lower_32_bits(val);
1608         u32 val_hi = upper_32_bits(val);
1609
1610         writel(val_lo, ptr);
1611         writel(val_hi, ptr + 1);
1612 }
1613
1614 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1615 {
1616         return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1617 }
1618
1619 /* xHCI debugging */
1620 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1621 void xhci_print_registers(struct xhci_hcd *xhci);
1622 void xhci_dbg_regs(struct xhci_hcd *xhci);
1623 void xhci_print_run_regs(struct xhci_hcd *xhci);
1624 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1625 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1626 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1627 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1628 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1629 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1630 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1631 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1632 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1633                 struct xhci_container_ctx *ctx);
1634 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1635                 unsigned int slot_id, unsigned int ep_index,
1636                 struct xhci_virt_ep *ep);
1637
1638 /* xHCI memory management */
1639 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1640 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1641 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1642 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1643 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1644 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1645                 struct usb_device *udev);
1646 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1647 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1648 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1649 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1650 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1651 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1652 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1653                 struct xhci_bw_info *ep_bw,
1654                 struct xhci_interval_bw_table *bw_table,
1655                 struct usb_device *udev,
1656                 struct xhci_virt_ep *virt_ep,
1657                 struct xhci_tt_bw_info *tt_info);
1658 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1659                 struct xhci_virt_device *virt_dev,
1660                 int old_active_eps);
1661 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1662 void xhci_update_bw_info(struct xhci_hcd *xhci,
1663                 struct xhci_container_ctx *in_ctx,
1664                 struct xhci_input_control_ctx *ctrl_ctx,
1665                 struct xhci_virt_device *virt_dev);
1666 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1667                 struct xhci_container_ctx *in_ctx,
1668                 struct xhci_container_ctx *out_ctx,
1669                 unsigned int ep_index);
1670 void xhci_slot_copy(struct xhci_hcd *xhci,
1671                 struct xhci_container_ctx *in_ctx,
1672                 struct xhci_container_ctx *out_ctx);
1673 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1674                 struct usb_device *udev, struct usb_host_endpoint *ep,
1675                 gfp_t mem_flags);
1676 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1677 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1678                                 unsigned int num_trbs, gfp_t flags);
1679 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1680                 struct xhci_virt_device *virt_dev,
1681                 unsigned int ep_index);
1682 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1683                 unsigned int num_stream_ctxs,
1684                 unsigned int num_streams, gfp_t flags);
1685 void xhci_free_stream_info(struct xhci_hcd *xhci,
1686                 struct xhci_stream_info *stream_info);
1687 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1688                 struct xhci_ep_ctx *ep_ctx,
1689                 struct xhci_stream_info *stream_info);
1690 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1691                 struct xhci_ep_ctx *ep_ctx,
1692                 struct xhci_virt_ep *ep);
1693 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1694         struct xhci_virt_device *virt_dev, bool drop_control_ep);
1695 struct xhci_ring *xhci_dma_to_transfer_ring(
1696                 struct xhci_virt_ep *ep,
1697                 u64 address);
1698 struct xhci_ring *xhci_stream_id_to_ring(
1699                 struct xhci_virt_device *dev,
1700                 unsigned int ep_index,
1701                 unsigned int stream_id);
1702 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1703                 bool allocate_in_ctx, bool allocate_completion,
1704                 gfp_t mem_flags);
1705 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1706 void xhci_free_command(struct xhci_hcd *xhci,
1707                 struct xhci_command *command);
1708
1709 #ifdef CONFIG_PCI
1710 /* xHCI PCI glue */
1711 int xhci_register_pci(void);
1712 void xhci_unregister_pci(void);
1713 #else
1714 static inline int xhci_register_pci(void) { return 0; }
1715 static inline void xhci_unregister_pci(void) {}
1716 #endif
1717
1718 #if defined(CONFIG_USB_XHCI_PLATFORM) \
1719         || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1720 int xhci_register_plat(void);
1721 void xhci_unregister_plat(void);
1722 #else
1723 static inline int xhci_register_plat(void)
1724 { return 0; }
1725 static inline void xhci_unregister_plat(void)
1726 {  }
1727 #endif
1728
1729 /* xHCI host controller glue */
1730 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1731 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1732                 u32 mask, u32 done, int usec);
1733 void xhci_quiesce(struct xhci_hcd *xhci);
1734 int xhci_halt(struct xhci_hcd *xhci);
1735 int xhci_reset(struct xhci_hcd *xhci);
1736 int xhci_init(struct usb_hcd *hcd);
1737 int xhci_run(struct usb_hcd *hcd);
1738 void xhci_stop(struct usb_hcd *hcd);
1739 void xhci_shutdown(struct usb_hcd *hcd);
1740 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1741
1742 #ifdef  CONFIG_PM
1743 int xhci_suspend(struct xhci_hcd *xhci);
1744 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1745 #else
1746 #define xhci_suspend    NULL
1747 #define xhci_resume     NULL
1748 #endif
1749
1750 int xhci_get_frame(struct usb_hcd *hcd);
1751 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1752 irqreturn_t xhci_msi_irq(int irq, void *hcd);
1753 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1754 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1755 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1756                 struct xhci_virt_device *virt_dev,
1757                 struct usb_device *hdev,
1758                 struct usb_tt *tt, gfp_t mem_flags);
1759 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1760                 struct usb_host_endpoint **eps, unsigned int num_eps,
1761                 unsigned int num_streams, gfp_t mem_flags);
1762 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1763                 struct usb_host_endpoint **eps, unsigned int num_eps,
1764                 gfp_t mem_flags);
1765 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1766 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1767 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1768                                 struct usb_device *udev, int enable);
1769 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1770                         struct usb_tt *tt, gfp_t mem_flags);
1771 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1772 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1773 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1774 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1775 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1776 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1777 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1778 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1779
1780 /* xHCI ring, segment, TRB, and TD functions */
1781 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1782 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1783                 union xhci_trb *start_trb, union xhci_trb *end_trb,
1784                 dma_addr_t suspect_dma);
1785 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1786 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1787 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1788 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1789                 u32 slot_id);
1790 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1791                 u32 field1, u32 field2, u32 field3, u32 field4);
1792 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1793                 unsigned int ep_index, int suspend);
1794 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1795                 int slot_id, unsigned int ep_index);
1796 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1797                 int slot_id, unsigned int ep_index);
1798 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1799                 int slot_id, unsigned int ep_index);
1800 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1801                 struct urb *urb, int slot_id, unsigned int ep_index);
1802 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1803                 u32 slot_id, bool command_must_succeed);
1804 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1805                 u32 slot_id, bool command_must_succeed);
1806 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1807                 unsigned int ep_index);
1808 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1809 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1810                 unsigned int slot_id, unsigned int ep_index,
1811                 unsigned int stream_id, struct xhci_td *cur_td,
1812                 struct xhci_dequeue_state *state);
1813 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1814                 unsigned int slot_id, unsigned int ep_index,
1815                 unsigned int stream_id,
1816                 struct xhci_dequeue_state *deq_state);
1817 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1818                 struct usb_device *udev, unsigned int ep_index);
1819 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1820                 unsigned int slot_id, unsigned int ep_index,
1821                 struct xhci_dequeue_state *deq_state);
1822 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1823 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
1824                 union xhci_trb *cmd_trb);
1825 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1826                 unsigned int ep_index, unsigned int stream_id);
1827
1828 /* xHCI roothub code */
1829 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1830                                 int port_id, u32 link_state);
1831 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1832                         struct usb_device *udev, enum usb3_link_state state);
1833 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1834                         struct usb_device *udev, enum usb3_link_state state);
1835 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1836                                 int port_id, u32 port_bit);
1837 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1838                 char *buf, u16 wLength);
1839 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1840 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1841
1842 #ifdef CONFIG_PM
1843 int xhci_bus_suspend(struct usb_hcd *hcd);
1844 int xhci_bus_resume(struct usb_hcd *hcd);
1845 #else
1846 #define xhci_bus_suspend        NULL
1847 #define xhci_bus_resume         NULL
1848 #endif  /* CONFIG_PM */
1849
1850 u32 xhci_port_state_to_neutral(u32 state);
1851 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1852                 u16 port);
1853 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1854
1855 /* xHCI contexts */
1856 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1857 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1858 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1859
1860 #endif /* __LINUX_XHCI_HCD_H */