2 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
3 * Copyright (C) 2005 Mips Technologies, Inc
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
8 #include <linux/cpumask.h>
9 #include <linux/interrupt.h>
10 #include <linux/security.h>
13 #include <asm/processor.h>
14 #include <asm/atomic.h>
15 #include <asm/system.h>
16 #include <asm/hardirq.h>
17 #include <asm/mmu_context.h>
19 #include <asm/mipsmtregs.h>
20 #include <asm/r4kcache.h>
21 #include <asm/cacheflush.h>
24 * CPU mask used to set process affinity for MT VPEs/TCs with FPUs
27 cpumask_t mt_fpu_cpumask
;
29 #ifdef CONFIG_MIPS_MT_FPAFF
31 #include <linux/cpu.h>
32 #include <linux/delay.h>
33 #include <asm/uaccess.h>
35 unsigned long mt_fpemul_threshold
= 0;
38 * Replacement functions for the sys_sched_setaffinity() and
39 * sys_sched_getaffinity() system calls, so that we can integrate
40 * FPU affinity with the user's requested processor affinity.
41 * This code is 98% identical with the sys_sched_setaffinity()
42 * and sys_sched_getaffinity() system calls, and should be
43 * updated when kernel/sched.c changes.
47 * find_process_by_pid - find a process with a matching PID value.
48 * used in sys_sched_set/getaffinity() in kernel/sched.c, so
51 static inline struct task_struct
*find_process_by_pid(pid_t pid
)
53 return pid
? find_task_by_pid(pid
) : current
;
58 * mipsmt_sys_sched_setaffinity - set the cpu affinity of a process
60 asmlinkage
long mipsmt_sys_sched_setaffinity(pid_t pid
, unsigned int len
,
61 unsigned long __user
*user_mask_ptr
)
64 cpumask_t effective_mask
;
66 struct task_struct
*p
;
68 if (len
< sizeof(new_mask
))
71 if (copy_from_user(&new_mask
, user_mask_ptr
, sizeof(new_mask
)))
75 read_lock(&tasklist_lock
);
77 p
= find_process_by_pid(pid
);
79 read_unlock(&tasklist_lock
);
85 * It is not safe to call set_cpus_allowed with the
86 * tasklist_lock held. We will bump the task_struct's
87 * usage count and drop tasklist_lock before invoking
93 if ((current
->euid
!= p
->euid
) && (current
->euid
!= p
->uid
) &&
94 !capable(CAP_SYS_NICE
)) {
95 read_unlock(&tasklist_lock
);
99 /* Record new user-specified CPU set for future reference */
100 p
->thread
.user_cpus_allowed
= new_mask
;
102 /* Unlock the task list */
103 read_unlock(&tasklist_lock
);
105 /* Compute new global allowed CPU set if necessary */
106 if( (p
->thread
.mflags
& MF_FPUBOUND
)
107 && cpus_intersects(new_mask
, mt_fpu_cpumask
)) {
108 cpus_and(effective_mask
, new_mask
, mt_fpu_cpumask
);
109 retval
= set_cpus_allowed(p
, effective_mask
);
111 p
->thread
.mflags
&= ~MF_FPUBOUND
;
112 retval
= set_cpus_allowed(p
, new_mask
);
118 unlock_cpu_hotplug();
123 * mipsmt_sys_sched_getaffinity - get the cpu affinity of a process
125 asmlinkage
long mipsmt_sys_sched_getaffinity(pid_t pid
, unsigned int len
,
126 unsigned long __user
*user_mask_ptr
)
128 unsigned int real_len
;
131 struct task_struct
*p
;
133 real_len
= sizeof(mask
);
138 read_lock(&tasklist_lock
);
141 p
= find_process_by_pid(pid
);
147 cpus_and(mask
, p
->thread
.user_cpus_allowed
, cpu_possible_map
);
150 read_unlock(&tasklist_lock
);
151 unlock_cpu_hotplug();
154 if (copy_to_user(user_mask_ptr
, &mask
, real_len
))
159 #endif /* CONFIG_MIPS_MT_FPAFF */
162 * Dump new MIPS MT state for the core. Does not leave TCs halted.
163 * Takes an argument which taken to be a pre-call MVPControl value.
166 void mips_mt_regdump(unsigned long mvpctl
)
169 unsigned long vpflags
;
170 unsigned long mvpconf0
;
175 unsigned long haltval
;
176 unsigned long tcstatval
;
177 #ifdef CONFIG_MIPS_MT_SMTC
178 void smtc_soft_dump(void);
179 #endif /* CONFIG_MIPT_MT_SMTC */
181 local_irq_save(flags
);
183 printk("=== MIPS MT State Dump ===\n");
184 printk("-- Global State --\n");
185 printk(" MVPControl Passed: %08lx\n", mvpctl
);
186 printk(" MVPControl Read: %08lx\n", vpflags
);
187 printk(" MVPConf0 : %08lx\n", (mvpconf0
= read_c0_mvpconf0()));
188 nvpe
= ((mvpconf0
& MVPCONF0_PVPE
) >> MVPCONF0_PVPE_SHIFT
) + 1;
189 ntc
= ((mvpconf0
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
190 printk("-- per-VPE State --\n");
191 for(i
= 0; i
< nvpe
; i
++) {
192 for(tc
= 0; tc
< ntc
; tc
++) {
194 if((read_tc_c0_tcbind() & TCBIND_CURVPE
) == i
) {
195 printk(" VPE %d\n", i
);
196 printk(" VPEControl : %08lx\n", read_vpe_c0_vpecontrol());
197 printk(" VPEConf0 : %08lx\n", read_vpe_c0_vpeconf0());
198 printk(" VPE%d.Status : %08lx\n",
199 i
, read_vpe_c0_status());
200 printk(" VPE%d.EPC : %08lx\n", i
, read_vpe_c0_epc());
201 printk(" VPE%d.Cause : %08lx\n", i
, read_vpe_c0_cause());
202 printk(" VPE%d.Config7 : %08lx\n",
203 i
, read_vpe_c0_config7());
204 break; /* Next VPE */
208 printk("-- per-TC State --\n");
209 for(tc
= 0; tc
< ntc
; tc
++) {
211 if(read_tc_c0_tcbind() == read_c0_tcbind()) {
212 /* Are we dumping ourself? */
213 haltval
= 0; /* Then we're not halted, and mustn't be */
214 tcstatval
= flags
; /* And pre-dump TCStatus is flags */
215 printk(" TC %d (current TC with VPE EPC above)\n", tc
);
217 haltval
= read_tc_c0_tchalt();
218 write_tc_c0_tchalt(1);
219 tcstatval
= read_tc_c0_tcstatus();
220 printk(" TC %d\n", tc
);
222 printk(" TCStatus : %08lx\n", tcstatval
);
223 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
224 printk(" TCRestart : %08lx\n", read_tc_c0_tcrestart());
225 printk(" TCHalt : %08lx\n", haltval
);
226 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
228 write_tc_c0_tchalt(0);
230 #ifdef CONFIG_MIPS_MT_SMTC
232 #endif /* CONFIG_MIPT_MT_SMTC */
233 printk("===========================\n");
235 local_irq_restore(flags
);
238 static int mt_opt_norps
= 0;
239 static int mt_opt_rpsctl
= -1;
240 static int mt_opt_nblsu
= -1;
241 static int mt_opt_forceconfig7
= 0;
242 static int mt_opt_config7
= -1;
244 static int __init
rps_disable(char *s
)
249 __setup("norps", rps_disable
);
251 static int __init
rpsctl_set(char *str
)
253 get_option(&str
, &mt_opt_rpsctl
);
256 __setup("rpsctl=", rpsctl_set
);
258 static int __init
nblsu_set(char *str
)
260 get_option(&str
, &mt_opt_nblsu
);
263 __setup("nblsu=", nblsu_set
);
265 static int __init
config7_set(char *str
)
267 get_option(&str
, &mt_opt_config7
);
268 mt_opt_forceconfig7
= 1;
271 __setup("config7=", config7_set
);
273 /* Experimental cache flush control parameters that should go away some day */
274 int mt_protiflush
= 0;
275 int mt_protdflush
= 0;
276 int mt_n_iflushes
= 1;
277 int mt_n_dflushes
= 1;
279 static int __init
set_protiflush(char *s
)
284 __setup("protiflush", set_protiflush
);
286 static int __init
set_protdflush(char *s
)
291 __setup("protdflush", set_protdflush
);
293 static int __init
niflush(char *s
)
295 get_option(&s
, &mt_n_iflushes
);
298 __setup("niflush=", niflush
);
300 static int __init
ndflush(char *s
)
302 get_option(&s
, &mt_n_dflushes
);
305 __setup("ndflush=", ndflush
);
306 #ifdef CONFIG_MIPS_MT_FPAFF
307 static int fpaff_threshold
= -1;
309 static int __init
fpaff_thresh(char *str
)
311 get_option(&str
, &fpaff_threshold
);
315 __setup("fpaff=", fpaff_thresh
);
316 #endif /* CONFIG_MIPS_MT_FPAFF */
318 static unsigned int itc_base
= 0;
320 static int __init
set_itc_base(char *str
)
322 get_option(&str
, &itc_base
);
326 __setup("itcbase=", set_itc_base
);
328 void mips_mt_set_cpuoptions(void)
330 unsigned int oconfig7
= read_c0_config7();
331 unsigned int nconfig7
= oconfig7
;
334 printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
336 if (mt_opt_rpsctl
>= 0) {
337 printk("34K return prediction stack override set to %d.\n",
340 nconfig7
|= (1 << 2);
342 nconfig7
&= ~(1 << 2);
344 if (mt_opt_nblsu
>= 0) {
345 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu
);
347 nconfig7
|= (1 << 5);
349 nconfig7
&= ~(1 << 5);
351 if (mt_opt_forceconfig7
) {
352 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7
);
353 nconfig7
= mt_opt_config7
;
355 if (oconfig7
!= nconfig7
) {
356 __asm__
__volatile("sync");
357 write_c0_config7(nconfig7
);
359 printk("Config7: 0x%08x\n", read_c0_config7());
362 /* Report Cache management debug options */
364 printk("I-cache flushes single-threaded\n");
366 printk("D-cache flushes single-threaded\n");
367 if (mt_n_iflushes
!= 1)
368 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes
);
369 if (mt_n_dflushes
!= 1)
370 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes
);
372 #ifdef CONFIG_MIPS_MT_FPAFF
373 /* FPU Use Factor empirically derived from experiments on 34K */
374 #define FPUSEFACTOR 333
376 if (fpaff_threshold
>= 0) {
377 mt_fpemul_threshold
= fpaff_threshold
;
379 mt_fpemul_threshold
=
380 (FPUSEFACTOR
* (loops_per_jiffy
/(500000/HZ
))) / HZ
;
382 printk("FPU Affinity set after %ld emulations\n",
383 mt_fpemul_threshold
);
384 #endif /* CONFIG_MIPS_MT_FPAFF */
388 * Configure ITC mapping. This code is very
389 * specific to the 34K core family, which uses
390 * a special mode bit ("ITC") in the ErrCtl
391 * register to enable access to ITC control
392 * registers via cache "tag" operations.
394 unsigned long ectlval
;
395 unsigned long itcblkgrn
;
397 /* ErrCtl register is known as "ecc" to Linux */
398 ectlval
= read_c0_ecc();
399 write_c0_ecc(ectlval
| (0x1 << 26));
401 #define INDEX_0 (0x80000000)
402 #define INDEX_8 (0x80000008)
403 /* Read "cache tag" for Dcache pseudo-index 8 */
404 cache_op(Index_Load_Tag_D
, INDEX_8
);
406 itcblkgrn
= read_c0_dtaglo();
407 itcblkgrn
&= 0xfffe0000;
408 /* Set for 128 byte pitch of ITC cells */
409 itcblkgrn
|= 0x00000c00;
410 /* Stage in Tag register */
411 write_c0_dtaglo(itcblkgrn
);
413 /* Write out to ITU with CACHE op */
414 cache_op(Index_Store_Tag_D
, INDEX_8
);
415 /* Now set base address, and turn ITC on with 0x1 bit */
416 write_c0_dtaglo((itc_base
& 0xfffffc00) | 0x1 );
418 /* Write out to ITU with CACHE op */
419 cache_op(Index_Store_Tag_D
, INDEX_0
);
420 write_c0_ecc(ectlval
);
422 printk("Mapped %ld ITC cells starting at 0x%08x\n",
423 ((itcblkgrn
& 0x7fe00000) >> 20), itc_base
);
428 * Function to protect cache flushes from concurrent execution
429 * depends on MP software model chosen.
432 void mt_cflush_lockdown(void)
434 #ifdef CONFIG_MIPS_MT_SMTC
435 void smtc_cflush_lockdown(void);
437 smtc_cflush_lockdown();
438 #endif /* CONFIG_MIPS_MT_SMTC */
439 /* FILL IN VSMP and AP/SP VERSIONS HERE */
442 void mt_cflush_release(void)
444 #ifdef CONFIG_MIPS_MT_SMTC
445 void smtc_cflush_release(void);
447 smtc_cflush_release();
448 #endif /* CONFIG_MIPS_MT_SMTC */
449 /* FILL IN VSMP and AP/SP VERSIONS HERE */